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00039 #ifndef _EDMA3_RM_H_
00040 #define _EDMA3_RM_H_
00041
00043 #include <ti/sdo/edma3/rm/edma3_common.h>
00044
00045 #ifdef __cplusplus
00046 extern "C" {
00047 #endif
00048
00049
00050
00083 typedef enum
00084 {
00089 EDMA3_RM_XFER_COMPLETE = 1,
00090
00096 EDMA3_RM_E_CC_DMA_EVT_MISS = 2,
00097
00102 EDMA3_RM_E_CC_QDMA_EVT_MISS = 3
00103
00104 } EDMA3_RM_TccStatus;
00105
00106
00107
00112 typedef enum
00113 {
00120 EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1,
00121
00127 EDMA3_RM_E_CC_TCC = 2,
00128
00133 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3,
00134
00138 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4,
00139
00144 EDMA3_RM_E_TC_INVALID_ADDR = 5,
00145
00151 EDMA3_RM_E_TC_TR_ERROR = 6
00152 } EDMA3_RM_GlobalError;
00153
00154
00155
00156
00157
00164 typedef void (* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus,
00165 unsigned int instanceId,
00166 void *gblerrData);
00167
00173 typedef struct {
00177 EDMA3_RM_GblErrCallback gblerrCb;
00178
00180 void *gblerrData;
00181
00182 } EDMA3_RM_GblErrCallbackParams;
00183
00184
00185
00186
00202 typedef void (* EDMA3_RM_TccCallback)(unsigned int tcc,
00203 EDMA3_RM_TccStatus status,
00204 void *appData);
00205
00206
00218 #define EDMA3_RM_RES_ANY (1010u)
00219
00220
00224 typedef enum
00225 {
00227 EDMA3_RM_RES_DMA_CHANNEL = 1,
00228
00230 EDMA3_RM_RES_QDMA_CHANNEL = 2,
00231
00233 EDMA3_RM_RES_TCC = 3,
00234
00236 EDMA3_RM_RES_PARAM_SET = 4
00237
00238 } EDMA3_RM_ResType;
00239
00240
00244 typedef struct
00245 {
00254 unsigned int resId;
00255
00257 EDMA3_RM_ResType type;
00258 } EDMA3_RM_ResDesc;
00259
00260
00261
00262
00294 EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
00295 const EDMA3_RM_ResDesc *channelObj,
00296 unsigned int tcc,
00297 EDMA3_RM_TccCallback tccCb,
00298 void *cbData);
00299
00300
00326 EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr,
00327 const EDMA3_RM_ResDesc *channelObj);
00328
00329
00330
00331
00332
00333
00334
00344
00345
00346
00347
00604
00605
00606
00607
00608
00609
00610
00620 #define EDMA3_RM_E_BASE (-155)
00621
00626 #define EDMA3_RM_E_OBJ_NOT_DELETED (EDMA3_RM_E_BASE)
00627
00632 #define EDMA3_RM_E_OBJ_NOT_CLOSED (EDMA3_RM_E_BASE-1)
00633
00638 #define EDMA3_RM_E_OBJ_NOT_OPENED (EDMA3_RM_E_BASE-2)
00639
00641 #define EDMA3_RM_E_INVALID_PARAM (EDMA3_RM_E_BASE-3)
00642
00644 #define EDMA3_RM_E_RES_ALREADY_FREE (EDMA3_RM_E_BASE-4)
00645
00647 #define EDMA3_RM_E_RES_NOT_OWNED (EDMA3_RM_E_BASE-5)
00648
00650 #define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-6)
00651
00653 #define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-7)
00654
00656 #define EDMA3_RM_E_INVALID_STATE (EDMA3_RM_E_BASE-8)
00657
00659 #define EDMA3_RM_E_MAX_RM_INST_OPENED (EDMA3_RM_E_BASE-9)
00660
00665 #define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS (EDMA3_RM_E_BASE-10)
00666
00668 #define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED (EDMA3_RM_E_BASE-11)
00669
00671 #define EDMA3_RM_E_SEMAPHORE (EDMA3_RM_E_BASE-12)
00672
00674 #define EDMA3_RM_E_FEATURE_UNSUPPORTED (EDMA3_RM_E_BASE-13)
00675
00677 #define EDMA3_RM_E_RES_NOT_ALLOCATED (EDMA3_RM_E_BASE-14)
00678
00679
00680
00681
00682
00683
00689 typedef unsigned int EDMA3_RM_RegionId;
00690
00698 typedef unsigned int EDMA3_RM_EventQueue;
00699
00700
00701
00718 typedef struct {
00720 unsigned int numDmaChannels;
00721
00723 unsigned int numQdmaChannels;
00724
00729 unsigned int numTccs;
00730
00732 unsigned int numPaRAMSets;
00733
00735 unsigned int numEvtQueue;
00736
00740 unsigned int numTcs;
00741
00743 unsigned int numRegions;
00744
00758 unsigned short dmaChPaRAMMapExists;
00759
00761 unsigned short memProtectionExists;
00762
00764 void *globalRegs;
00765
00767 void *tcRegs[EDMA3_MAX_TC];
00768
00773 unsigned int xferCompleteInt;
00774
00776 unsigned int ccError;
00777
00779 unsigned int tcError[EDMA3_MAX_TC];
00780
00790 unsigned int evtQPri [EDMA3_MAX_EVT_QUE];
00791
00802 unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
00803
00811 unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];
00812
00824 unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
00825
00835 unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];
00836
00849 unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
00850 } EDMA3_RM_GblConfigParams;
00851
00852
00853
00917 typedef struct
00918 {
00920 unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00921
00923 unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00924
00926 unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00927
00929 unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];
00930
00938 unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00939
00947 unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00948
00956 unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00957
00965 unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];
00966 }EDMA3_RM_InstanceInitConfig;
00967
00968
00969
00976 typedef struct {
00978 EDMA3_RM_RegionId regionId;
00979
00985 unsigned short isMaster;
00986
00995 EDMA3_RM_InstanceInitConfig *rmInstInitConfig;
00996
01002 void *rmSemHandle;
01003
01007 unsigned short regionInitEnable;
01008
01010 EDMA3_RM_GblErrCallbackParams gblerrCbParams;
01011 } EDMA3_RM_Param;
01012
01013
01014
01023 typedef struct {
01030 unsigned short isSlave;
01031
01033 unsigned short param;
01034 }EDMA3_RM_MiscParam;
01035
01036
01037
01038
01073 EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
01074 const EDMA3_RM_GblConfigParams *gblCfgParams,
01075 const void *miscParam);
01076
01077
01095 EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
01096 const void *param);
01097
01098
01099
01138 EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
01139 const EDMA3_RM_Param *initParam,
01140 EDMA3_RM_Result *errorCode);
01141
01142
01143
01161 EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
01162 const void *param);
01163
01164
01165
01166
01167
01168
01225 EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr,
01226 EDMA3_RM_ResDesc *resObj);
01227
01228
01229
01253 EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
01254 const EDMA3_RM_ResDesc *resObj);
01255
01256
01257
01315 EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
01316 EDMA3_RM_ResDesc *firstResIdObj,
01317 unsigned int numResources);
01318
01319
01320
01350 EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
01351 EDMA3_RM_ResDesc *firstResIdObj,
01352 unsigned int numResources);
01353
01354
01355
01356
01357
01358
01365 #define EDMA3_RM_DMA_CHANNEL_ANY (1011u)
01366
01373 #define EDMA3_RM_QDMA_CHANNEL_ANY (1012u)
01374
01382 #define EDMA3_RM_TCC_ANY (1013u)
01383
01391 #define EDMA3_RM_PARAM_ANY (1014u)
01392
01402 #define EDMA3_RM_CH_NO_PARAM_MAP (1015u)
01403
01413 #define EDMA3_RM_CH_NO_TCC_MAP (1016u)
01414
01415
01416
01435 typedef enum
01436 {
01438 EDMA3_RM_HW_CHANNEL_EVENT_0 = 0,
01440 EDMA3_RM_HW_CHANNEL_EVENT_1,
01442 EDMA3_RM_HW_CHANNEL_EVENT_2,
01444 EDMA3_RM_HW_CHANNEL_EVENT_3,
01446 EDMA3_RM_HW_CHANNEL_EVENT_4,
01448 EDMA3_RM_HW_CHANNEL_EVENT_5,
01450 EDMA3_RM_HW_CHANNEL_EVENT_6,
01452 EDMA3_RM_HW_CHANNEL_EVENT_7,
01454 EDMA3_RM_HW_CHANNEL_EVENT_8,
01456 EDMA3_RM_HW_CHANNEL_EVENT_9,
01458 EDMA3_RM_HW_CHANNEL_EVENT_10,
01460 EDMA3_RM_HW_CHANNEL_EVENT_11,
01462 EDMA3_RM_HW_CHANNEL_EVENT_12,
01464 EDMA3_RM_HW_CHANNEL_EVENT_13,
01466 EDMA3_RM_HW_CHANNEL_EVENT_14,
01468 EDMA3_RM_HW_CHANNEL_EVENT_15,
01470 EDMA3_RM_HW_CHANNEL_EVENT_16,
01472 EDMA3_RM_HW_CHANNEL_EVENT_17,
01474 EDMA3_RM_HW_CHANNEL_EVENT_18,
01476 EDMA3_RM_HW_CHANNEL_EVENT_19,
01478 EDMA3_RM_HW_CHANNEL_EVENT_20,
01480 EDMA3_RM_HW_CHANNEL_EVENT_21,
01482 EDMA3_RM_HW_CHANNEL_EVENT_22,
01484 EDMA3_RM_HW_CHANNEL_EVENT_23,
01486 EDMA3_RM_HW_CHANNEL_EVENT_24,
01488 EDMA3_RM_HW_CHANNEL_EVENT_25,
01490 EDMA3_RM_HW_CHANNEL_EVENT_26,
01492 EDMA3_RM_HW_CHANNEL_EVENT_27,
01494 EDMA3_RM_HW_CHANNEL_EVENT_28,
01496 EDMA3_RM_HW_CHANNEL_EVENT_29,
01498 EDMA3_RM_HW_CHANNEL_EVENT_30,
01500 EDMA3_RM_HW_CHANNEL_EVENT_31,
01502 EDMA3_RM_HW_CHANNEL_EVENT_32,
01504 EDMA3_RM_HW_CHANNEL_EVENT_33,
01506 EDMA3_RM_HW_CHANNEL_EVENT_34,
01508 EDMA3_RM_HW_CHANNEL_EVENT_35,
01510 EDMA3_RM_HW_CHANNEL_EVENT_36,
01512 EDMA3_RM_HW_CHANNEL_EVENT_37,
01514 EDMA3_RM_HW_CHANNEL_EVENT_38,
01516 EDMA3_RM_HW_CHANNEL_EVENT_39,
01518 EDMA3_RM_HW_CHANNEL_EVENT_40,
01520 EDMA3_RM_HW_CHANNEL_EVENT_41,
01522 EDMA3_RM_HW_CHANNEL_EVENT_42,
01524 EDMA3_RM_HW_CHANNEL_EVENT_43,
01526 EDMA3_RM_HW_CHANNEL_EVENT_44,
01528 EDMA3_RM_HW_CHANNEL_EVENT_45,
01530 EDMA3_RM_HW_CHANNEL_EVENT_46,
01532 EDMA3_RM_HW_CHANNEL_EVENT_47,
01534 EDMA3_RM_HW_CHANNEL_EVENT_48,
01536 EDMA3_RM_HW_CHANNEL_EVENT_49,
01538 EDMA3_RM_HW_CHANNEL_EVENT_50,
01540 EDMA3_RM_HW_CHANNEL_EVENT_51,
01542 EDMA3_RM_HW_CHANNEL_EVENT_52,
01544 EDMA3_RM_HW_CHANNEL_EVENT_53,
01546 EDMA3_RM_HW_CHANNEL_EVENT_54,
01548 EDMA3_RM_HW_CHANNEL_EVENT_55,
01550 EDMA3_RM_HW_CHANNEL_EVENT_56,
01552 EDMA3_RM_HW_CHANNEL_EVENT_57,
01554 EDMA3_RM_HW_CHANNEL_EVENT_58,
01556 EDMA3_RM_HW_CHANNEL_EVENT_59,
01558 EDMA3_RM_HW_CHANNEL_EVENT_60,
01560 EDMA3_RM_HW_CHANNEL_EVENT_61,
01562 EDMA3_RM_HW_CHANNEL_EVENT_62,
01564 EDMA3_RM_HW_CHANNEL_EVENT_63
01565 } EDMA3_RM_HW_CHANNEL_EVENT;
01566
01567
01568
01650 EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
01651 EDMA3_RM_ResDesc *lChObj,
01652 unsigned int *pParam,
01653 unsigned int *pTcc);
01654
01655
01656
01677 EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
01678 EDMA3_RM_ResDesc *lChObj);
01679
01680
01681
01682
01692 typedef struct {
01694 volatile unsigned int OPT;
01695
01700 volatile unsigned int SRC;
01701
01706 volatile unsigned int A_B_CNT;
01707
01713 volatile unsigned int DST;
01714
01725 volatile unsigned int SRC_DST_BIDX;
01726
01736 volatile unsigned int LINK_BCNTRLD;
01737
01743 volatile unsigned int SRC_DST_CIDX;
01744
01748 volatile unsigned int CCNT;
01749 } EDMA3_RM_ParamentryRegs;
01750
01751
01752
01759 typedef struct {
01761 volatile unsigned int opt;
01762
01767 volatile unsigned int srcAddr;
01768
01772 volatile unsigned short aCnt;
01773
01777 volatile unsigned short bCnt;
01778
01784 volatile unsigned int destAddr;
01785
01791 volatile short srcBIdx;
01792
01798 volatile short destBIdx;
01799
01807 volatile unsigned short linkAddr;
01808
01813 volatile unsigned short bCntReload;
01814
01818 volatile short srcCIdx;
01819
01823 volatile short destCIdx;
01824
01828 volatile unsigned short cCnt;
01829
01830 } EDMA3_RM_PaRAMRegs;
01831
01832
01833
01834
01841 typedef enum
01842 {
01847 EDMA3_RM_QDMA_TRIG_OPT = 0,
01852 EDMA3_RM_QDMA_TRIG_SRC = 1,
01857 EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2,
01862 EDMA3_RM_QDMA_TRIG_DST = 3,
01867 EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4,
01872 EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5,
01877 EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6,
01882 EDMA3_RM_QDMA_TRIG_CCNT = 7,
01884 EDMA3_RM_QDMA_TRIG_DEFAULT = 7
01885 } EDMA3_RM_QdmaTrigWord;
01886
01887
01888
01896 typedef enum
01897 {
01899 EDMA3_RM_CC_PHY_ADDR = 0,
01901 EDMA3_RM_TC0_PHY_ADDR,
01903 EDMA3_RM_TC1_PHY_ADDR,
01905 EDMA3_RM_TC2_PHY_ADDR,
01907 EDMA3_RM_TC3_PHY_ADDR,
01909 EDMA3_RM_TC4_PHY_ADDR,
01911 EDMA3_RM_TC5_PHY_ADDR,
01913 EDMA3_RM_TC6_PHY_ADDR,
01915 EDMA3_RM_TC7_PHY_ADDR
01916 }EDMA3_RM_Cntrlr_PhyAddr;
01917
01918
01919
01946 EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
01947 unsigned int channelId,
01948 unsigned int paRAMId);
01949
01950
01979 EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
01980 unsigned int channelId,
01981 unsigned int paRAMId,
01982 EDMA3_RM_QdmaTrigWord trigWord);
01983
01984
01985
02007 EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
02008 unsigned int regOffset,
02009 unsigned int newRegValue);
02010
02011
02027 EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
02028 unsigned int regOffset,
02029 unsigned int *regValue);
02030
02031
02032
02054 EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
02055 unsigned int tccNo);
02056
02057
02058
02059
02085 EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
02086 unsigned int tccNo,
02087 unsigned short *tccStatus);
02088
02089
02090
02091
02117 EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
02118 EDMA3_RM_ResDesc *lChObj,
02119 const EDMA3_RM_PaRAMRegs *newPaRAM);
02120
02121
02122
02140 EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
02141 EDMA3_RM_ResDesc *lChObj,
02142 EDMA3_RM_PaRAMRegs *currPaRAM);
02143
02144
02145
02173 EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
02174 EDMA3_RM_ResDesc *lChObj,
02175 unsigned int *paramPhyAddr);
02176
02177
02195 EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
02196 EDMA3_RM_Cntrlr_PhyAddr controllerId,
02197 unsigned int *phyAddress);
02198
02199
02200
02219 EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId,
02220 EDMA3_RM_GblConfigParams *gblCfgParams);
02221
02222
02223
02244 EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr,
02245 EDMA3_RM_InstanceInitConfig *instanceInitConfig);
02246
02247
02251 typedef enum
02252 {
02253
02254 EDMA3_RM_IOCTL_MIN_IOCTL = 0,
02255
02277 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION,
02278
02291 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,
02292
02315 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION,
02316
02329 EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION,
02330
02331
02332 EDMA3_RM_IOCTL_MAX_IOCTL
02333 } EDMA3_RM_IoctlCmd;
02334
02335
02353 EDMA3_RM_Result EDMA3_RM_Ioctl(
02354 EDMA3_RM_Handle hEdmaResMgr,
02355 EDMA3_RM_IoctlCmd cmd,
02356 void *cmdArg,
02357 void *param
02358 );
02359
02360
02361
02362
02363
02364
02365 #ifdef __cplusplus
02366 }
02367 #endif
02368
02369 #endif