EDMA3 Driver Typical EDMA Transfer Setup
[EDMA3 Driver Interface Definition]


Data Structures
struct	EDMA3_DRV_ChainOptions
	Structure to be used to configure interrupt generation and chaining options. More...
Enumerations
enum	EDMA3_DRV_OptField { EDMA3_DRV_OPT_FIELD_SAM = 0, EDMA3_DRV_OPT_FIELD_DAM = 1, EDMA3_DRV_OPT_FIELD_SYNCDIM = 2, EDMA3_DRV_OPT_FIELD_STATIC = 3, EDMA3_DRV_OPT_FIELD_FWID = 4, EDMA3_DRV_OPT_FIELD_TCCMODE = 5, EDMA3_DRV_OPT_FIELD_TCC = 6, EDMA3_DRV_OPT_FIELD_TCINTEN = 7, EDMA3_DRV_OPT_FIELD_ITCINTEN = 8, EDMA3_DRV_OPT_FIELD_TCCHEN = 9, EDMA3_DRV_OPT_FIELD_ITCCHEN = 10 }
	OPT Field Offset. More...
enum	EDMA3_DRV_AddrMode { EDMA3_DRV_ADDR_MODE_INCR = 0, EDMA3_DRV_ADDR_MODE_FIFO = 1 }
	EDMA Addressing modes. More...
enum	EDMA3_DRV_SyncType { EDMA3_DRV_SYNC_A = 0, EDMA3_DRV_SYNC_AB = 1 }
	EDMA Transfer Synchronization type. More...
enum	EDMA3_DRV_StaticMode { EDMA3_DRV_STATIC_DIS = 0, EDMA3_DRV_STATIC_EN = 1 }
	True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. More...
enum	EDMA3_DRV_FifoWidth { EDMA3_DRV_W8BIT = 0, EDMA3_DRV_W16BIT = 1, EDMA3_DRV_W32BIT = 2, EDMA3_DRV_W64BIT = 3, EDMA3_DRV_W128BIT = 4, EDMA3_DRV_W256BIT = 5 }
	EDMA3 FIFO width. More...
enum	EDMA3_DRV_TccMode { EDMA3_DRV_TCCMODE_NORMAL = 0, EDMA3_DRV_TCCMODE_EARLY = 1 }
	Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. More...
enum	EDMA3_DRV_TcintEn { EDMA3_DRV_TCINTEN_DIS = 0, EDMA3_DRV_TCINTEN_EN = 1 }
	Transfer complete interrupt enable. More...
enum	EDMA3_DRV_ItcintEn { EDMA3_DRV_ITCINTEN_DIS = 0, EDMA3_DRV_ITCINTEN_EN = 1 }
	Intermediate Transfer complete interrupt enable. More...
enum	EDMA3_DRV_TcchEn { EDMA3_DRV_TCCHEN_DIS = 0, EDMA3_DRV_TCCHEN_EN = 1 }
	Transfer complete chaining enable. More...
enum	EDMA3_DRV_ItcchEn { EDMA3_DRV_ITCCHEN_DIS = 0, EDMA3_DRV_ITCCHEN_EN = 1 }
	Intermediate Transfer complete chaining enable. More...
enum	EDMA3_DRV_TrigMode { EDMA3_DRV_TRIG_MODE_MANUAL = 0, EDMA3_DRV_TRIG_MODE_QDMA = 1, EDMA3_DRV_TRIG_MODE_EVENT = 2, EDMA3_DRV_TRIG_MODE_NONE = 3 }
	EDMA Trigger Mode Selection. More...
Functions
EDMA3_DRV_Result	EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
	Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result	EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
	Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result	EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
	DMA source parameters setup.
EDMA3_DRV_Result	EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
	DMA Destination parameters setup.
EDMA3_DRV_Result	EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
	DMA source index setup.
EDMA3_DRV_Result	EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
	DMA destination index setup.
EDMA3_DRV_Result	EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
	DMA transfer parameters setup.
EDMA3_DRV_Result	EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
	Chain the two specified channels.
EDMA3_DRV_Result	EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
	Unchain the two channels.
EDMA3_DRV_Result	EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
	Start EDMA transfer on the specified channel.
EDMA3_DRV_Result	EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
	Disable DMA transfer on the specified channel.
EDMA3_DRV_Result	EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
	Disable the event driven DMA channel or QDMA channel.

Detailed Description

The typical EDMA transfer related Interface of the EDMA3 Driver

Enumeration Type Documentation

enum EDMA3_DRV_AddrMode

EDMA Addressing modes.

The EDMA3 TC supports two addressing modes

Increment transfer
FIFO transfer

The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register.

Enumerator:

EDMA3_DRV_ADDR_MODE_INCR	Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
EDMA3_DRV_ADDR_MODE_FIFO	FIFO mode. Source addressing within an array wraps around upon reaching FIFO width.

enum EDMA3_DRV_FifoWidth

EDMA3 FIFO width.

The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode.

Enumerator:

EDMA3_DRV_W8BIT	FIFO width is 8-bit.
EDMA3_DRV_W16BIT	FIFO width is 16-bit.
EDMA3_DRV_W32BIT	FIFO width is 32-bit.
EDMA3_DRV_W64BIT	FIFO width is 64-bit.
EDMA3_DRV_W128BIT	FIFO width is 128-bit.
EDMA3_DRV_W256BIT	FIFO width is 256-bit.

enum EDMA3_DRV_ItcchEn

Intermediate Transfer complete chaining enable.

Enumerator:

EDMA3_DRV_ITCCHEN_DIS	Intermediate Transfer complete chaining is disabled
EDMA3_DRV_ITCCHEN_EN	Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_ItcintEn

Intermediate Transfer complete interrupt enable.

Enumerator:

EDMA3_DRV_ITCINTEN_DIS

Intermediate Transfer complete interrupt is disabled

EDMA3_DRV_ITCINTEN_EN

Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_OptField

OPT Field Offset.

Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set.

Enumerator:

EDMA3_DRV_OPT_FIELD_SAM	Source addressing mode (INCR / FIFO) (Bit 0)
EDMA3_DRV_OPT_FIELD_DAM	Destination addressing mode (INCR / FIFO) (Bit 1)
EDMA3_DRV_OPT_FIELD_SYNCDIM	Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2)
EDMA3_DRV_OPT_FIELD_STATIC	The STATIC field PaRAM set is static/non-static? (Bit 3)
EDMA3_DRV_OPT_FIELD_FWID	FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10)
EDMA3_DRV_OPT_FIELD_TCCMODE	Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11)
EDMA3_DRV_OPT_FIELD_TCC	Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17)
EDMA3_DRV_OPT_FIELD_TCINTEN	Transfer complete interrupt enable/disable. (Bit 20)
EDMA3_DRV_OPT_FIELD_ITCINTEN	Intermediate transfer complete interrupt enable/disable. (Bit 21)
EDMA3_DRV_OPT_FIELD_TCCHEN	Transfer complete chaining enable/disable (Bit 22)
EDMA3_DRV_OPT_FIELD_ITCCHEN	Intermediate transfer completion chaining enable/disable (Bit 23)

enum EDMA3_DRV_StaticMode

True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted.

Enumerator:

EDMA3_DRV_STATIC_DIS	PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers
EDMA3_DRV_STATIC_EN	PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.

enum EDMA3_DRV_SyncType

EDMA Transfer Synchronization type.

Two types of Synchronization of transfers are possible

A Synchronized
AB Syncronized

A Sync

Each Array is submitted as one TR
(BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)
(S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)

AB Sync
1. Each Frame is submitted as one TR
2. Only CCNT number of sync events are needed to completely service a PaRAM set
3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)

Note:: ABC sync transfers can be achieved logically by chaining multiple AB sync transfers

Enumerator:

EDMA3_DRV_SYNC_A	A-synchronized. Each event triggers the transfer of a single array of ACNT bytes
EDMA3_DRV_SYNC_AB	AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes

enum EDMA3_DRV_TcchEn

Transfer complete chaining enable.

Enumerator:

EDMA3_DRV_TCCHEN_DIS	Transfer complete chaining is disabled
EDMA3_DRV_TCCHEN_EN	Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_TccMode

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation.

Enumerator:

EDMA3_DRV_TCCMODE_NORMAL	A transfer is considered completed after transfer of data
EDMA3_DRV_TCCMODE_EARLY	A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.

enum EDMA3_DRV_TcintEn

Transfer complete interrupt enable.

Enumerator:

EDMA3_DRV_TCINTEN_DIS	Transfer complete interrupt is disabled
EDMA3_DRV_TCINTEN_EN	Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_TrigMode

EDMA Trigger Mode Selection.

Use this enum to select the EDMA trigger mode while enabling the EDMA transfer

Enumerator:

EDMA3_DRV_TRIG_MODE_MANUAL	Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH).
EDMA3_DRV_TRIG_MODE_QDMA	Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered).
EDMA3_DRV_TRIG_MODE_EVENT	Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request.
EDMA3_DRV_TRIG_MODE_NONE	Used to specify the trigger mode NONE

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_chainChannel	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh1,
		unsigned int	lCh2,
		const EDMA3_DRV_ChainOptions *	chainOptions
	)

Chain the two specified channels.

This API is used to chain two previously allocated logical (DMA/QDMA) channels.

Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained channel.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance.
	lCh1	[IN] Channel to which particular channel will be chained.
	lCh2	[IN] Channel which needs to be chained to the first channel.
	chainOptions	[IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.

EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_TrigMode	trigMode
	)

Disable the event driven DMA channel or QDMA channel.

This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.

This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] DMA/QDMA Channel which needs to be disabled
	trigMode	[IN] Mode of triggering start of transfer

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

EDMA3_DRV_Result EDMA3_DRV_disableTransfer	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_TrigMode	trigMode
	)

Disable DMA transfer on the specified channel.

There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.

To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Channel on which transfer has to be stopped
	trigMode	[IN] Mode of triggering start of transfer

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Even Enable Register, for the specific QDMA channel.

To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Channel on which transfer has to be stopped
	trigMode	[IN] Mode of triggering start of transfer

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

EDMA3_DRV_Result EDMA3_DRV_enableTransfer	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_TrigMode	trigMode
	)

Start EDMA transfer on the specified channel.

There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Event and Event Miss Register and then enables the DMA channel by writing to the EESR.

In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.

In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Channel on which transfer has to be started
	trigMode	[IN] Mode of triggering start of transfer (Manual, QDMA or Event)

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_ChBoundResources::trigMode.

EDMA3_DRV_Result EDMA3_DRV_getOptField	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_OptField	optField,
		unsigned int *	optFieldVal
	)

Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance.
	lCh	[IN] Logical Channel, bound to which PaRAM set OPT field is required.
	optField	[IN] The particular field of OPT Word that is needed
	optFieldVal	[IN/OUT] Value of the OPT field

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant.

EDMA3_DRV_Result EDMA3_DRV_setDestIndex	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		int	destBIdx,
		int	destCIdx
	)

DMA destination index setup.

It is used to program the destination B index and destination C index.

DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.

DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which dest indices are to be configured
	destBIdx	[IN] Destination B index
	destCIdx	[IN] Destination C index

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_DSTBIDX_MAX_VAL, EDMA3_DRV_DSTBIDX_MIN_VAL, EDMA3_DRV_DSTCIDX_MAX_VAL, EDMA3_DRV_DSTCIDX_MIN_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setDestParams	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		unsigned int	destAddr,
		EDMA3_DRV_AddrMode	addrMode,
		EDMA3_DRV_FifoWidth	fifoWidth
	)

DMA Destination parameters setup.

It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which the destination parameters are to be configured
	destAddr	[IN] Destination address
	addrMode	[IN] Address mode [FIFO or Increment]
	fifoWidth	[IN] Width of FIFO (Valid only if addrMode is FIFO) 0 - 8 bit 1 - 16 bit 2 - 32 bit 3 - 64 bit 4 - 128 bit 5 - 256 bit

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

In FIFO Addressing mode, memory location must be 32 bytes aligned

Memory is not 32 bytes aligned

If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not.

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

EDMA3_DRV_Result EDMA3_DRV_setOptField	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_OptField	optField,
		unsigned int	newOptFieldVal
	)

Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance.
	lCh	[IN] Logical Channel, bound to which PaRAM set OPT field needs to be set.
	optField	[IN] The particular field of OPT Word that needs setting
	newOptFieldVal	[IN] The new OPT field value

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

EDMA3_DRV_Result EDMA3_DRV_setSrcIndex	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		int	srcBIdx,
		int	srcCIdx
	)

DMA source index setup.

It is used to program the source B index and source C index.

SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.

SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which source indices are to be configured
	srcBIdx	[IN] Source B index
	srcCIdx	[IN] Source C index

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_SRCBIDX_MAX_VAL, EDMA3_DRV_SRCBIDX_MIN_VAL, EDMA3_DRV_SRCCIDX_MAX_VAL, EDMA3_DRV_SRCCIDX_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setSrcParams	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		unsigned int	srcAddr,
		EDMA3_DRV_AddrMode	addrMode,
		EDMA3_DRV_FifoWidth	fifoWidth
	)

DMA source parameters setup.

It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which the source parameters are to be configured
	srcAddr	[IN] Source address
	addrMode	[IN] Address mode [FIFO or Increment]
	fifoWidth	[IN] Width of FIFO (Valid only if addrMode is FIFO) 0 - 8 bit 1 - 16 bit 2 - 32 bit 3 - 64 bit 4 - 128 bit 5 - 256 bit

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

In FIFO Addressing mode, memory location must be 32 bytes aligned

Memory is not 32 bytes aligned

If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not.

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

EDMA3_DRV_Result EDMA3_DRV_setTransferParams	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		unsigned int	aCnt,
		unsigned int	bCnt,
		unsigned int	cCnt,
		unsigned int	bCntReload,
		EDMA3_DRV_SyncType	syncType
	)

DMA transfer parameters setup.

It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type

ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.

BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which transfer parameters are to be configured
	aCnt	[IN] Count for 1st Dimension.
	bCnt	[IN] Count for 2nd Dimension.
	cCnt	[IN] Count for 3rd Dimension.
	bCntReload	[IN] Reload value for bCnt.
	syncType	[IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_ACNT_MAX_VAL, EDMA3_DRV_BCNT_MAX_VAL, EDMA3_DRV_BCNTRELD_MAX_VAL, EDMA3_DRV_CCNT_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_SYNC_A, EDMA3_DRV_SYNC_AB, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_unchainChannel	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh
	)

Unchain the two channels.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance.
	lCh	[IN] Channel whose chaining with the other channel has to be removed.

Returns:: EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:: This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3 Driver Typical EDMA Transfer Setup [EDMA3 Driver Interface Definition]

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Enumeration Type Documentation

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EDMA3 Driver Typical EDMA Transfer Setup
[EDMA3 Driver Interface Definition]