EDMA3 Driver Error Codes
[EDMA3 Driver Interface Definition]

Usage of EDMA3 Driver. More...

Defines
#define	EDMA3_DRV_E_BASE   (-128)
#define	EDMA3_DRV_E_OBJ_NOT_DELETED   (EDMA3_DRV_E_BASE)
#define	EDMA3_DRV_E_OBJ_NOT_CLOSED   (EDMA3_DRV_E_BASE-1)
#define	EDMA3_DRV_E_OBJ_NOT_OPENED   (EDMA3_DRV_E_BASE-2)
#define	EDMA3_DRV_E_RM_CLOSE_FAIL   (EDMA3_DRV_E_BASE-3)
#define	EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-4)
#define	EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-5)
#define	EDMA3_DRV_E_PARAM_SET_UNAVAIL   (EDMA3_DRV_E_BASE-6)
#define	EDMA3_DRV_E_TCC_UNAVAIL   (EDMA3_DRV_E_BASE-7)
#define	EDMA3_DRV_E_TCC_REGISTER_FAIL   (EDMA3_DRV_E_BASE-8)
#define	EDMA3_DRV_E_CH_PARAM_BIND_FAIL   (EDMA3_DRV_E_BASE-9)
#define	EDMA3_DRV_E_ADDRESS_NOT_ALIGNED   (EDMA3_DRV_E_BASE-10)
#define	EDMA3_DRV_E_INVALID_PARAM   (EDMA3_DRV_E_BASE-11)
#define	EDMA3_DRV_E_INVALID_STATE   (EDMA3_DRV_E_BASE-12)
#define	EDMA3_DRV_E_INST_ALREADY_EXISTS   (EDMA3_DRV_E_BASE-13)
#define	EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED   (EDMA3_DRV_E_BASE-14)
#define	EDMA3_DRV_E_SEMAPHORE   (EDMA3_DRV_E_BASE-15)
#define	EDMA3_DRV_E_INST_NOT_OPENED   (EDMA3_DRV_E_BASE-16)

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Detailed Description

Usage of EDMA3 Driver.

1. Create EDMA3 Driver Object (one for each EDMA3 hardware instance)
   • EDMA3_DRV_Result result = EDMA3_DRV_SOK;
   • unsigned int edma3HwInstanceId = 0;
   • EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;
   • Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken.
   • result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);

1. Open EDMA3 driver Instance
   • Steps
     • EDMA3_DRV_InitConfig initCfg;
     • EDMA3_DRV_Handle hEdma = NULL;
     • EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
     • EDMA3_DRV_Result edmaResult; -To get the error code while opening driver instance

1. initCfg.regionId = One of the possible regions available for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for different masters.

1. initCfg.isMaster = TRUE/FALSE (Whether this EDMA3 DRV instance is Master or not. The EDMA3 Shadow Region tied to the Master DRV Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled).

1. initCfg.drvSemHandle = EDMA3 DRV Instance specific semaphore handle. It should be provided by the user for proper sharing of resources.
   • edma3Result = edma3OsSemCreate(1, &semAttrs, &initCfg.drvSemHandle);

1. initCfg.drvInstInitConfig = Init-time Region Specific Configuration Structure. It can be provided by the user at run-time. If not provided by the user, this info would be taken from the platform specific config file, if it exists.

1. initCfg.drvInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the EDMA3 Driver
   E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver owns DMA Channel Id 24
   Later when a request is made based on a particular Channel Id, the EDMA3 Driver will check first if it owns that channel. If it doesnot own it, EDMA3 Driver returns error.
2. initCfg.drvInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the EDMA3 Driver
   
3. initCfg.drvInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the EDMA3 Driver
   
4. initCfg.drvInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the EDMA3 Driver
   

1. initCfg.drvInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the EDMA3 Driver
   E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver reserves Channel Id 24
   These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.
   
2. initCfg.drvInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the EDMA3 Driver
   E.g. A '1' at bit position 1 indicates that this instance of the EDMA3 Driver reserves QDMA Channel Id 1
   These channels are reserved for some specific purpose, these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request
   
3. initCfg.drvInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region;
4. initCfg.drvInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region;

1. initCfg.gblerrCb = Instance wide callback function to catch non-channel specific errors;
2. initCfg.gblerrData = Application data to be passed back to the callback function;

1. hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);

1. EDMA3 driver APIs
   • EDMA3_RM_ResDesc resObj;
   • EDMA3_DRV_Result result;
   • unsigned int ch1Id = 0;
   • unsigned int ch2Id = 0;
   • unsigned int tcc1 = 0;
   • unsigned int tcc2 = 0;
   • unsigned int qCh1Id = 0;
   • unsigned int qTcc1 = 0;
   • unsigned int qCh2Id = 0;
   • unsigned int qTcc2 = 0;
   • unsigned int paRAMId;
   • int srcbidx = 0;
   • int desbidx = 0;
   • int srccidx = 0;
   • int descidx = 0;
   • unsigned int acnt = 0;
   • unsigned int bcnt = 0;
   • unsigned int ccnt = 0;
   • unsigned int bcntreload = 0;
   • EDMA3_DRV_SyncType synctype;
   • EDMA3_RM_TccCallback tccCb;
   • void *cbData;
   • Use Case 1: Memory to memory transfer on any available
   • DMA Channel
     
     
     • tcc1 = EDMA3_DRV_TCC_ANY;
     • ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
     • result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

• result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
• result = EDMA3_DRV_setDestParams (hEdma, ch1Id, (unsigned int)(dstBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

• Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
• result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, bcntreload, synctype);

• Set srcbidx and srccidx to the appropriate values
• srcbidx = acnt; srccidx = acnt;
• result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);

• Set desbidx and descidx to the appropriate values
• desbidx = acnt; descidx = acnt;
• result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);

• Enable the final completion interrupt.
• result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

• Enable the transfer
• result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);

• Use Case 2: Linked memory to memory transfer on any available
• DMA Channel
  
  
  • Perform steps as for Use Case 1 for the Master logical channel ch1Id for configuration. DONOT enable the transfer for ch1Id.
  • Configure link channel, ch2Id.
  • tcc2 = EDMA3_DRV_TCC_ANY;
  • ch2Id = EDMA3_DRV_LINK_CHANNEL;
  • result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);

• result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
• result = EDMA3_DRV_setDestParams (hEdma, ch2Id,( unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

• result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
• result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);

• result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, bcntreload, synctype);

• Link both the channels
• result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);

• Enable the final completion interrupts on both the channels
• result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
• result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

• Enable the transfer on channel 1.
• result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);
• Wait for the completion interrupt on Ch1 and then enable the transfer again for the LINK channel, to provide the required sync event.
• result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);

• Note: Enabling of transfers on channel 1 (for master and link channel) is required as many number of times as the sync events are required. For ASync mode, number of sync events=(bcnt * ccnt) and for ABSync mode, number of sync events = ccnt.

• Use Case 3: Memory to memory transfer on any available
• QDMA Channel
  
  
  • qTcc1 = EDMA3_DRV_TCC_ANY;
  • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;

• result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

• Set the QDMA trigger word.
• result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_RM_QDMA_TRIG_DST);
• Note: DONOT write the destination address (trigger word) before completing the configuration as it will trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the destination address

• result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

• Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
• result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);

• srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
• result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
• result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);

• Enable the final completion interrupt.
• result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

• Set the Destination Addressing Mode as Increment
• result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);

• Trigger the QDMA channel by writing the destination address
• result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));

• Use Case 4: Linked memory to memory transfer on any available
• QDMA Channel
  
  
  • Setup for any QDMA Channel
  • qTcc1 = EDMA3_DRV_TCC_ANY;
  • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
  • result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

• Setup for Channel 2
• qCh2Id = EDMA3_DRV_LINK_CHANNEL;
• qTcc2 = EDMA3_DRV_TCC_ANY;
• result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);

• result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
• result = EDMA3_DRV_setDestParams(hEdma, qCh2Id, (unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

• acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
• result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_A);

• srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
• result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
• result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);

• result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

• Make the PaRAM Set associated with qCh2Id as Static
• result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_STATIC, 1u);

• Link both the channels
• result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);

• Set the QDMA trigger word.
• result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_DRV_QDMA_TRIG_DST);
• Note: DONOT write the destination address (trigger word) before completing the configuration as it'll trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams () function to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the dest address.

• result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

• Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
• result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);

• srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
• result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
• result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);

• result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

• Set the Destination Addressing Mode as Increment
• result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);

• Trigger the QDMA channel by writing the destination address
• result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));

Error Codes returned by the EDMA3 Driver

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Define Documentation

#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED   (EDMA3_DRV_E_BASE-10)

The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned.

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_E_BASE   (-128)

EDMA3 Driver Error Codes Base define

#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL   (EDMA3_DRV_E_BASE-9)

The binding of Channel and PaRAM Set failed

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-4)

The requested DMA Channel not available

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED   (EDMA3_DRV_E_BASE-14)

FIFO width not supported by the requested TC

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_E_INST_ALREADY_EXISTS   (EDMA3_DRV_E_BASE-13)

EDMA3 Driver instance already exists for the specified region

Referenced by EDMA3_DRV_open().

#define EDMA3_DRV_E_INST_NOT_OPENED   (EDMA3_DRV_E_BASE-16)

EDMA3 Driver Instance does not exist, it is not opened yet

Referenced by EDMA3_DRV_getInstHandle().

#define EDMA3_DRV_E_INVALID_PARAM   (EDMA3_DRV_E_BASE-11)

Invalid Parameter passed to API

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_Ioctl(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and EDMA3_DRV_waitAndClearTcc().

#define EDMA3_DRV_E_INVALID_STATE   (EDMA3_DRV_E_BASE-12)

Invalid State of EDMA3 HW Obj

Referenced by EDMA3_DRV_delete(), and EDMA3_DRV_open().

#define EDMA3_DRV_E_OBJ_NOT_CLOSED   (EDMA3_DRV_E_BASE-1)

EDMA3 Driver Object Not Closed yet. So it cannot be deleted.

Referenced by EDMA3_DRV_delete().

#define EDMA3_DRV_E_OBJ_NOT_DELETED   (EDMA3_DRV_E_BASE)

EDMA3 Driver Object Not Deleted yet. So it cannot be created.

Referenced by EDMA3_DRV_create().

#define EDMA3_DRV_E_OBJ_NOT_OPENED   (EDMA3_DRV_E_BASE-2)

EDMA3 Driver Object Not Opened yet So it cannot be closed.

Referenced by EDMA3_DRV_close().

#define EDMA3_DRV_E_PARAM_SET_UNAVAIL   (EDMA3_DRV_E_BASE-6)

The requested PaRAM Set not available

#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-5)

The requested QDMA Channel not available

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_RM_CLOSE_FAIL   (EDMA3_DRV_E_BASE-3)

While closing EDMA3 Driver, Resource Manager Close Failed.

Referenced by EDMA3_DRV_close().

#define EDMA3_DRV_E_SEMAPHORE   (EDMA3_DRV_E_BASE-15)

Semaphore related error

#define EDMA3_DRV_E_TCC_REGISTER_FAIL   (EDMA3_DRV_E_BASE-8)

The registration of TCC failed

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_TCC_UNAVAIL   (EDMA3_DRV_E_BASE-7)

The requested TCC not available

Referenced by EDMA3_DRV_requestChannel().