This module manages the data and instruction caches on Cortex A9
processors.
It provides a list of functions that perform cache operations. The
functions operate on a per cache line except for the 'All' functions
which operate on the entire cache specified. Any Address that is not
aligned to a cache line gets rounded down to the address of
the nearest cache line.
The L1 data and program caches as well as the L2 cache are enabled
by default early during the startup sequence (prior to any
Module_startup()s).
Data caching requires the MMU to be enabled and the cacheable
attribute of the section/page descriptor for a corresponding
memory region to be enabled.
Program caching does not require the MMU to be enabled and therefore
occurs when the L1 program cache is enabled.
Here's an example showing how to enable L2 interrupt and register an
interrupt callback function:
const Cache_sizeL1dCacheLine |
|
Size of L1 data cache Line
#define Cache_sizeL1dCacheLine (UInt)32
const Cache_sizeL1pCacheLine |
|
Size of L1 program cache Line
#define Cache_sizeL1pCacheLine (UInt)32
const Cache_sizeL2CacheLine |
|
Size of L2 cache Line
#define Cache_sizeL2CacheLine (UInt)32
enum Cache_L2CounterIntType |
|
Lists of bitmask for event counter interrupt generation types
typedef enum Cache_L2CounterIntType {
Cache_L2CounterIntType_DISABLED,
// Disabled
Cache_L2CounterIntType_INCREMENT,
// Interrupt generated on counter
increment
Cache_L2CounterIntType_OVERFLOW
// Interrupt generated on counter
overflow
} Cache_L2CounterIntType;
enum Cache_L2EventSource |
|
Lists of bitmask for event sources to the L2 Cache event counter
typedef enum Cache_L2EventSource {
Cache_L2EventSource_DISABLED,
// Counter Disabled
Cache_L2EventSource_CO,
// Eviction of a line from the L2 cache
Cache_L2EventSource_DRHIT,
// Data read hit in the L2 cache
Cache_L2EventSource_DRREQ,
// Data read lookup to the L2 cache.
Results in a hit or miss
Cache_L2EventSource_DWHIT,
// Data write hit in the L2 cache
Cache_L2EventSource_DWREQ,
// Data write lookup to the L2 cache.
Results in a hit or miss
Cache_L2EventSource_DWTREQ,
// Data write lookup to L2 cache with
Write-Through attribute. Results in
a hit or miss
Cache_L2EventSource_IRHIT,
// Instruction read hit in the L2 cache
Cache_L2EventSource_IRREQ,
// Instruction read lookup to the L2
cache. Results in a hit or miss
Cache_L2EventSource_WA,
// Allocation into L2 cache caused by a
write, with Write-Allocate attribute.
Result of a cache miss
Cache_L2EventSource_IPFALLOC,
// Allocation of a prefetch generated by
L2 cache controller into L2 cache
Cache_L2EventSource_EPFHIT,
// Prefetch hint hits in the L2 cache
Cache_L2EventSource_EPFALLOC,
// Prefetch hint allocated into L2
cache
Cache_L2EventSource_SRRCVD,
// Speculative read received by slave
port S0/1
Cache_L2EventSource_SRCONF,
// Speculative read confirmed in slave
port S0/1
Cache_L2EventSource_EPFRCVD
// Prefetch hint received by slave port
S0/1
} Cache_L2EventSource;
enum Cache_Type |
|
Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
typedef Cache_CacheIntHandlerFuncPtr |
|
Cache interrupt handler function type definition
typedef Void (*Cache_CacheIntHandlerFuncPtr)(UArg);
struct Cache_L2ControllerRegs |
|
PL310 L2 Cache controller registers. Symbol "Cache_l2ControllerRegs"
is a physical device
typedef struct Cache_L2ControllerRegs {
UInt32 CACHEID;
// 0x000 Cache Id Register
UInt32 CACHETYPE;
// 0x004 Cache Type Register
UInt32 hole0[62];
// 0x008-0x0FC
UInt32 CONTROL;
// 0x100 Control Register
UInt32 AUXCONTROL;
// 0x104 Auxiliary Control Register
UInt32 TAGRAMCONTROL;
// 0x108 Tag RAM Latency Control Register
UInt32 DATARAMCONTROL;
// 0x10C Data RAM Latency Control Register
UInt32 hole1[60];
// 0x110-0x1FC
UInt32 EVCOUNTERCTRL;
// 0x200 Event Counter Control Register
UInt32 EVCOUNTER1CFG;
// 0x204 Event Counter1 Config Register
UInt32 EVCOUNTER0CFG;
// 0x208 Event Counter0 Config Register
UInt32 EVCOUNTER1;
// 0x20C Event Counter1 Value Register
UInt32 EVCOUNTER0;
// 0x210 Event Counter0 Value Register
UInt32 INTMASK;
// 0x214 Interrupt Mask Register
UInt32 INTMASKSTATUS;
// 0x218 Interrupt Mask Status Register
UInt32 INTRAWSTATUS;
// 0x21C Interrupt Raw Status Register
UInt32 INTCLEAR;
// 0x220 Interrupt Clear Register
UInt32 hole2[323];
// 0x224-0x72C
UInt32 CACHESYNC;
// 0x730 Cache Sync Register
UInt32 hole3[15];
// 0x734-0x76C
UInt32 INVPA;
// 0x770 Invalidate By Physical Address
UInt32 hole4[2];
// 0x774-0x778
UInt32 INVWAY;
// 0x77C Invalidate By Way Number
UInt32 hole5[12];
// 0x780-0x7AC
UInt32 CLEANPA;
// 0x7B0 Clean By Physical Address
UInt32 hole6[1];
// 0x7B4
UInt32 CLEANINDEX;
// 0x7B8 Clean by Set or Way
UInt32 CLEANWAY;
// 0x7BC Clean by Way
UInt32 hole7[12];
// 0x7C0-0x7EC
UInt32 CLEANINVPA;
// 0x7F0 Clean & Invalidate by Phy Address
UInt32 hole8[1];
// 0x7F4
UInt32 CLEANINVINDEX;
// 0x7F8 Clean & Invalidate By Set or Way
UInt32 CLEANINVWAY;
// 0x7FC Clean & Invalidate By Way
UInt32 hole9[64];
// 0x800-0x8FC
UInt32 LOCKDOWN[16];
// 0x900-0x93C D & I Cache Lockdown regs
UInt32 hole10[4];
// 0x940-0x94C
UInt32 LOCKLINEEN;
// 0x950 Lock Line Enable
UInt32 UNLOCKWAY;
// 0x954 Unlock Way
UInt32 hole11[170];
// 0x958-0xBFC
UInt32 ADDRFILTERSTART;
// 0xC00 Address Filtering Start
UInt32 ADDRFILTEREND;
// 0xC04 Address Filtering End
UInt32 hole12[206];
// 0xC08-0xF3C
UInt32 DEBUGCTRL;
// 0xF40 Debug Register
UInt32 hole13[7];
// 0xF44-0xF5C
UInt32 PREFETCHCTRL;
// 0xF60 Prefetch Control Register
UInt32 hole14[7];
// 0xF64-0xF7C
UInt32 POWERCTRL;
// 0xF80 Power Control Register
} Cache_L2ControllerRegs;
config Cache_A_badBlockLength // module-wide |
|
Asserted in Cache_lock (see Cache_lock for more info)
extern const Assert_Id Cache_A_badBlockLength;
config Cache_A_badInvCallWithL2En // module-wide |
|
Assert raised when Cache invalidate called with L2 enabled
extern const Assert_Id Cache_A_badInvCallWithL2En;
config Cache_A_badL2CacheOperation // module-wide |
|
Assert raised when attempting to perform a L2 Cache maintenance
operation with L2 configured as SRAM memory
extern const Assert_Id Cache_A_badL2CacheOperation;
config Cache_A_blockCrossesPage // module-wide |
|
Asserted in Cache_lock (see Cache_lock for more info)
extern const Assert_Id Cache_A_blockCrossesPage;
config Cache_A_invalidL2CounterId // module-wide |
|
Assert raised when invalid counter id passed to L2 cache event counter
APIs
extern const Assert_Id Cache_A_invalidL2CounterId;
config Cache_A_l1PrefetchApiNotSupported // module-wide |
|
Assert raised when an unsupported API is called
extern const Assert_Id Cache_A_l1PrefetchApiNotSupported;
config Cache_A_noNonSecureInterruptAccess // module-wide |
|
Assert raised when enableL2CacheInterruot is set to true, but interrupt
control through non-secure access is not allowed
extern const Assert_Id Cache_A_noNonSecureInterruptAccess;
config Cache_A_noNonSecureLockdown // module-wide |
|
Assert raised when Cache_lock() called but non-secure lockdown is not
enabled
extern const Assert_Id Cache_A_noNonSecureLockdown;
config Cache_branchPredictionEnabled // module-wide |
|
Enable Branch Prediction at startup, default is true
extern const Bool Cache_branchPredictionEnabled;
DETAILS
This flag controls whether Branch Prediction should be automatically
enabled or disabled during system startup.
NOTE
Upon reset, the A9's Program Flow Prediction (Branch Prediction)
feature is disabled.
config Cache_configureL2Sram // module-wide |
|
Configure L2 as cache or SRAM memory
extern const Bool Cache_configureL2Sram;
DETAILS
By default, when the device resets, it will be set
as cache. If this parameter is set to "true",
L2 cache will be configured as SRAM memory during
startup.
NOTE
This config param is only supported on AM437X.
config Cache_enableCache // module-wide |
|
Enable L1 and L2 data and program caches
extern const Bool Cache_enableCache;
DETAILS
To enable a subset of the caches, set this parameter
to 'false' and call Cache_enable() within main, passing it only
the
Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page
descriptor cacheable attribute to be enabled.
config Cache_enableL2Interrupt // module-wide |
|
This flag controls whether L2 Cache Controller interrupt is enabled.
(default is true)
extern const Bool Cache_enableL2Interrupt;
DETAILS
If this flag is enabled, this cache module will enable all L2 cache
controller interrupts and register a L2 cache interrupt handler that
will call the l2InterruptFunc if a callback function is registered.
The callback function is passed the contents of the Masked Interrupt
Status Register.
The L2 cache interrupt handler will detect any L2 cache errors
and the errors will be visible in this module's ROV view. The handler
also ackowledges the interrupt.
config Cache_l2DataPrefetchEnable // module-wide |
|
Enable L2 Data prefetching
extern const Bool Cache_l2DataPrefetchEnable;
config Cache_l2DoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill
extern const Bool Cache_l2DoubleLinefillEnable;
NOTE
This config param is only supported on AM437X.
config Cache_l2IncrDoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill on Incrementing reads
extern const Bool Cache_l2IncrDoubleLinefillEnable;
NOTE
This config param is only supported on AM437X.
config Cache_l2InstructionPrefetchEnable // module-wide |
|
Enable L2 Instruction prefetching
extern const Bool Cache_l2InstructionPrefetchEnable;
config Cache_l2InterruptFunc // module-wide |
|
Function called when a L2 cache Interrupt occurs
DETAILS
The function is passed the contents of the Masked Interrupt Status
Register as an argument.
Masked Interrupt Status Register bit assignments
----------------------------------------------------------------------
| Bits | Field | Description |
----------------------------------------------------------------------
| 31:9 | Reserved | Read as 0 |
----------------------------------------------------------------------
| 8 | Decode error received on master port from L3 | |
------------------------------------------------------ |
| 7 | Slave error received on master port from L3 | A 1 indicates |
------------------------------------------------------ the status of |
| 6 | Error on L2 data RAM read | the input line|
------------------------------------------------------ triggering |
| 5 | Error on L2 tag RAM read | an interrupt. |
------------------------------------------------------ |
| 4 | Error on L2 data RAM write | A 0 indicates |
------------------------------------------------------ either no |
| 3 | Error on L2 tag RAM write | interrupt has |
------------------------------------------------------ been generated|
| 2 | Parity error on L2 data RAM read | or the |
------------------------------------------------------ interrupt is |
| 1 | Parity error on L2 tag RAM read | masked. |
------------------------------------------------------ |
| 0 | Event counter 0/1 overflow/increment | |
----------------------------------------------------------------------
config Cache_l2InterruptMask // module-wide |
|
L2 cache Interrupt mask
extern const UInt32 Cache_l2InterruptMask;
DETAILS
This mask controls which L2 cache Interrupts are enabled when
enableL2Interrupt is true. By default, all interrupts
are enabled.
config Cache_l2PrefetchDropEnable // module-wide |
|
Enable L2 prefetch drop
extern const Bool Cache_l2PrefetchDropEnable;
NOTE
This config param is only supported on AM437X.
config Cache_l2PrefetchOffset // module-wide |
|
Prefetch offset for subsequent cache line prefetches
extern const UInt8 Cache_l2PrefetchOffset;
DETAILS
L2C-310 supports offset values of 0-7, 15, 23 and 31 only.
NOTE
This field has affect only if L2 data/instruction
prefetching is enabled.
config Cache_l2WrapDoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill on Wrapping reads
extern const Bool Cache_l2WrapDoubleLinefillEnable;
NOTE
This config param is only supported on AM437X.
config Cache_unlockL2Cache // module-wide |
|
Unlock all L2 cache ways at startup, default is true
extern const Bool Cache_unlockL2Cache;
DETAILS
Ordinarily, the L2 cache ways should all be unlocked at
system startup.
During development using CCS, if the application exits
while L2 cache ways are locked, the soft-reset function
DOES NOT unlock the L2 cache ways. To overcome this problem,
the L2 cache ways are unlocked during Cache module startup.
If for any reason this behavior is undesirable, setting this
config parameter to false will disable the automatic unlocking
of the L2 cache ways.
extern Cache_l2ControllerRegs |
|
Cache_L2ControllerRegs Cache_l2ControllerRegs; // linked as extern ti_sysbios_family_arm_a9_Cache_l2ControllerRegs
Cache_configureL2EventCounter() // module-wide |
|
Sets the event source and interrupt generation type for the specified
L2 Cache event counter
ARGUMENTS
counterId
Event counter Id (0/1)
eventSource
Counter event source
interruptType
Bit mask of event counter interrupt generation
type
NOTE
This API disables the event counter before updating the event counter
config registers.
Cache_disable() // module-wide |
|
Backend for ti.sysbios.hal.Cache.disable()
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
NOTE
This function disables interrupts while performing L1 and L2 cache
maintenance operations. It can affect interrupt latency and should
not be called unless absolutely necessary.
SEE
Cache_disableBP() // module-wide |
|
Disable Branch Prediction
DETAILS
Calling this API will disable branch prediction.
NOTE
Upon reset, the A9's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_disableL1Prefetch() // module-wide |
|
Disable L1 data prefetching
Void Cache_disableL1Prefetch();
NOTE
This API is only supported on AM437X.
Cache_disableL2EventCounters() // module-wide |
|
Disables the L2 Cache event counters
Void Cache_disableL2EventCounters();
Cache_enable() // module-wide |
|
Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_enableBP() // module-wide |
|
Enable Branch Prediction
DETAILS
Calling this API will enable branch prediction.
NOTE
Upon reset, the A9's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_enableL1Prefetch() // module-wide |
|
Enable L1 data prefetching
Void Cache_enableL1Prefetch();
NOTE
This API is only supported on AM437X.
Cache_enableL2EventCounters() // module-wide |
|
Enables the L2 Cache event counters
Void Cache_enableL2EventCounters();
Cache_getL2AuxControlReg() // module-wide |
|
Get current L2 Aux Control register contents
Bits32 Cache_getL2AuxControlReg();
DETAILS
Refer
ARM PL310 Cache Controller Reference Manual
for a description of the Auxiliary Control Register.
Cache_getL2EventCount() // module-wide |
|
Return counter register value for the specified L2 Cache event counter
UInt32 Cache_getL2EventCount(UInt counterId);
ARGUMENTS
counterId
Event counter Id (0/1)
RETURNS
Event count
Cache_getL2PrefetchControl() // module-wide |
|
Get current L2 prefetch control register contents
Bits32 Cache_getL2PrefetchControl();
DETAILS
Refer
ARM PL310 Cache Controller Reference Manual
for a description of the Prefetch Control Register.
Cache_inv() // module-wide |
|
Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1dAll() // module-wide |
|
Invalidate all of L1 data cache
DETAILS
This function should be used with caution. In general, the
L1 data cache may contain some stack variable or valid data
that should not be invalidated. This function should be used
only when all contents of L1 data cache are unwanted.
Cache_invL1pAll() // module-wide |
|
Invalidate all of L1 program cache
Cache_invL2All() // module-wide |
|
Invalidate entire L2 unified cache
DETAILS
This function should only be called with the L2 cache disabled.
If called with cache enabled, it will generate an assertion failure.
Cache_lock() // module-wide |
|
Loads and locks a memory block into the L2 cache
UInt Cache_lock(Ptr blockPtr, SizeT byteCnt);
ARGUMENTS
blockPtr
start address of range to be locked
byteCnt
number of bytes to be locked
RETURNS
key = bitmask of L2 cache "way" used
DETAILS
A block of memory is loaded into the L2 cache and
a corresponding L2 cache "way" is locked.
The memory block is loaded into cache one L2 cache line at a time.
The returned key is a bitmask of the L2 cache "way"
used to lock the memory block. This key should be passed in
a subsequent call to
Cache_unlock() if the memory
block is to be unlocked.
If the key returned is zero, then the lock operation failed
due to insufficient cache "ways" remaining to perform the operation.
The locking algorithm requires at least two unlocked cache ways:
one for the memory block, and one for the locking code itself.
The A9 external L2 cache can be an 8 or 16 way cache. Locking a cache
way consumes 1/8 or 1/16 of the total L2 cache, regardless of the
actual memory block size. For instance, if the size of L2 cache is
256K bytes and the L2 is configured as a 16 way cache, locking ANY size
memory block into a way will tie up 16K bytes of L2 cache.
The byteCnt argument must be less than or equal to an L2 "way"
size. Locking memory blocks larger than a way page size requires
calling this API multiple times. An assert is generated if this rule
is violated.
The memory block must not cross an L2 "way" page boundary.
Locking memory blocks that cross way page boundaries requires
calling this API multiple times. An assert is generated if this rule
is violated.
Except for the normal L1 instruction cache behavior
during code execution, the L1 instruction cache is
unaffected by this API.
The L1 data cache will be temporarily polluted by the contents
of the referenced memory block.
NOTE
Interrupts are disabled for the entire time the memory block
is being loaded into cache. For this reason, use of this API
is probably best at system intialization time
(ie: within 'main()').
Cache_resetL2EventCounter() // module-wide |
|
Reset the specified L2 Cache event counter
Void Cache_resetL2EventCounter(UInt counterId);
ARGUMENTS
counterId
Event counter Id (0/1)
Cache_setL2AuxControlReg() // module-wide |
|
Set L2 Aux Control register
Void Cache_setL2AuxControlReg(Bits32 arg);
DETAILS
Refer
ARM PL310 Cache Controller Reference Manual
for a description of the Auxiliary Control Register.
Cache_setL2PrefetchControl() // module-wide |
|
Set L2 prefetch control register
Void Cache_setL2PrefetchControl(UInt32 regVal);
DETAILS
Refer
ARM PL310 Cache Controller Reference Manual
for a description of the Prefetch Control Register.
Cache_unlock() // module-wide |
|
Unlocks an L2 cache way
Void Cache_unlock(UInt key);
ARGUMENTS
key
Key returned by Cache_lock()
DETAILS
Unlocks the L2 cache "way" locked by
Cache_lock().
NOTE
Multiple L2 cache "ways" can be unlocked simultaneously by "or-ing"
together the bitmasks returned from several invocations of Cache_lock().
Cache_wait() // module-wide |
|
Backend for ti.sysbios.hal.Cache.wait()
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Implementation for this API uses Data Synchronization Barrier (DSB)
ARM instruction.
SEE
Cache_wb() // module-wide |
|
Backend for ti.sysbios.hal.Cache.wb()
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
NOTE
This function ignores the 'type' argument and does a write-back
on both L1 data and L2 caches.
SEE
Cache_wbAll() // module-wide |
|
Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
Cache_wbInv() // module-wide |
|
Backend for ti.sysbios.hal.Cache.wbInv()
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
NOTE
This function ignores the 'type' argument and does a write-back
invalidate on both L1 data and L2 caches.
SEE
Cache_wbInvAll() // module-wide |
|
Write back invalidate all caches
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
const Cache.sizeL1dCacheLine |
|
Size of L1 data cache Line
const Cache.sizeL1dCacheLine = 32;
C SYNOPSIS
const Cache.sizeL1pCacheLine |
|
Size of L1 program cache Line
const Cache.sizeL1pCacheLine = 32;
C SYNOPSIS
const Cache.sizeL2CacheLine |
|
Size of L2 cache Line
const Cache.sizeL2CacheLine = 32;
C SYNOPSIS
enum Cache.L2CounterIntType |
|
Lists of bitmask for event counter interrupt generation types
values of type Cache.L2CounterIntType
const Cache.L2CounterIntType_DISABLED;
// Disabled
const Cache.L2CounterIntType_INCREMENT;
// Interrupt generated on counter
increment
const Cache.L2CounterIntType_OVERFLOW;
// Interrupt generated on counter
overflow
C SYNOPSIS
enum Cache.L2EventSource |
|
Lists of bitmask for event sources to the L2 Cache event counter
values of type Cache.L2EventSource
const Cache.L2EventSource_DISABLED;
// Counter Disabled
const Cache.L2EventSource_CO;
// Eviction of a line from the L2 cache
const Cache.L2EventSource_DRHIT;
// Data read hit in the L2 cache
const Cache.L2EventSource_DRREQ;
// Data read lookup to the L2 cache.
Results in a hit or miss
const Cache.L2EventSource_DWHIT;
// Data write hit in the L2 cache
const Cache.L2EventSource_DWREQ;
// Data write lookup to the L2 cache.
Results in a hit or miss
const Cache.L2EventSource_DWTREQ;
// Data write lookup to L2 cache with
Write-Through attribute. Results in
a hit or miss
const Cache.L2EventSource_IRHIT;
// Instruction read hit in the L2 cache
const Cache.L2EventSource_IRREQ;
// Instruction read lookup to the L2
cache. Results in a hit or miss
const Cache.L2EventSource_WA;
// Allocation into L2 cache caused by a
write, with Write-Allocate attribute.
Result of a cache miss
const Cache.L2EventSource_IPFALLOC;
// Allocation of a prefetch generated by
L2 cache controller into L2 cache
const Cache.L2EventSource_EPFHIT;
// Prefetch hint hits in the L2 cache
const Cache.L2EventSource_EPFALLOC;
// Prefetch hint allocated into L2
cache
const Cache.L2EventSource_SRRCVD;
// Speculative read received by slave
port S0/1
const Cache.L2EventSource_SRCONF;
// Speculative read confirmed in slave
port S0/1
const Cache.L2EventSource_EPFRCVD;
// Prefetch hint received by slave port
S0/1
C SYNOPSIS
enum Cache.Type |
|
Lists of bitmask cache types
values of type Cache.Type
const Cache.Type_L1P;
// Level 1 Program cache
const Cache.Type_L1D;
// Level 1 Data cache
const Cache.Type_L1;
// Level 1 caches
const Cache.Type_L2P;
// Level 2 Program cache
const Cache.Type_L2D;
// Level 2 Data cache
const Cache.Type_L2;
// Level 2 caches
const Cache.Type_ALLP;
// All Program caches
const Cache.Type_ALLD;
// All Data caches
const Cache.Type_ALL;
// All caches
C SYNOPSIS
struct Cache.L2ControllerRegs |
|
PL310 L2 Cache controller registers. Symbol "Cache_l2ControllerRegs"
is a physical device
var obj = new Cache.L2ControllerRegs;
obj.CACHEID = UInt32 ...
// 0x000 Cache Id Register
obj.CACHETYPE = UInt32 ...
// 0x004 Cache Type Register
obj.hole0 = UInt32[62] ...
// 0x008-0x0FC
obj.CONTROL = UInt32 ...
// 0x100 Control Register
obj.AUXCONTROL = UInt32 ...
// 0x104 Auxiliary Control Register
obj.TAGRAMCONTROL = UInt32 ...
// 0x108 Tag RAM Latency Control Register
obj.DATARAMCONTROL = UInt32 ...
// 0x10C Data RAM Latency Control Register
obj.hole1 = UInt32[60] ...
// 0x110-0x1FC
obj.EVCOUNTERCTRL = UInt32 ...
// 0x200 Event Counter Control Register
obj.EVCOUNTER1CFG = UInt32 ...
// 0x204 Event Counter1 Config Register
obj.EVCOUNTER0CFG = UInt32 ...
// 0x208 Event Counter0 Config Register
obj.EVCOUNTER1 = UInt32 ...
// 0x20C Event Counter1 Value Register
obj.EVCOUNTER0 = UInt32 ...
// 0x210 Event Counter0 Value Register
obj.INTMASK = UInt32 ...
// 0x214 Interrupt Mask Register
obj.INTMASKSTATUS = UInt32 ...
// 0x218 Interrupt Mask Status Register
obj.INTRAWSTATUS = UInt32 ...
// 0x21C Interrupt Raw Status Register
obj.INTCLEAR = UInt32 ...
// 0x220 Interrupt Clear Register
obj.hole2 = UInt32[323] ...
// 0x224-0x72C
obj.CACHESYNC = UInt32 ...
// 0x730 Cache Sync Register
obj.hole3 = UInt32[15] ...
// 0x734-0x76C
obj.INVPA = UInt32 ...
// 0x770 Invalidate By Physical Address
obj.hole4 = UInt32[2] ...
// 0x774-0x778
obj.INVWAY = UInt32 ...
// 0x77C Invalidate By Way Number
obj.hole5 = UInt32[12] ...
// 0x780-0x7AC
obj.CLEANPA = UInt32 ...
// 0x7B0 Clean By Physical Address
obj.hole6 = UInt32[1] ...
// 0x7B4
obj.CLEANINDEX = UInt32 ...
// 0x7B8 Clean by Set or Way
obj.CLEANWAY = UInt32 ...
// 0x7BC Clean by Way
obj.hole7 = UInt32[12] ...
// 0x7C0-0x7EC
obj.CLEANINVPA = UInt32 ...
// 0x7F0 Clean & Invalidate by Phy Address
obj.hole8 = UInt32[1] ...
// 0x7F4
obj.CLEANINVINDEX = UInt32 ...
// 0x7F8 Clean & Invalidate By Set or Way
obj.CLEANINVWAY = UInt32 ...
// 0x7FC Clean & Invalidate By Way
obj.hole9 = UInt32[64] ...
// 0x800-0x8FC
obj.LOCKDOWN = UInt32[16] ...
// 0x900-0x93C D & I Cache Lockdown regs
obj.hole10 = UInt32[4] ...
// 0x940-0x94C
obj.LOCKLINEEN = UInt32 ...
// 0x950 Lock Line Enable
obj.UNLOCKWAY = UInt32 ...
// 0x954 Unlock Way
obj.hole11 = UInt32[170] ...
// 0x958-0xBFC
obj.ADDRFILTERSTART = UInt32 ...
// 0xC00 Address Filtering Start
obj.ADDRFILTEREND = UInt32 ...
// 0xC04 Address Filtering End
obj.hole12 = UInt32[206] ...
// 0xC08-0xF3C
obj.DEBUGCTRL = UInt32 ...
// 0xF40 Debug Register
obj.hole13 = UInt32[7] ...
// 0xF44-0xF5C
obj.PREFETCHCTRL = UInt32 ...
// 0xF60 Prefetch Control Register
obj.hole14 = UInt32[7] ...
// 0xF64-0xF7C
obj.POWERCTRL = UInt32 ...
// 0xF80 Power Control Register
C SYNOPSIS
config Cache.A_badBlockLength // module-wide |
|
Asserted in Cache_lock (see Cache_lock for more info)
msg: "A_badBlockLength: Block length too large. Must be <= L2 way size."
};
C SYNOPSIS
config Cache.A_badInvCallWithL2En // module-wide |
|
Assert raised when Cache invalidate called with L2 enabled
msg: "A_badInvCallWithL2En: Cannot call cache Invalidate with L2 cache enabled."
};
C SYNOPSIS
config Cache.A_badL2CacheOperation // module-wide |
|
Assert raised when attempting to perform a L2 Cache maintenance
operation with L2 configured as SRAM memory
msg: "A_badL2CacheOperation: Cannot perform L2 Cache maintenance when L2 configured as SRAM."
};
C SYNOPSIS
config Cache.A_blockCrossesPage // module-wide |
|
Asserted in Cache_lock (see Cache_lock for more info)
msg: "A_blockCrossesPage: Memory block crosses L2 way page boundary."
};
C SYNOPSIS
config Cache.A_invalidL2CounterId // module-wide |
|
Assert raised when invalid counter id passed to L2 cache event counter
APIs
msg: "A_invalidL2CounterId: Invalid L2 cache event counter Id passed."
};
C SYNOPSIS
config Cache.A_l1PrefetchApiNotSupported // module-wide |
|
Assert raised when an unsupported API is called
msg: "A_l1PrefetchApiNotSupported: Cache_enableL1Prefetch()/Cache_disableL1Prefetch() APIs not supported on this device."
};
C SYNOPSIS
config Cache.A_noNonSecureInterruptAccess // module-wide |
|
Assert raised when enableL2CacheInterruot is set to true, but interrupt
control through non-secure access is not allowed
msg: "A_noNonSecureInterruptAccess: Non-secure interrupt access control disabled."
};
C SYNOPSIS
config Cache.A_noNonSecureLockdown // module-wide |
|
Assert raised when Cache_lock() called but non-secure lockdown is not
enabled
msg: "A_noNonSecureLockdown: Non-secure lockdown is not enabled."
};
C SYNOPSIS
config Cache.branchPredictionEnabled // module-wide |
|
Enable Branch Prediction at startup, default is true
Cache.branchPredictionEnabled = Bool true;
DETAILS
This flag controls whether Branch Prediction should be automatically
enabled or disabled during system startup.
NOTE
Upon reset, the A9's Program Flow Prediction (Branch Prediction)
feature is disabled.
C SYNOPSIS
config Cache.configureL2Sram // module-wide |
|
Configure L2 as cache or SRAM memory
Cache.configureL2Sram = Bool false;
DETAILS
By default, when the device resets, it will be set
as cache. If this parameter is set to "true",
L2 cache will be configured as SRAM memory during
startup.
NOTE
This config param is only supported on AM437X.
C SYNOPSIS
config Cache.enableCache // module-wide |
|
Enable L1 and L2 data and program caches
Cache.enableCache = Bool true;
DETAILS
To enable a subset of the caches, set this parameter
to 'false' and call Cache_enable() within main, passing it only
the
Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page
descriptor cacheable attribute to be enabled.
C SYNOPSIS
config Cache.enableL2Interrupt // module-wide |
|
This flag controls whether L2 Cache Controller interrupt is enabled.
(default is true)
Cache.enableL2Interrupt = Bool true;
DETAILS
If this flag is enabled, this cache module will enable all L2 cache
controller interrupts and register a L2 cache interrupt handler that
will call the l2InterruptFunc if a callback function is registered.
The callback function is passed the contents of the Masked Interrupt
Status Register.
The L2 cache interrupt handler will detect any L2 cache errors
and the errors will be visible in this module's ROV view. The handler
also ackowledges the interrupt.
C SYNOPSIS
config Cache.l2DataPrefetchEnable // module-wide |
|
Enable L2 Data prefetching
Cache.l2DataPrefetchEnable = Bool true;
C SYNOPSIS
config Cache.l2DoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill
Cache.l2DoubleLinefillEnable = Bool true;
NOTE
This config param is only supported on AM437X.
C SYNOPSIS
config Cache.l2IncrDoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill on Incrementing reads
Cache.l2IncrDoubleLinefillEnable = Bool false;
NOTE
This config param is only supported on AM437X.
C SYNOPSIS
config Cache.l2InstructionPrefetchEnable // module-wide |
|
Enable L2 Instruction prefetching
Cache.l2InstructionPrefetchEnable = Bool true;
C SYNOPSIS
config Cache.l2InterruptFunc // module-wide |
|
Function called when a L2 cache Interrupt occurs
Cache.l2InterruptFunc = Void(*)(UArg) null;
DETAILS
The function is passed the contents of the Masked Interrupt Status
Register as an argument.
Masked Interrupt Status Register bit assignments
----------------------------------------------------------------------
| Bits | Field | Description |
----------------------------------------------------------------------
| 31:9 | Reserved | Read as 0 |
----------------------------------------------------------------------
| 8 | Decode error received on master port from L3 | |
------------------------------------------------------ |
| 7 | Slave error received on master port from L3 | A 1 indicates |
------------------------------------------------------ the status of |
| 6 | Error on L2 data RAM read | the input line|
------------------------------------------------------ triggering |
| 5 | Error on L2 tag RAM read | an interrupt. |
------------------------------------------------------ |
| 4 | Error on L2 data RAM write | A 0 indicates |
------------------------------------------------------ either no |
| 3 | Error on L2 tag RAM write | interrupt has |
------------------------------------------------------ been generated|
| 2 | Parity error on L2 data RAM read | or the |
------------------------------------------------------ interrupt is |
| 1 | Parity error on L2 tag RAM read | masked. |
------------------------------------------------------ |
| 0 | Event counter 0/1 overflow/increment | |
----------------------------------------------------------------------
C SYNOPSIS
config Cache.l2InterruptMask // module-wide |
|
L2 cache Interrupt mask
Cache.l2InterruptMask = UInt32 0x1FF;
DETAILS
This mask controls which L2 cache Interrupts are enabled when
enableL2Interrupt is true. By default, all interrupts
are enabled.
C SYNOPSIS
config Cache.l2PrefetchDropEnable // module-wide |
|
Enable L2 prefetch drop
Cache.l2PrefetchDropEnable = Bool false;
NOTE
This config param is only supported on AM437X.
C SYNOPSIS
config Cache.l2PrefetchOffset // module-wide |
|
Prefetch offset for subsequent cache line prefetches
Cache.l2PrefetchOffset = UInt8 0;
DETAILS
L2C-310 supports offset values of 0-7, 15, 23 and 31 only.
NOTE
This field has affect only if L2 data/instruction
prefetching is enabled.
C SYNOPSIS
config Cache.l2WrapDoubleLinefillEnable // module-wide |
|
Enable L2 Double Linefill on Wrapping reads
Cache.l2WrapDoubleLinefillEnable = Bool false;
NOTE
This config param is only supported on AM437X.
C SYNOPSIS
config Cache.unlockL2Cache // module-wide |
|
Unlock all L2 cache ways at startup, default is true
Cache.unlockL2Cache = Bool true;
DETAILS
Ordinarily, the L2 cache ways should all be unlocked at
system startup.
During development using CCS, if the application exits
while L2 cache ways are locked, the soft-reset function
DOES NOT unlock the L2 cache ways. To overcome this problem,
the L2 cache ways are unlocked during Cache module startup.
If for any reason this behavior is undesirable, setting this
config parameter to false will disable the automatic unlocking
of the L2 cache ways.
C SYNOPSIS
metaonly config Cache.common$ // module-wide |
|
Common module configuration parameters
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.