JTAG

#Introduction JTAG is the common name of the IEEE1149.1 standard, which defines the Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan ([BSDL](./emu_bsdl.html)). It is also used for application development. IEEE 1149.1 is also commonly known as JTAG (Joint Test Action Group) and has been in use for more than two decades. This technology is integrated into Debug Probes and TI microcontrollers and processors to allow external inspection and debugging. #IEEE 1149.1 (JTAG) Technology Overview Texas Instruments invented JTAG scan-based emulation, an approach that has since been broadly adopted for embedded systems development. JTAG emulation is now widely preferred over the older and more expensive "in-circuit emulation", or "ICE" technology. In-Circuit Emulation replaces the target processor with a different device that acts like, or "emulates", the original device, but has additional pins to make internal structures on the device, like busses, visible. In-Circuit Emulation is limited because the cost of supporting high-speed processors beyond 200 MHz quickly becomes prohibitive. The JTAG emulation technology used by TI' XDS-series emulators eliminates these debugging costs and difficulties by communicating directly with the processor, avoiding a special emulation device altogether. JTAG lets data be moved on- and off-chip non-intrusively, without interrupting the executing device. TI then augments this capability with additional emulation logic to provide even greater visibility and access into registers and other internal functions such as on-chip cache memories. JTAG emulation is also widely preferred over monitor based solutions as JTAG solutions do not need valuable processor resources. JTAG also acts as a connection for boundary scan. Boundary scan is valuable in ensuring the quality of products during manufacturing. Boundary scan can be used to perform board and system-level tests that can detect and diagnose pin-level structural faults such as opens and shorts. ##References - IEEE 1149.1 JTAG Testability Primer: [SSYA002](https://www.ti.com/lit/an/ssya002d/ssya002d.pdf) - JTAG Scan Educator: [SATB002](https://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=satb002a) - JTAG/MPSD Emulation Technical Reference: [SPDU079](https://www.ti.com/lit/ug/spdu079a/spdu079a.pdf) - [WIKIpedia entry](http://en.wikipedia.org/wiki/JTAG) - The [IEEE 1149.1 standard](http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-2001_desc.html) - Free commercial quality software (BSDL, pin toggle, access internal regs, tcl/tk scripting) at [Intellitech](http://www.intellitech.com/jtag/free-jtag-software-ijtag.asp) #IEEE 1149.7 Technology Overview IEEE 1149.7 is complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard and it was ratified in 2009. IEEE 1149.7 adds substantial functionality to the existing standard, but it is not a replacement for IEEE 1149.1. Backward compatibility is maintained so that any a board or system that integrates chips that support either standard is amenable to test or debug procedures. The new IEEE 1149.7 standard offers embedded designers several benefits, including: - The ability to control debug logic power consumption in an industry standard way. Whereas IEEE 1149.1 (JTAG) had a single "always on" state, IEEE 1149.7 offers four selectable power modes to enable ultra-low power devices. - The ability to quickly access a specific device in a system with multiple devices. By implementing a system level bypass, the scan chain is drastically shorter, which directly improves the debugging experience. - The introduction of a star topology to complement the standard serial topology. Designers working with stacked-die devices, multi-chip modules and plug-in cards will favor the star topology because it simplifies the physical inter-device connections. - Two-pin operation instead of the four-pin operation required in IEEE 1149.1. Since most of today's systems integrate multiple ICs and often have severe size constraints, reducing the number of pins and traces will help designers meet their form factor goals and allowing for additional functional pins and/or low package cost. - Compatibility with existing IEEE 1149.1 (JTAG) compliant IP, allowing preservation of investment. While IEEE 1149.7 adds substantial functionality to the existing standard, it is important to note that it is not a replacement for IEEE 1149.1. Backward compatibility is maintained so that any board or system that integrates chips that support either standard is amenable to test or debug procedures. ##Related standards - IEEE 1149.1 (JTAG) is the predecessor to IEEE 1149.7. - [IEEE 1149.6](http://grouper.ieee.org/groups/1149/6) is focused on boundary-scan testing for advanced digital networks. - [IEEE 1149.7](http://grouper.ieee.org/groups/1149/7/) is a complementary superset of IEEE 1149.1. - [IEEE 1500](http://grouper.ieee.org/groups/1500) is a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry. - [IEEE P1687](http://grouper.ieee.org/groups/1687) is developing a methodology for access to embedded test and debug features, to include a description language. - [IEEE-ISTO 5001](http://www.nexus5001.org) is the NEXUS debug standard. IEEE 1149.1 is a connection type used by NEXUS. IEEE 1149.7 will be included in the new revision of the NEXUS debug specification. - [MIPI](http://mipi.org/) is the Mobile Industry Processor Interface Alliance, and IEEE 1149.7 is a recommended Test and Debug interface. (see the [MIPI T&D White Paper Interface Framework](http://www.mipi.org/docs/MIPI_TDWG_whitepaper_v3_2.pdf) - The [specification at the IEEE](http://ieeexplore.ieee.org/servlet/opac?punumber=5412864) ##Related articles - Presentation from SWDFT 2009: [IEEE1149.7 Overview](./files/IEEE1149.7overview.pdf) - [The importance of standards](./files/IEEE1149.7importanceofstandards.pdf) - IEEE 1149.7 official webpage is [here](http://grouper.ieee.org/groups/1149/7/) - [Embedded Systems Magazine article](http://www.embedded.com/design/210200584) - [Corelis press release](http://www.corelis.com/news/pr-Corelis_Promotes_Improved_Circuit_Test.htm) - IEEE 1149.7 Overview at Southwest Design for Test Conference (SWDFT) Austin, Texas April 2009. [Hosted](http://www.siliconaid.com/2009_SWDFT_presentation/IEEE1149-7%20for%20SWDFT.pdf) and [Original](./files/IEEE1149.7overview.pdf) - [Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7](http://www.design-reuse.com/articles/21304/ieee-nexus-5001-1149-7.html) - [EDN: Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7](http://i.cmpnet.com/edadesignline/2009/aug/EI%20Using%20IEEE%205001%20and%201141_full_061509.pdf)  <hr>  <div id="footer"></div>