#What is ICEPick?
ICEPick is TI's name for the JTAG route controller in its devices, similar in function to an Ethernet router but for JTAG signals. In other words, it serves as a chip level TAP (Test Access Port) controller.
It brings several advantages to a traditional point-to-point JTAG connection to a scan chain.
- Allows connecting and disconnecting cores from the scan chain without interrupting the Debug Probe connection.
- Selected devices allow monitoring of the core status for various signals (power, clock, reset status) on ICEPick-D. It can also preserve the connection during power and reset transitions on selected devices.
- Features Dynamic Scan Chain management within the device (if the debug probe supports it), which enables the same interface to simultaneously connect to multiple cores with different frequencies (or RTCK domains).
- Selected devices have the [Wait in Reset](./emu_wait_in_reset.html) functionality enabled.
- Keeps the IR register at a fixed low number of bits (6 for the ICEPick-C and ICEPick-D variants), thus allowing longer scan chains.
A description of the ICEPICK TAP router, also generically refered to as JTAG Route Controller or JRC can be found at the [SPRP603 presentation](https://focus.ti.com/lit/ml/sprp603/sprp603.pdf).
There are various versions of ICEPick:
- ICEPick-M - used in J721E, xWR164x, xWR684x
- ICEPick-D - used in AM335x, AM43xx, AM57xx, 66AK2x, C665x, C667x, DM814x, DM816x, OMAP44xx, OMAP46xx, OMAP543x, TCI66xx
- ICEPick-C - used in CC13x0, CC26x0, CC13x2, CC26x2, CC322x, CC32x5, C674x, OMAPL13x, TMS570, RM46, RM48, CC2538, OMAP34xx, AM35x, DM350/355, DM365/368, DM6467, DM510, TMS320TCI648x, C2000 Sonata F28M3x
- ICEPick-B - used in OMAP2420
The main difference between ICEPick-B and ICEPick-C is the number of bits on the JTAG IR register: 2 bits for the "B" variant and 6 bits for the "C" variant.
ICEPick-D provides additional capabilities as summarized below:
- the number of debug taps is increased to 32 from 16
- adds non-JTAG control registers (NJCR) to support power, clock and reset management for processors or subsystem that is not associated with a JTAG TAP. Cortex processors from ARM Ltd, for example.
#Non-XDS Debug Probes
To allow non-XDS Debug Probes to connect to devices that feature ICEPick, a specific IR configuration is needed to bypass the ICEPick router. This is particularly useful to access the DAP of ARM Cortex CPUs. The port number for the secondary taps are device specific but this information can be found either via the Device Datasheet, the Device TRM or the Debug TRM. The Debug TRM is available at the Emulation Developer Community portal - check the section References below.
The sequence of commands to select a second TAP is available at:
Most of the documentation is available at the Emulation Developer Community portal. To inquiry about access, please contact the tools team at the Code Composer Studio forum at https://e2e.ti.com
A few useful public documents can be found below:
- The ICEPick functional specification is available at the Emulation Developer Community portal.
- A detailed description of the ICEPick-C functionality and configuration can be found at the [SPRUH35 document](https://www.ti.com/lit/ug/spruh35/spruh35.pdf).
- To add devices to a ICEPick-C or a ICEPick-D scan chain, check the documents [Router Scan Sequence](./files/Router_Scan_Sequence.pdf) or [Router Scan Sequence ICEPick-D](./files/Router_Scan_Sequence-ICEpick-D.pdf)
- To see the ICEPick registers in Code Composer Studio, check section 7.5.7 of the [CCS User's Guide](../users_guide/index.html)
- To see the core status of the cores under the ICEPick router, check section 7.5.7 of the [CCS User's Guide](../users_guide/index.html)
- To enable the Low Power Run mode to keep the debug connection through power transitions, check section 7.2.6 of the [CCS User's Guide](../users_guide/index.html)
- OMAP35xx information can be found at [this external reference](https://www.elinux.org/OMAP3530_ICEPICK)