emif.h

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//###########################################################################
//
// FILE:   emif.h
//
// TITLE:  C29x EMIF driver.
//
//###########################################################################
// //
//  Copyright: Copyright (C) Texas Instruments Incorporated
//  All rights reserved not granted herein.
//
//  Redistribution and use in source and binary forms, with or without 
//  modification, are permitted provided that the following conditions 
//  are met:
//
//  Redistributions of source code must retain the above copyright 
//  notice, this list of conditions and the following disclaimer.
//
//  Redistributions in binary form must reproduce the above copyright
//  notice, this list of conditions and the following disclaimer in the 
//  documentation and/or other materials provided with the   
//  distribution.
//
//  Neither the name of Texas Instruments Incorporated nor the names of
//  its contributors may be used to endorse or promote products derived
//  from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
 
//###########################################################################
 
#ifndef EMIF_H
#define EMIF_H
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
 
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_emif.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
 
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Define to mask out the bits in the ASYNC_CSx_CR register that
// aren't associated with async configuration.
//
//*****************************************************************************
#define EMIF_ASYNC_CS_CR_MASK    ((uint32_t)EMIF_ASYNC_CS2_CR_R_HOLD_M    |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_R_STROBE_M  |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_R_SETUP_M   |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_W_HOLD_M    |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_W_STROBE_M  |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_W_SETUP_M   |   \
                                  (uint32_t)EMIF_ASYNC_CS2_CR_TA_M)
 
//*****************************************************************************
//
// Define to mask out the bits in the INT_MSK register that aren't associated
// with interrupts.
//
//*****************************************************************************
#define EMIF_ASYNC_INT_MASK      ((uint16_t)EMIF_INT_MSK_SET_AT_MASK_SET  |   \
                                  (uint16_t)EMIF_INT_MSK_SET_LT_MASK_SET  |   \
                                  (uint16_t)EMIF_INT_MSK_SET_WR_MASK_SET_M)
 
//*****************************************************************************
//
// Defines to specify interrupt sources to EMIF_enableAsyncInterrupt() and
// EMIF_disableAsyncInterrupt().Three interrupts are available for asynchronous
// memory interface: Masked Asyncronous Timeout(AT) to indicate EMxWAIT signal
// remains active even after maximum wait cycles are reached. Masked Line Trap
// (LT) to indicate illegal memory access or invalid cache line size.
// Masked Wait Rise(WR) to indicate rising edge on EMxWAIT is detected.
//
//*****************************************************************************
#define EMIF_ASYNC_INT_AT      EMIF_INT_MSK_SET_AT_MASK_SET
 
#define EMIF_ASYNC_INT_LT      EMIF_INT_MSK_SET_LT_MASK_SET
 
#define EMIF_ASYNC_INT_WR      EMIF_INT_MSK_SET_WR_MASK_SET_M
 
//*****************************************************************************
//
// Define for key for EMIF1MSEL register that enables the register write.
//
//*****************************************************************************
#define EMIF_MSEL_KEY  0x93A5CE70U
 
//*****************************************************************************
//
// Define to mask out the bits in the SDRAM_CR register that aren't
// associated with SDRAM configuration parameters.
//
//*****************************************************************************
#define EMIF_SYNC_SDRAM_CR_MASK   ((uint32_t)EMIF_SDRAM_CR_PAGESIGE_M    |    \
                                   (uint32_t)EMIF_SDRAM_CR_IBANK_M       |    \
                                   (uint32_t)EMIF_SDRAM_CR_BIT_11_9_LOCK |    \
                                   (uint32_t)EMIF_SDRAM_CR_CL_M          |    \
                                   (uint32_t)EMIF_SDRAM_CR_NM            |    \
                                   (uint32_t)EMIF_SDRAM_CR_SR)
 
//*****************************************************************************
//
// Define to mask out the bits in the SDRAM_TR register that aren't
// associated with SDRAM timings parameters.
//
//*****************************************************************************
#define EMIF_SYNC_SDRAM_TR_MASK  ((uint32_t)EMIF_SDRAM_TR_T_RRD_M  |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_RC_M   |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_RAS_M  |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_WR_M   |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_RCD_M  |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_RP_M   |          \
                                  (uint32_t)EMIF_SDRAM_TR_T_RFC_M)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_ASYNC_CS2_OFFSET = EMIF_O_ASYNC_CS2_CR, 
    EMIF_ASYNC_CS3_OFFSET = EMIF_O_ASYNC_CS3_CR, 
    EMIF_ASYNC_CS4_OFFSET = EMIF_O_ASYNC_CS4_CR  
} EMIF_AsyncCSOffset;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_ASYNC_DATA_WIDTH_8  = 0x0000U, 
    EMIF_ASYNC_DATA_WIDTH_16 = 0x0001U, 
    EMIF_ASYNC_DATA_WIDTH_32 = 0x0002U  
} EMIF_AsyncDataWidth;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_ASYNC_STROBE_MODE = 0x80000000U, 
    EMIF_ASYNC_NORMAL_MODE = 0x00000000U  
} EMIF_AsyncMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_ASYNC_WAIT_POLARITY_LOW  = 0x00000000U,
    EMIF_ASYNC_WAIT_POLARITY_HIGH = 0x10000000U
} EMIF_AsyncWaitPolarity;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_SYNC_NARROW_MODE_TRUE = 0x00004000U, 
    EMIF_SYNC_NARROW_MODE_FALSE = 0x00000000U 
} EMIF_SyncNarrowMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_SYNC_BANK_1 = 0x00000000U, 
    EMIF_SYNC_BANK_2 = 0x00000010U, 
    EMIF_SYNC_BANK_4 = 0x00000020U  
} EMIF_SyncBank;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
  EMIF_SYNC_CAS_LAT_2    = 0x00000500U,  
  EMIF_SYNC_CAS_LAT_3    = 0x00000700U   
} EMIF_SyncCASLatency;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EMIF_SYNC_COLUMN_WIDTH_8  = 0x00000000U, 
    EMIF_SYNC_COLUMN_WIDTH_9  = 0x00000001U, 
    EMIF_SYNC_COLUMN_WIDTH_10 = 0x00000002U, 
    EMIF_SYNC_COLUMN_WIDTH_11 = 0x00000003U  
} EMIF_SyncPageSize;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct
{
    uint32_t rSetup;            
    uint32_t rStrobe;           
    uint32_t rHold;             
    uint32_t wSetup;            
    uint32_t wStrobe;           
    uint32_t wHold;             
    uint32_t turnArnd;          
} EMIF_AsyncTimingParams;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct
{
    EMIF_SyncNarrowMode narrowMode;     
    EMIF_SyncBank iBank;                
    EMIF_SyncCASLatency casLatency;     
    EMIF_SyncPageSize pageSize;         
} EMIF_SyncConfig;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct
{
    uint32_t tRfc;          
    uint32_t tRp;           
    uint32_t tRcd;          
    uint32_t tWr;           
    uint32_t tRas;          
    uint32_t tRc;           
    uint32_t tRrd;          
} EMIF_SyncTimingParams;
 
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
#ifdef DEBUG
static inline bool
EMIF_isBaseValid(uint32_t base)
{
    return(
           (base == EMIF1_BASE)
           );
}
#endif
 
//*****************************************************************************
//
// Prototypes for Asynchronous Memory Interface
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setAsyncMode(uint32_t base, EMIF_AsyncCSOffset offset,
                  EMIF_AsyncMode mode)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the async mode of operation.
    //
    HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset)
                                      & ~((uint32_t)EMIF_ASYNC_CS2_CR_SS))
                                      | (uint32_t)mode;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_enableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bit that enables extended wait mode.
    //
    HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) |
                                     EMIF_ASYNC_CS2_CR_EW;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_disableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset)
 {
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bit that disables extended wait mode.
    //
    HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) &
                                     ~((uint32_t)EMIF_ASYNC_CS2_CR_EW);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setAsyncWaitPolarity(uint32_t base, EMIF_AsyncWaitPolarity polarity)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the polarity for async extended wait mode.
    //
    HWREG(base + EMIF_O_ASYNC_WCCR) = (HWREG(base + EMIF_O_ASYNC_WCCR)
                                      & ~((uint32_t)EMIF_ASYNC_WCCR_WP0))
                                      | (uint32_t)polarity;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setAsyncMaximumWaitCycles(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(value <= (EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M));
 
    //
    // Sets the bit that enables extended wait mode.
    //
    HWREGH(base + EMIF_O_ASYNC_WCCR) = (HWREGH(base + EMIF_O_ASYNC_WCCR)
                                  & ~((uint16_t)EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M))
                                  | value;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setAsyncTimingParams(uint32_t base, EMIF_AsyncCSOffset offset,
                          const EMIF_AsyncTimingParams *tParam)
{
    uint32_t temp;
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the async memory timing parameters.
    //
    temp = (tParam->turnArnd << EMIF_ASYNC_CS2_CR_TA_S)      |
           (tParam->rHold << EMIF_ASYNC_CS2_CR_R_HOLD_S)     |
           (tParam->rStrobe << EMIF_ASYNC_CS2_CR_R_STROBE_S) |
           (tParam->rSetup << EMIF_ASYNC_CS2_CR_R_SETUP_S)   |
           (tParam->wHold << EMIF_ASYNC_CS2_CR_W_HOLD_S)     |
           (tParam->wStrobe << EMIF_ASYNC_CS2_CR_W_STROBE_S) |
           (tParam->wSetup << EMIF_ASYNC_CS2_CR_W_SETUP_S);
 
    HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) &
                                       ~EMIF_ASYNC_CS_CR_MASK) | temp;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setAsyncDataBusWidth(uint32_t base, EMIF_AsyncCSOffset offset,
                           EMIF_AsyncDataWidth width)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the async memory data bus width.
    //
    HWREGH(base + (uint32_t)offset) = (HWREGH(base + (uint32_t)offset)
                                      & ~((uint16_t)EMIF_ASYNC_CS2_CR_ASIZE_M))
                                      | (uint32_t)width;
}
 
//*****************************************************************************
//
// Prototypes for Interrupt Handling
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_enableAsyncInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(intFlags <= EMIF_ASYNC_INT_MASK);
 
    //
    // Sets the bits that enables async memory interrupts.
    //
    HWREGH(base + EMIF_O_INT_MSK_SET) = intFlags;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_disableAsyncInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(intFlags <= EMIF_ASYNC_INT_MASK);
 
    //
    // Sets the bits that disables async memory interrupts.
    //
    HWREGH(base + EMIF_O_INT_MSK_CLR) = intFlags;
 
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EMIF_getAsyncInterruptStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Gets the async memory interrupt status.
    //
    return(HWREGH(base + EMIF_O_INT_MSK) & EMIF_ASYNC_INT_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_clearAsyncInterruptStatus(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(intFlags <= EMIF_ASYNC_INT_MASK);
 
    //
    // Sets the bit that clears desired async memory interrupts.
    //
    HWREGH(base + EMIF_O_INT_MSK) = intFlags;
}
 
//*****************************************************************************
//
// Prototypes for Synchronous Memory Interface
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setSyncTimingParams(uint32_t base, const EMIF_SyncTimingParams *tParam)
{
    uint32_t temp;
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets sync memory timing parameters.
    //
    temp = ((tParam->tRrd << EMIF_SDRAM_TR_T_RRD_S)
                            & EMIF_SDRAM_TR_T_RRD_M)
                    | ((tParam->tRc << EMIF_SDRAM_TR_T_RC_S)
                            & EMIF_SDRAM_TR_T_RC_M)
                    | ((tParam->tRas << EMIF_SDRAM_TR_T_RAS_S)
                            & EMIF_SDRAM_TR_T_RAS_M)
                    | ((tParam->tWr << EMIF_SDRAM_TR_T_WR_S)
                            & EMIF_SDRAM_TR_T_WR_M)
                    | ((tParam->tRcd << EMIF_SDRAM_TR_T_RCD_S)
                            & EMIF_SDRAM_TR_T_RCD_M)
                    | ((tParam->tRp << EMIF_SDRAM_TR_T_RP_S)
                            & EMIF_SDRAM_TR_T_RP_M)
                    | ((tParam->tRfc << EMIF_SDRAM_TR_T_RFC_S)
                            & EMIF_SDRAM_TR_T_RFC_M);
 
    HWREG(base + EMIF_O_SDRAM_TR) = (HWREG(base + EMIF_O_SDRAM_TR) &
                                     ~EMIF_SYNC_SDRAM_TR_MASK) | temp;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setSyncSelfRefreshExitTmng(uint32_t base, uint16_t tXs)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(tXs <= EMIF_SDR_EXT_TMNG_T_XS_M);
 
    //
    // Sets the self refresh exit timing for sync memory.
    //
    HWREGH(base + EMIF_O_SDR_EXT_TMNG) = (HWREGH(base + EMIF_O_SDR_EXT_TMNG)
                                        & ~((uint16_t)EMIF_SDR_EXT_TMNG_T_XS_M))
                                        | tXs;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setSyncRefreshRate(uint32_t base, uint16_t refRate)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
    ASSERT(refRate <= EMIF_SDRAM_RCR_REFRESH_RATE_M);
 
    //
    // Sets the sync memory refresh rate.
    //
    HWREGH(base + EMIF_O_SDRAM_RCR) = (HWREGH(base + EMIF_O_SDRAM_RCR)
                                   & (~(uint16_t)EMIF_SDRAM_RCR_REFRESH_RATE_M))
                                   | refRate;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_setSyncMemoryConfig(uint32_t base, const EMIF_SyncConfig *config)
{
    uint32_t temp;
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the sync memory configuration bits.
    //
    temp = ((uint32_t)config->casLatency | (uint32_t)config->iBank |
            (uint32_t)config->narrowMode | (uint32_t)config->pageSize);
 
    HWREG(base + EMIF_O_SDRAM_CR) = (HWREG(base + EMIF_O_SDRAM_CR) &
                                     ~EMIF_SYNC_SDRAM_CR_MASK) | temp;
}
 
//*****************************************************************************
//
// Prototypes for EMIF Low Power Modes
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_enableSyncSelfRefresh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that enables sync memory self refresh mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_SR;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_disableSyncSelfRefresh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that disables sync memory self refresh mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_SR);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_enableSyncPowerDown(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that enables sync memory power down mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PD;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_disableSyncPowerDown(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that disables sync memory power down mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PD);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_enableSyncRefreshInPowerDown(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that enables refresh in power down mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PDWR;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EMIF_disableSyncRefreshInPowerDown(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Sets the bits that disables refresh in power down mode.
    //
    HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PDWR);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EMIF_getSyncTotalAccesses(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Gets total accesses to sync memory.
    //
    return(HWREG(base + EMIF_O_TOTAL_SDRAM_AR));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EMIF_getSyncTotalActivateAccesses(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(EMIF_isBaseValid(base));
 
    //
    // Gets total accesses to sync memory which requires activate command.
    //
    return(HWREG(base + EMIF_O_TOTAL_SDRAM_ACTR));
}
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // EMIF_H