EMIF

Table of Contents

• Features Supported
• SysConfig Features
• Features NOT Supported
• Important Usage Guidelines
• Example Usage
• API

The EMIF driver provides API to configure the EMIF module. Below are the high level features supported by the EMIF driver.

Features Supported

This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 32-bit/16-bit data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external devices including:

• Single data rate (SDR) SDRAM
• Asynchronous devices including NOR Flash and SRAM A common use for the EMIF is to interface with both a Flash device and an SDRAM device simultaneously.

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

• Support for Wait Polarity.
• Support for Maximum Wait.
• CS0 SDRAM configurations.
  • CAS latency
  • Narrow Mode
  • Number of banks
  • Column address width
  • Refresh rate in cycles
  • Auto refresh time
  • Row precharge time
  • RAS to CAS delay
  • Write recovery time
  • Row active time
  • Read cycle time
  • Row active to row active delay
  • Sync self refresh exit timing
• CS2/CS3/CS4 ASRAM configurations.
  • Write setup cycles
  • Write strobe cycles
  • Write hold cycles
  • Read setup cycles
  • Read strobe cycles
  • Read hold cycles
  • Turn around cycles
• Data and Address pin mux configurations
• Seperate DMA trigger.

Features NOT Supported

NA

Important Usage Guidelines

NA

Example Usage

Include the below file to access the APIs #include <emif.h>

API

EMIF