am6 Board Configuration Resource Assignment Type Descriptions¶
Introduction¶
This chapter provides information of Board Configuration resource assignment type IDs that are permitted in the am6 SoC. The resource type IDs represent am6 resources ranges assignable to SoC processing entities (or PEs).
| Device Name | Device ID (10-bits) | Subtype Name | Subtype ID (6-bits) | Unique Type ID (16-bits) |
|---|---|---|---|---|
| AM6_DEV_MCU_CPSW0 | 0x005 | RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x0140 |
| RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x01 | 0x0141 | ||
| AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | 0x0A1 | RESASG_SUBTYPE_WKUP_DMSC0_CORTEX_M3_0_NVIC_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x00 | 0x2840 |
| AM6_DEV_ESM0 | 0x034 | RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x00 | 0x0D00 |
| RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x01 | 0x0D01 | ||
| RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x02 | 0x0D02 | ||
| AM6_DEV_WKUP_ESM0 | 0x036 | RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x00 | 0x0D80 |
| RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x01 | 0x0D81 | ||
| RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x02 | 0x0D82 | ||
| AM6_DEV_GIC0 | 0x038 | RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 | 0x00 | 0x0E00 |
| RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x01 | 0x0E01 | ||
| RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 | 0x02 | 0x0E02 | ||
| RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 | 0x03 | 0x0E03 | ||
| RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x04 | 0x0E04 | ||
| AM6_DEV_PRU_ICSSG0 | 0x03E | RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x0F80 |
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x01 | 0x0F81 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x02 | 0x0F82 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x03 | 0x0F83 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x04 | 0x0F84 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x05 | 0x0F85 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 | 0x06 | 0x0F86 | ||
| RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x07 | 0x0F87 | ||
| AM6_DEV_PRU_ICSSG1 | 0x03F | RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x0FC0 |
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x01 | 0x0FC1 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x02 | 0x0FC2 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x03 | 0x0FC3 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x04 | 0x0FC4 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x05 | 0x0FC5 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 | 0x06 | 0x0FC6 | ||
| RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x07 | 0x0FC7 | ||
| AM6_DEV_PRU_ICSSG2 | 0x040 | RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x1000 |
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x01 | 0x1001 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x02 | 0x1002 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x03 | 0x1003 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x04 | 0x1004 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x05 | 0x1005 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 | 0x06 | 0x1006 | ||
| RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 | 0x07 | 0x1007 | ||
| AM6_DEV_NAVSS0 | 0x076 | RESASG_SUBTYPE_NAVSS0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x1D80 |
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x01 | 0x1D81 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x02 | 0x1D82 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x03 | 0x1D83 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x04 | 0x1D84 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x05 | 0x1D85 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x06 | 0x1D86 | ||
| RESASG_SUBTYPE_NAVSS0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x07 | 0x1D87 | ||
| AM6_DEV_NAVSS0_MODSS_INTA0 | 0x0B4 | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x2D0A |
| RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x2D0D | ||
| AM6_DEV_NAVSS0_MODSS_INTA1 | 0x0B5 | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x2D4A |
| RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x2D4D | ||
| AM6_DEV_NAVSS0_RINGACC0 | 0x0BB | RESASG_SUBTYPE_RA_ERROR_OES | 0x00 | 0x2EC0 |
| RESASG_SUBTYPE_RA_GP | 0x01 | 0x2EC1 | ||
| RESASG_SUBTYPE_RA_UDMAP_RX | 0x02 | 0x2EC2 | ||
| RESASG_SUBTYPE_RA_UDMAP_TX | 0x03 | 0x2EC3 | ||
| RESASG_SUBTYPE_RA_UDMAP_TX_EXT | 0x04 | 0x2EC4 | ||
| RESASG_SUBTYPE_RA_UDMAP_RX_H | 0x05 | 0x2EC5 | ||
| RESASG_SUBTYPE_RA_UDMAP_TX_H | 0x07 | 0x2EC7 | ||
| RESASG_SUBTYPE_RA_VIRTID | 0x0A | 0x2ECA | ||
| AM6_DEV_NAVSS0_UDMAP0 | 0x0BC | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON | 0x00 | 0x2F00 |
| RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES | 0x01 | 0x2F01 | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER | 0x02 | 0x2F02 | ||
| RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x2F03 | ||
| RESASG_SUBTYPE_UDMAP_RX_CHAN | 0x0A | 0x2F0A | ||
| RESASG_SUBTYPE_UDMAP_RX_HCHAN | 0x0B | 0x2F0B | ||
| RESASG_SUBTYPE_UDMAP_TX_CHAN | 0x0D | 0x2F0D | ||
| RESASG_SUBTYPE_UDMAP_TX_ECHAN | 0x0E | 0x2F0E | ||
| RESASG_SUBTYPE_UDMAP_TX_HCHAN | 0x0F | 0x2F0F | ||
| AM6_DEV_NAVSS0_UDMASS_INTA0 | 0x0B3 | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x2CCA |
| RESASG_SUBTYPE_GLOBAL_EVENT_GEVT | 0x0B | 0x2CCB | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_MEVT | 0x0C | 0x2CCC | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x2CCD | ||
| AM6_DEV_MCU_NAVSS0_RINGACC0 | 0x0C3 | RESASG_SUBTYPE_RA_ERROR_OES | 0x00 | 0x30C0 |
| RESASG_SUBTYPE_RA_GP | 0x01 | 0x30C1 | ||
| RESASG_SUBTYPE_RA_UDMAP_RX | 0x02 | 0x30C2 | ||
| RESASG_SUBTYPE_RA_UDMAP_TX | 0x03 | 0x30C3 | ||
| RESASG_SUBTYPE_RA_UDMAP_RX_H | 0x05 | 0x30C5 | ||
| RESASG_SUBTYPE_RA_UDMAP_TX_H | 0x07 | 0x30C7 | ||
| RESASG_SUBTYPE_RA_VIRTID | 0x0A | 0x30CA | ||
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 0x0C2 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON | 0x00 | 0x3080 |
| RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES | 0x01 | 0x3081 | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER | 0x02 | 0x3082 | ||
| RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x3083 | ||
| RESASG_SUBTYPE_UDMAP_RX_CHAN | 0x0A | 0x308A | ||
| RESASG_SUBTYPE_UDMAP_RX_HCHAN | 0x0B | 0x308B | ||
| RESASG_SUBTYPE_UDMAP_TX_CHAN | 0x0D | 0x308D | ||
| RESASG_SUBTYPE_UDMAP_TX_HCHAN | 0x0F | 0x308F | ||
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 | 0x0BD | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x2F4A |
| RESASG_SUBTYPE_GLOBAL_EVENT_GEVT | 0x0B | 0x2F4B | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_MEVT | 0x0C | 0x2F4C | ||
| RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x2F4D | ||
| AM6_DEV_PCIE0 | 0x078 | RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x1E00 |
| AM6_DEV_PCIE1 | 0x079 | RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x1E40 |
| AM6_DEV_PDMA1 | 0x07C | RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 | 0x00 | 0x1F00 |
| RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 | 0x01 | 0x1F01 | ||
| AM6_DEV_MCU_ARMSS0_CPU0 | 0x09F | RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 | 0x00 | 0x27C0 |
| RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x01 | 0x27C1 | ||
| RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 | 0x02 | 0x27C2 | ||
| RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 | 0x03 | 0x27C3 | ||
| AM6_DEV_MCU_ARMSS0_CPU1 | 0x0F5 | RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 | 0x00 | 0x3D40 |
| RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 | 0x01 | 0x3D41 | ||
| RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 | 0x02 | 0x3D42 | ||
| RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 | 0x03 | 0x3D43 |