am6 Navigator Subsystem Descriptions¶
Introduction¶
This chapter provides information on the Navigator Subsystems in the am6 SoC. Some System Firmware TISCI messages take Navigator Subsystem specific inputs. This chapter provides information on the valid values for applicable TISCI message parameters.
Navigator Subsystem Device IDs¶
Some System Firmware TISCI message APIs require the device ID of the Navigator Subsystem to be modified as part of the request. Based on am6 Device IDs these are the valid Navigator Subsystem device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| AM6_DEV_NAVSS0_MODSS_INTA0 | 180 |
| AM6_DEV_NAVSS0_MODSS_INTA1 | 181 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 | 179 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 | 189 |
| Ring Accelerator Device Name | Ring Accelerator Device ID |
|---|---|
| AM6_DEV_NAVSS0_RINGACC0 | 187 |
| AM6_DEV_MCU_NAVSS0_RINGACC0 | 195 |
| UDMA Device Name | UDMA Device ID |
|---|---|
| AM6_DEV_NAVSS0_UDMAP0 | 188 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 |
| Proxy Device Name | Proxy Device ID |
|---|---|
| AM6_DEV_NAVSS0_PROXY0 | 185 |
| AM6_DEV_MCU_NAVSS0_PROXY0 | 191 |
| PSI-L Proxy Navigator Device Name | PSI-L Proxy Navigator Device ID |
|---|---|
| AM6_DEV_NAVSS0 | 118 |
| AM6_DEV_MCU_NAVSS0 | 119 |
Navigator Subsystem Ring Indices¶
This section describes valid Navigator Subsystem Ring Accelerator ring indices for each Navigator ring type. The ring index and type ID are used in some Ring Accelerator based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
navss0_ringacc0
| Ring Type | Ring Index Range |
|---|---|
| UDMAP_TX_H (RESERVED BY SYSTEM FIRMWARE) | 0 to 0 |
| UDMAP_TX_H | 1 to 7 |
| UDMAP_TX | 8 to 119 |
| UDMAP_TX_EXT | 120 to 151 |
| UDMAP_RX_H (RESERVED BY SYSTEM FIRMWARE) | 152 to 152 |
| UDMAP_RX_H | 153 to 159 |
| UDMAP_RX | 160 to 301 |
| GP (RESERVED BY SYSTEM FIRMWARE) | 302 to 303 |
| GP | 304 to 767 |
| Monitor Index Range | |
|---|---|
| Ring Monitors | 0 to 31 |
mcu_navss0_ringacc0
| Ring Type | Ring Index Range |
|---|---|
| UDMAP_TX_H | 0 to 1 |
| UDMAP_TX | 2 to 47 |
| UDMAP_RX_H | 48 to 49 |
| UDMAP_RX | 50 to 95 |
| GP | 96 to 255 |
| Monitor Index Range | |
|---|---|
| Ring Monitors | 0 to 31 |
Navigator Subsystem Channel and Flow Indices¶
This section describes valid Navigator Subsystem UDMA transmit channel and receive channel indices for each Navigator UDMA channel type. The receive flow index range has no type information since it’s required for receive flows.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
navss0_udmap0
| Tx Channel Type | Tx Channel Index Range |
|---|---|
| TX_HCHAN (RESERVED BY SYSTEM FIRMWARE) | 0 to 0 |
| TX_HCHAN | 1 to 7 |
| TX_CHAN | 8 to 119 |
| TX_ECHAN | 120 to 151 |
| Rx Channel Type | Rx Channel Index Range |
|---|---|
| RX_HCHAN (RESERVED BY SYSTEM FIRMWARE) | 0 to 1 |
| RX_HCHAN | 2 to 7 |
| RX_CHAN | 8 to 149 |
| Rx Flow Type | Rx Flow Index Range |
|---|---|
| DEFAULT (RESERVED BY SYSTEM FIRMWARE) | 0 to 1 |
| DEFAULT | 2 to 149 |
| CONFIGURABLE | 150 to 299 |
mcu_navss0_udmap0
| Tx Channel Type | Tx Channel Index Range |
|---|---|
| TX_HCHAN | 0 to 1 |
| TX_CHAN | 2 to 47 |
| Rx Channel Type | Rx Channel Index Range |
|---|---|
| RX_HCHAN | 0 to 1 |
| RX_CHAN | 2 to 47 |
| Rx Flow Type | Rx Flow Index Range |
|---|---|
| DEFAULT | 0 to 47 |
| CONFIGURABLE | 48 to 95 |
Navigator Subsystem Virtual Interrupts¶
This section describes Navigator Subsystem virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| AM6_DEV_NAVSS0_MODSS_INTA0 | 0 to 63 |
| AM6_DEV_NAVSS0_MODSS_INTA1 | 0 to 63 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 15 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 | 16 to 255 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 7 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 | 8 to 255 |
Navigator Subsystem Global Events¶
This section describes Navigator Subsystem global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| NAVSS0_UDMASS_INTA0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 15 |
| NAVSS0_UDMASS_INTA0 SEVT | 16 to 4607 |
| MCU_NAVSS0_INTR_AGGR_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 16384 to 16391 |
| MCU_NAVSS0_INTR_AGGR_0 SEVT | 16392 to 17919 |
| NAVSS0_MODSS_INTA0 SEVT | 20480 to 21503 |
| NAVSS0_MODSS_INTA1 SEVT | 22528 to 23551 |
| NAVSS0_UDMASS_INTA0 MEVT | 32768 to 33279 |
| MCU_NAVSS0_INTR_AGGR_0 MEVT | 34816 to 34943 |
| NAVSS0_UDMASS_INTA0 GEVT | 36864 to 37375 |
| MCU_NAVSS0_INTR_AGGR_0 GEVT | 39936 to 40191 |
| NAVSS0_UDMAP0 TRIGGER | 49152 to 50175 |
| MCU_NAVSS0_UDMAP0 TRIGGER | 56320 to 56575 |
Navigator Subsystem Proxies¶
This section describes Navigator Subsystem proxy proxies.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Proxy Name | Proxy Range |
|---|---|
| AM6_DEV_NAVSS0_PROXY0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 0 |
| AM6_DEV_NAVSS0_PROXY0 | 1 to 63 |
| AM6_DEV_MCU_NAVSS0_PROXY0 | 0 to 63 |
Navigator Subsystem PSI-L Source and Destination Thread IDs¶
This section describes valid Navigator Subsystem PSI-L source and destination thread IDs for each thread type. The thread IDs are used in the PSI-L based TISCI messages.
Warning
PSI-L threads marked as reserved for use by DMSC cannot be assigned be linked to another thread.
| Thread Type | Thread Range |
|---|---|
| udmap0_trstrm_tx | 0x8 to 0x8 |
| udmap0_cfgstrm_tx | 0x20 to 0x20 |
| udmap0_tx (Reserved by System Firmware) | 0x1000 to 0x1000 |
| udmap0_tx | 0x1001 to 0x1077 |
| saul0_rx (Reserved by System Firmware) | 0x4000 to 0x4000 |
| saul0_rx | 0x4001 to 0x4003 |
| icssg0_rx | 0x4100 to 0x4104 |
| icssg1_rx | 0x4200 to 0x4204 |
| icssg2_rx | 0x4300 to 0x4304 |
| pdma_main0_mcasp0_rx | 0x4400 to 0x4400 |
| pdma_main0_mcasp1_rx | 0x4401 to 0x4401 |
| pdma_main0_mcasp2_rx | 0x4402 to 0x4402 |
| pdma_main1_spi0_rx | 0x4500 to 0x4503 |
| pdma_main1_spi1_rx | 0x4504 to 0x4507 |
| pdma_main1_spi2_rx | 0x4508 to 0x450b |
| pdma_main1_spi3_rx | 0x450c to 0x450f |
| pdma_main1_spi4_rx | 0x4510 to 0x4513 |
| pdma_main1_usart0_rx | 0x4514 to 0x4514 |
| pdma_main1_usart1_rx | 0x4515 to 0x4515 |
| pdma_main1_usart2_rx | 0x4516 to 0x4516 |
| pdma_debug_mcu_rx | 0x4600 to 0x4600 |
| pdma_debug_main_rx | 0x4601 to 0x4601 |
| pdma_debug_cc_rx | 0x4602 to 0x4602 |
| cal0_rx | 0x4700 to 0x4707 |
| msmc0_rx | 0x4800 to 0x481f |
| navss_mcu_rx | 0x6000 to 0x7fff |
| pdma_cpsw0_rx | 0x7000 to 0x7000 |
| pdma_mcu0_adc12_rx | 0x7100 to 0x7103 |
| pdma_mcu1_spi0_rx | 0x7200 to 0x7203 |
| pdma_mcu1_spi1_rx | 0x7204 to 0x7207 |
| pdma_mcu1_spi2_rx | 0x7208 to 0x720b |
| pdma_mcu1_mcan0_rx | 0x720c to 0x720e |
| pdma_mcu1_mcan1_rx | 0x720f to 0x7211 |
| pdma_mcu1_usart0_rx | 0x7212 to 0x7212 |
| udmap0_rx (Reserved by System Firmware) | 0x9000 to 0x9001 |
| udmap0_rx | 0x9002 to 0x9095 |
| saul0_tx (Reserved by System Firmware) | 0xc000 to 0xc000 |
| saul0_tx | 0xc001 to 0xc001 |
| icssg0_tx | 0xc100 to 0xc108 |
| icssg1_tx | 0xc200 to 0xc208 |
| icssg2_tx | 0xc300 to 0xc308 |
| pdma_main0_mcasp0_tx | 0xc400 to 0xc400 |
| pdma_main0_mcasp1_tx | 0xc401 to 0xc401 |
| pdma_main0_mcasp2_tx | 0xc402 to 0xc402 |
| pdma_main1_spi0_tx | 0xc500 to 0xc503 |
| pdma_main1_spi1_tx | 0xc504 to 0xc507 |
| pdma_main1_spi2_tx | 0xc508 to 0xc50b |
| pdma_main1_spi3_tx | 0xc50c to 0xc50f |
| pdma_main1_spi4_tx | 0xc510 to 0xc513 |
| pdma_main1_usart0_tx | 0xc514 to 0xc514 |
| pdma_main1_usart1_tx | 0xc515 to 0xc515 |
| pdma_main1_usart2_tx | 0xc516 to 0xc516 |
| msmc0_tx | 0xc800 to 0xc81f |
| navss_mcu_tx | 0xe000 to 0xffff |
| pdma_cpsw0_tx | 0xf000 to 0xf007 |
| pdma_mcu0_adc12_tx | 0xf100 to 0xf103 |
| pdma_mcu1_spi0_tx | 0xf200 to 0xf203 |
| pdma_mcu1_spi1_tx | 0xf204 to 0xf207 |
| pdma_mcu1_spi2_tx | 0xf208 to 0xf20b |
| pdma_mcu1_mcan0_tx | 0xf20c to 0xf20e |
| pdma_mcu1_mcan1_tx | 0xf20f to 0xf211 |
| pdma_mcu1_usart0_tx | 0xf212 to 0xf212 |