MSP432E4 DriverLib API Guide  1.11.00.03
Data Structures | Macros | Functions
udma.h File Reference
#include <stdint.h>
#include <stdbool.h>
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Data Structures

struct  tDMAControlTable
 

Macros

#define uDMATaskStructEntry(ui32TransferCount, ui32ItemSize, ui32SrcIncrement, pvSrcAddr, ui32DstIncrement, pvDstAddr, ui32ArbSize, ui32Mode)
 
#define UDMA_ATTR_USEBURST   0x00000001
 
#define UDMA_ATTR_ALTSELECT   0x00000002
 
#define UDMA_ATTR_HIGH_PRIORITY   0x00000004
 
#define UDMA_ATTR_REQMASK   0x00000008
 
#define UDMA_ATTR_ALL   0x0000000F
 
#define UDMA_MODE_STOP   0x00000000
 
#define UDMA_MODE_BASIC   0x00000001
 
#define UDMA_MODE_AUTO   0x00000002
 
#define UDMA_MODE_PINGPONG   0x00000003
 
#define UDMA_MODE_MEM_SCATTER_GATHER   0x00000004
 
#define UDMA_MODE_PER_SCATTER_GATHER   0x00000006
 
#define UDMA_MODE_ALT_SELECT   0x00000001
 
#define UDMA_DST_INC_8   0x00000000
 
#define UDMA_DST_INC_16   0x40000000
 
#define UDMA_DST_INC_32   0x80000000
 
#define UDMA_DST_INC_NONE   0xc0000000
 
#define UDMA_SRC_INC_8   0x00000000
 
#define UDMA_SRC_INC_16   0x04000000
 
#define UDMA_SRC_INC_32   0x08000000
 
#define UDMA_SRC_INC_NONE   0x0c000000
 
#define UDMA_SIZE_8   0x00000000
 
#define UDMA_SIZE_16   0x11000000
 
#define UDMA_SIZE_32   0x22000000
 
#define UDMA_DST_PROT_PRIV   0x00200000
 
#define UDMA_SRC_PROT_PRIV   0x00040000
 
#define UDMA_ARB_1   0x00000000
 
#define UDMA_ARB_2   0x00004000
 
#define UDMA_ARB_4   0x00008000
 
#define UDMA_ARB_8   0x0000c000
 
#define UDMA_ARB_16   0x00010000
 
#define UDMA_ARB_32   0x00014000
 
#define UDMA_ARB_64   0x00018000
 
#define UDMA_ARB_128   0x0001c000
 
#define UDMA_ARB_256   0x00020000
 
#define UDMA_ARB_512   0x00024000
 
#define UDMA_ARB_1024   0x00028000
 
#define UDMA_NEXT_USEBURST   0x00000008
 
#define UDMA_PRI_SELECT   0x00000000
 
#define UDMA_ALT_SELECT   0x00000020
 
#define UDMA_CH0_RESERVED0   0x00000000
 
#define UDMA_CH0_UART2RX   0x00010000
 
#define UDMA_CH0_RESERVED2   0x00020000
 
#define UDMA_CH0_TIMER4A   0x00030000
 
#define UDMA_CH0_RESERVED4   0x00040000
 
#define UDMA_CH0_RESERVED5   0x00050000
 
#define UDMA_CH0_I2C0RX   0x00060000
 
#define UDMA_CH0_RESERVED7   0x00070000
 
#define UDMA_CH0_RESERVED8   0x00080000
 
#define UDMA_CH1_RESERVED0   0x00000001
 
#define UDMA_CH1_UART2TX   0x00010001
 
#define UDMA_CH1_RESERVED2   0x00020001
 
#define UDMA_CH1_TIMER4B   0x00030001
 
#define UDMA_CH1_RESERVED4   0x00040001
 
#define UDMA_CH1_RESERVED5   0x00050001
 
#define UDMA_CH1_I2C0TX   0x00060001
 
#define UDMA_CH1_RESERVED7   0x00070001
 
#define UDMA_CH1_RESERVED8   0x00080001
 
#define UDMA_CH2_RESERVED0   0x00000002
 
#define UDMA_CH2_TIMER3A   0x00010002
 
#define UDMA_CH2_RESERVED2   0x00020002
 
#define UDMA_CH2_RESERVED3   0x00030002
 
#define UDMA_CH2_RESERVED4   0x00040002
 
#define UDMA_CH2_RESERVED5   0x00050002
 
#define UDMA_CH2_I2C1RX   0x00060002
 
#define UDMA_CH2_RESERVED7   0x00070002
 
#define UDMA_CH2_RESERVED8   0x00080002
 
#define UDMA_CH3_RESERVED0   0x00000003
 
#define UDMA_CH3_TIMER3B   0x00010003
 
#define UDMA_CH3_RESERVED2   0x00020003
 
#define UDMA_CH3_RESERVED3   0x00030003
 
#define UDMA_CH3_RESERVED4   0x00040003
 
#define UDMA_CH3_RESERVED5   0x00050003
 
#define UDMA_CH3_I2C1TX   0x00060003
 
#define UDMA_CH3_RESERVED7   0x00070003
 
#define UDMA_CH3_RESERVED8   0x00080003
 
#define UDMA_CH4_RESERVED0   0x00000004
 
#define UDMA_CH4_TIMER2A   0x00010004
 
#define UDMA_CH4_RESERVED2   0x00020004
 
#define UDMA_CH4_GPIOA   0x00030004
 
#define UDMA_CH4_RESERVED4   0x00040004
 
#define UDMA_CH4_SHAMD50CIN   0x00050004
 
#define UDMA_CH4_I2C2RX   0x00060004
 
#define UDMA_CH4_RESERVED7   0x00070004
 
#define UDMA_CH4_RESERVED8   0x00080004
 
#define UDMA_CH5_RESERVED0   0x00000005
 
#define UDMA_CH5_TIMER2B   0x00010005
 
#define UDMA_CH5_RESERVED2   0x00020005
 
#define UDMA_CH5_GPIOB   0x00030005
 
#define UDMA_CH5_RESERVED4   0x00040005
 
#define UDMA_CH5_SHAMD50DIN   0x00050005
 
#define UDMA_CH5_I2C2TX   0x00060005
 
#define UDMA_CH5_RESERVED7   0x00070005
 
#define UDMA_CH5_RESERVED8   0x00080005
 
#define UDMA_CH6_RESERVED0   0x00000006
 
#define UDMA_CH6_TIMER2A   0x00010006
 
#define UDMA_CH6_UART5RX   0x00020006
 
#define UDMA_CH6_GPIOC   0x00030006
 
#define UDMA_CH6_I2C0RX   0x00040006
 
#define UDMA_CH6_SHAMD50COUT   0x00050006
 
#define UDMA_CH6_RESERVED6   0x00060006
 
#define UDMA_CH6_RESERVED7   0x00070006
 
#define UDMA_CH6_RESERVED8   0x00080006
 
#define UDMA_CH7_RESERVED0   0x00000007
 
#define UDMA_CH7_TIMER2B   0x00010007
 
#define UDMA_CH7_UART5TX   0x00020007
 
#define UDMA_CH7_GPIOD   0x00030007
 
#define UDMA_CH7_I2C0TX   0x00040007
 
#define UDMA_CH7_RESERVED5   0x00050007
 
#define UDMA_CH7_RESERVED6   0x00060007
 
#define UDMA_CH7_RESERVED7   0x00070007
 
#define UDMA_CH7_RESERVED8   0x00080007
 
#define UDMA_CH8_UART0RX   0x00000008
 
#define UDMA_CH8_UART1RX   0x00010008
 
#define UDMA_CH8_RESERVED2   0x00020008
 
#define UDMA_CH8_TIMER5A   0x00030008
 
#define UDMA_CH8_I2C1RX   0x00040008
 
#define UDMA_CH8_RESERVED5   0x00050008
 
#define UDMA_CH8_RESERVED6   0x00060008
 
#define UDMA_CH8_RESERVED7   0x00070008
 
#define UDMA_CH8_RESERVED8   0x00080008
 
#define UDMA_CH9_UART0TX   0x00000009
 
#define UDMA_CH9_UART1TX   0x00010009
 
#define UDMA_CH9_RESERVED2   0x00020009
 
#define UDMA_CH9_TIMER5B   0x00030009
 
#define UDMA_CH9_I2C1TX   0x00040009
 
#define UDMA_CH9_RESERVED5   0x00050009
 
#define UDMA_CH9_RESERVED6   0x00060009
 
#define UDMA_CH9_RESERVED7   0x00070009
 
#define UDMA_CH9_RESERVED8   0x00080009
 
#define UDMA_CH10_SSI0RX   0x0000000A
 
#define UDMA_CH10_SSI1RX   0x0001000A
 
#define UDMA_CH10_UART6RX   0x0002000A
 
#define UDMA_CH10_RESERVED3   0x0003000A
 
#define UDMA_CH10_I2C2RX   0x0004000A
 
#define UDMA_CH10_RESERVED5   0x0005000A
 
#define UDMA_CH10_RESERVED6   0x0006000A
 
#define UDMA_CH10_TIMER6A   0x0007000A
 
#define UDMA_CH10_RESERVED8   0x0008000A
 
#define UDMA_CH11_SSI0TX   0x0000000B
 
#define UDMA_CH11_SSI1TX   0x0001000B
 
#define UDMA_CH11_UART6TX   0x0002000B
 
#define UDMA_CH11_RESERVED3   0x0003000B
 
#define UDMA_CH11_I2C2TX   0x0004000B
 
#define UDMA_CH11_RESERVED5   0x0005000B
 
#define UDMA_CH11_RESERVED6   0x0006000B
 
#define UDMA_CH11_TIMER6B   0x0007000B
 
#define UDMA_CH11_RESERVED8   0x0008000B
 
#define UDMA_CH12_RESERVED0   0x0000000C
 
#define UDMA_CH12_UART2RX   0x0001000C
 
#define UDMA_CH12_SSI2RX   0x0002000C
 
#define UDMA_CH12_RESERVED3   0x0003000C
 
#define UDMA_CH12_GPIOK   0x0004000C
 
#define UDMA_CH12_AES0CIN   0x0005000C
 
#define UDMA_CH12_RESERVED6   0x0006000C
 
#define UDMA_CH12_TIMER7A   0x0007000C
 
#define UDMA_CH12_RESERVED8   0x0008000C
 
#define UDMA_CH13_RESERVED0   0x0000000D
 
#define UDMA_CH13_UART2TX   0x0001000D
 
#define UDMA_CH13_SSI2TX   0x0002000D
 
#define UDMA_CH13_RESERVED3   0x0003000D
 
#define UDMA_CH13_GPIOL   0x0004000D
 
#define UDMA_CH13_AES0COUT   0x0005000D
 
#define UDMA_CH13_RESERVED6   0x0006000D
 
#define UDMA_CH13_TIMER7B   0x0007000D
 
#define UDMA_CH13_RESERVED8   0x0008000D
 
#define UDMA_CH14_ADC0_0   0x0000000E
 
#define UDMA_CH14_TIMER2A   0x0001000E
 
#define UDMA_CH14_SSI3RX   0x0002000E
 
#define UDMA_CH14_GPIOE   0x0003000E
 
#define UDMA_CH14_GPIOM   0x0004000E
 
#define UDMA_CH14_AES0DIN   0x0005000E
 
#define UDMA_CH14_RESERVED6   0x0006000E
 
#define UDMA_CH14_RESERVED7   0x0007000E
 
#define UDMA_CH14_RESERVED8   0x0008000E
 
#define UDMA_CH15_ADC0_1   0x0000000F
 
#define UDMA_CH15_TIMER2B   0x0001000F
 
#define UDMA_CH15_SSI3TX   0x0002000F
 
#define UDMA_CH15_GPIOF   0x0003000F
 
#define UDMA_CH15_GPION   0x0004000F
 
#define UDMA_CH15_AES0DOUT   0x0005000F
 
#define UDMA_CH15_RESERVED6   0x0006000F
 
#define UDMA_CH15_RESERVED7   0x0007000F
 
#define UDMA_CH15_RESERVED8   0x0008000F
 
#define UDMA_CH16_ADC0_2   0x00000010
 
#define UDMA_CH16_RESERVED1   0x00010010
 
#define UDMA_CH16_UART3RX   0x00020010
 
#define UDMA_CH16_RESERVED3   0x00030010
 
#define UDMA_CH16_GPIOP   0x00040010
 
#define UDMA_CH16_RESERVED5   0x00050010
 
#define UDMA_CH16_RESERVED6   0x00060010
 
#define UDMA_CH16_RESERVED7   0x00070010
 
#define UDMA_CH16_RESERVED8   0x00080010
 
#define UDMA_CH17_ADC0_3   0x00000011
 
#define UDMA_CH17_RESERVED1   0x00010011
 
#define UDMA_CH17_UART3TX   0x00020011
 
#define UDMA_CH17_RESERVED3   0x00030011
 
#define UDMA_CH17_RESERVED4   0x00040011
 
#define UDMA_CH17_RESERVED5   0x00050011
 
#define UDMA_CH17_RESERVED6   0x00060011
 
#define UDMA_CH17_RESERVED7   0x00070011
 
#define UDMA_CH17_RESERVED8   0x00080011
 
#define UDMA_CH18_TIMER0A   0x00000012
 
#define UDMA_CH18_TIMER1A   0x00010012
 
#define UDMA_CH18_UART4RX   0x00020012
 
#define UDMA_CH18_GPIOB   0x00030012
 
#define UDMA_CH18_I2C3RX   0x00040012
 
#define UDMA_CH18_RESERVED5   0x00050012
 
#define UDMA_CH18_RESERVED6   0x00060012
 
#define UDMA_CH18_RESERVED7   0x00070012
 
#define UDMA_CH18_RESERVED8   0x00080012
 
#define UDMA_CH19_TIMER0B   0x00000013
 
#define UDMA_CH19_TIMER1B   0x00010013
 
#define UDMA_CH19_UART4TX   0x00020013
 
#define UDMA_CH19_GPIOG   0x00030013
 
#define UDMA_CH19_I2C3TX   0x00040013
 
#define UDMA_CH19_RESERVED5   0x00050013
 
#define UDMA_CH19_RESERVED6   0x00060013
 
#define UDMA_CH19_RESERVED7   0x00070013
 
#define UDMA_CH19_RESERVED8   0x00080013
 
#define UDMA_CH20_TIMER1A   0x00000014
 
#define UDMA_CH20_EPI0RX   0x00010014
 
#define UDMA_CH20_UART7RX   0x00020014
 
#define UDMA_CH20_GPIOH   0x00030014
 
#define UDMA_CH20_I2C4RX   0x00040014
 
#define UDMA_CH20_DES0CIN   0x00050014
 
#define UDMA_CH20_RESERVED6   0x00060014
 
#define UDMA_CH20_RESERVED7   0x00070014
 
#define UDMA_CH20_RESERVED8   0x00080014
 
#define UDMA_CH21_TIMER1B   0x00000015
 
#define UDMA_CH21_EPI0TX   0x00010015
 
#define UDMA_CH21_UART7TX   0x00020015
 
#define UDMA_CH21_GPIOJ   0x00030015
 
#define UDMA_CH21_I2C4TX   0x00040015
 
#define UDMA_CH21_DES0DIN   0x00050015
 
#define UDMA_CH21_RESERVED6   0x00060015
 
#define UDMA_CH21_RESERVED7   0x00070015
 
#define UDMA_CH21_RESERVED8   0x00080015
 
#define UDMA_CH22_UART1RX   0x00000016
 
#define UDMA_CH22_RESERVED1   0x00010016
 
#define UDMA_CH22_RESERVED2   0x00020016
 
#define UDMA_CH22_RESERVED3   0x00030016
 
#define UDMA_CH22_I2C5RX   0x00040016
 
#define UDMA_CH22_DES0DOUT   0x00050016
 
#define UDMA_CH22_RESERVED6   0x00060016
 
#define UDMA_CH22_RESERVED7   0x00070016
 
#define UDMA_CH22_I2C8RX   0x00080016
 
#define UDMA_CH23_UART1TX   0x00000017
 
#define UDMA_CH23_RESERVED1   0x00010017
 
#define UDMA_CH23_RESERVED2   0x00020017
 
#define UDMA_CH23_RESERVED3   0x00030017
 
#define UDMA_CH23_I2C5TX   0x00040017
 
#define UDMA_CH23_RESERVED5   0x00050017
 
#define UDMA_CH23_RESERVED6   0x00060017
 
#define UDMA_CH23_RESERVED7   0x00070017
 
#define UDMA_CH23_I2C8TX   0x00080017
 
#define UDMA_CH24_SSI1RX   0x00000018
 
#define UDMA_CH24_ADC1_0   0x00010018
 
#define UDMA_CH24_RESERVED2   0x00020018
 
#define UDMA_CH24_RESERVED3   0x00030018
 
#define UDMA_CH24_GPIOQ   0x00040018
 
#define UDMA_CH24_RESERVED5   0x00050018
 
#define UDMA_CH24_RESERVED6   0x00060018
 
#define UDMA_CH24_RESERVED7   0x00070018
 
#define UDMA_CH24_I2C9RX   0x00080018
 
#define UDMA_CH25_SSI1TX   0x00000019
 
#define UDMA_CH25_ADC1_1   0x00010019
 
#define UDMA_CH25_RESERVED2   0x00020019
 
#define UDMA_CH25_RESERVED3   0x00030019
 
#define UDMA_CH25_GPIOR   0x00040019
 
#define UDMA_CH25_RESERVED5   0x00050019
 
#define UDMA_CH25_RESERVED6   0x00060019
 
#define UDMA_CH25_RESERVED7   0x00070019
 
#define UDMA_CH25_I2C9TX   0x00080019
 
#define UDMA_CH26_RESERVED0   0x0000001A
 
#define UDMA_CH26_ADC1_2   0x0001001A
 
#define UDMA_CH26_RESERVED2   0x0002001A
 
#define UDMA_CH26_RESERVED3   0x0003001A
 
#define UDMA_CH26_GPIOS   0x0004001A
 
#define UDMA_CH26_RESERVED5   0x0005001A
 
#define UDMA_CH26_RESERVED6   0x0006001A
 
#define UDMA_CH26_RESERVED7   0x0007001A
 
#define UDMA_CH26_I2C6RX   0x0008001A
 
#define UDMA_CH27_RESERVED0   0x0000001B
 
#define UDMA_CH27_ADC1_3   0x0001001B
 
#define UDMA_CH27_RESERVED2   0x0002001B
 
#define UDMA_CH27_RESERVED3   0x0003001B
 
#define UDMA_CH27_RESERVED4   0x0004001B
 
#define UDMA_CH27_RESERVED5   0x0005001B
 
#define UDMA_CH27_GPIOT   0x0006001B
 
#define UDMA_CH27_RESERVED7   0x0007001B
 
#define UDMA_CH27_I2C6TX   0x0008001B
 
#define UDMA_CH28_RESERVED0   0x0000001C
 
#define UDMA_CH28_RESERVED1   0x0001001C
 
#define UDMA_CH28_RESERVED2   0x0002001C
 
#define UDMA_CH28_RESERVED3   0x0003001C
 
#define UDMA_CH28_RESERVED4   0x0004001C
 
#define UDMA_CH28_RESERVED5   0x0005001C
 
#define UDMA_CH28_RESERVED6   0x0006001C
 
#define UDMA_CH28_RESERVED7   0x0007001C
 
#define UDMA_CH28_I2C7RX   0x0008001C
 
#define UDMA_CH29_RESERVED0   0x0000001D
 
#define UDMA_CH29_RESERVED1   0x0001001D
 
#define UDMA_CH29_RESERVED2   0x0002001D
 
#define UDMA_CH29_RESERVED3   0x0003001D
 
#define UDMA_CH29_RESERVED4   0x0004001D
 
#define UDMA_CH29_RESERVED5   0x0005001D
 
#define UDMA_CH29_RESERVED6   0x0006001D
 
#define UDMA_CH29_RESERVED7   0x0007001D
 
#define UDMA_CH29_I2C7TX   0x0008001D
 
#define UDMA_CH30_SW   0x0000001E
 
#define UDMA_CH30_RESERVED1   0x0001001E
 
#define UDMA_CH30_RESERVED2   0x0002001E
 
#define UDMA_CH30_RESERVED3   0x0003001E
 
#define UDMA_CH30_RESERVED4   0x0004001E
 
#define UDMA_CH30_RESERVED5   0x0005001E
 
#define UDMA_CH30_RESERVED6   0x0006001E
 
#define UDMA_CH30_EPI0RX   0x0007001E
 
#define UDMA_CH30_1WIRE0   0x0008001E
 
#define UDMA_CH31_RESERVED0   0x0000001F
 
#define UDMA_CH31_RESERVED1   0x0001001F
 
#define UDMA_CH31_RESERVED2   0x0002001F
 
#define UDMA_CH31_RESERVED3   0x0003001F
 
#define UDMA_CH31_RESERVED4   0x0004001F
 
#define UDMA_CH31_RESERVED5   0x0005001F
 
#define UDMA_CH31_RESERVED6   0x0006001F
 
#define UDMA_CH31_EPI0RX   0x0007001F
 
#define UDMA_CH31_RESERVED8   0x0008001F
 

Functions

void uDMAInit (void)
 
void uDMAEnable (void)
 
void uDMADisable (void)
 
uint32_t uDMAErrorStatusGet (void)
 
void uDMAErrorStatusClear (void)
 
void uDMAChannelEnable (uint32_t ui32ChannelNum)
 
void uDMAChannelDisable (uint32_t ui32ChannelNum)
 
bool uDMAChannelIsEnabled (uint32_t ui32ChannelNum)
 
void uDMAControlBaseSet (void *pControlTable)
 
void * uDMAControlBaseGet (void)
 
void * uDMAControlAlternateBaseGet (void)
 
void uDMAChannelRequest (uint32_t ui32ChannelNum)
 
void uDMAChannelAttributeEnable (uint32_t ui32ChannelNum, uint32_t ui32Attr)
 
void uDMAChannelAttributeDisable (uint32_t ui32ChannelNum, uint32_t ui32Attr)
 
uint32_t uDMAChannelAttributeGet (uint32_t ui32ChannelNum)
 
void uDMAChannelControlSet (uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
 
void uDMAChannelTransferSet (uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)
 
void uDMAChannelScatterGatherSet (uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)
 
uint32_t uDMAChannelSizeGet (uint32_t ui32ChannelStructIndex)
 
uint32_t uDMAChannelModeGet (uint32_t ui32ChannelStructIndex)
 
void uDMAIntRegister (uint32_t ui32IntChannel, void(*pfnHandler)(void))
 
void uDMAIntUnregister (uint32_t ui32IntChannel)
 
void uDMAChannelAssign (uint32_t ui32Mapping)
 

Macro Definition Documentation

§ UDMA_ATTR_USEBURST

#define UDMA_ATTR_USEBURST   0x00000001

Referenced by uDMAChannelAttributeDisable(), uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_ATTR_ALTSELECT

#define UDMA_ATTR_ALTSELECT   0x00000002

Referenced by uDMAChannelAttributeDisable(), uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_ATTR_HIGH_PRIORITY

#define UDMA_ATTR_HIGH_PRIORITY   0x00000004

Referenced by uDMAChannelAttributeDisable(), uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_ATTR_REQMASK

#define UDMA_ATTR_REQMASK   0x00000008

Referenced by uDMAChannelAttributeDisable(), uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_ATTR_ALL

#define UDMA_ATTR_ALL   0x0000000F

§ UDMA_MODE_STOP

#define UDMA_MODE_STOP   0x00000000

§ UDMA_MODE_BASIC

#define UDMA_MODE_BASIC   0x00000001

§ UDMA_MODE_AUTO

#define UDMA_MODE_AUTO   0x00000002

§ UDMA_MODE_PINGPONG

#define UDMA_MODE_PINGPONG   0x00000003

§ UDMA_MODE_MEM_SCATTER_GATHER

#define UDMA_MODE_MEM_SCATTER_GATHER   0x00000004

Referenced by uDMAChannelModeGet(), and uDMAChannelTransferSet().

§ UDMA_MODE_PER_SCATTER_GATHER

#define UDMA_MODE_PER_SCATTER_GATHER   0x00000006

Referenced by uDMAChannelModeGet(), and uDMAChannelTransferSet().

§ UDMA_MODE_ALT_SELECT

#define UDMA_MODE_ALT_SELECT   0x00000001

Referenced by uDMAChannelModeGet(), and uDMAChannelTransferSet().

§ UDMA_DST_INC_8

#define UDMA_DST_INC_8   0x00000000

§ UDMA_DST_INC_16

#define UDMA_DST_INC_16   0x40000000

§ UDMA_DST_INC_32

#define UDMA_DST_INC_32   0x80000000

§ UDMA_DST_INC_NONE

#define UDMA_DST_INC_NONE   0xc0000000

Referenced by uDMAChannelTransferSet().

§ UDMA_SRC_INC_8

#define UDMA_SRC_INC_8   0x00000000

§ UDMA_SRC_INC_16

#define UDMA_SRC_INC_16   0x04000000

§ UDMA_SRC_INC_32

#define UDMA_SRC_INC_32   0x08000000

§ UDMA_SRC_INC_NONE

#define UDMA_SRC_INC_NONE   0x0c000000

Referenced by uDMAChannelTransferSet().

§ UDMA_SIZE_8

#define UDMA_SIZE_8   0x00000000

§ UDMA_SIZE_16

#define UDMA_SIZE_16   0x11000000

§ UDMA_SIZE_32

#define UDMA_SIZE_32   0x22000000

§ UDMA_DST_PROT_PRIV

#define UDMA_DST_PROT_PRIV   0x00200000

§ UDMA_SRC_PROT_PRIV

#define UDMA_SRC_PROT_PRIV   0x00040000

§ UDMA_ARB_1

#define UDMA_ARB_1   0x00000000

§ UDMA_ARB_2

#define UDMA_ARB_2   0x00004000

§ UDMA_ARB_4

#define UDMA_ARB_4   0x00008000

§ UDMA_ARB_8

#define UDMA_ARB_8   0x0000c000

§ UDMA_ARB_16

#define UDMA_ARB_16   0x00010000

§ UDMA_ARB_32

#define UDMA_ARB_32   0x00014000

§ UDMA_ARB_64

#define UDMA_ARB_64   0x00018000

§ UDMA_ARB_128

#define UDMA_ARB_128   0x0001c000

§ UDMA_ARB_256

#define UDMA_ARB_256   0x00020000

§ UDMA_ARB_512

#define UDMA_ARB_512   0x00024000

§ UDMA_ARB_1024

#define UDMA_ARB_1024   0x00028000

§ UDMA_NEXT_USEBURST

#define UDMA_NEXT_USEBURST   0x00000008

§ UDMA_PRI_SELECT

#define UDMA_PRI_SELECT   0x00000000

§ UDMA_ALT_SELECT

#define UDMA_ALT_SELECT   0x00000020

Referenced by uDMAChannelScatterGatherSet(), and uDMAChannelTransferSet().

§ UDMA_CH0_RESERVED0

#define UDMA_CH0_RESERVED0   0x00000000

§ UDMA_CH0_UART2RX

#define UDMA_CH0_UART2RX   0x00010000

§ UDMA_CH0_RESERVED2

#define UDMA_CH0_RESERVED2   0x00020000

§ UDMA_CH0_TIMER4A

#define UDMA_CH0_TIMER4A   0x00030000

§ UDMA_CH0_RESERVED4

#define UDMA_CH0_RESERVED4   0x00040000

§ UDMA_CH0_RESERVED5

#define UDMA_CH0_RESERVED5   0x00050000

§ UDMA_CH0_I2C0RX

#define UDMA_CH0_I2C0RX   0x00060000

§ UDMA_CH0_RESERVED7

#define UDMA_CH0_RESERVED7   0x00070000

§ UDMA_CH0_RESERVED8

#define UDMA_CH0_RESERVED8   0x00080000

§ UDMA_CH1_RESERVED0

#define UDMA_CH1_RESERVED0   0x00000001

§ UDMA_CH1_UART2TX

#define UDMA_CH1_UART2TX   0x00010001

§ UDMA_CH1_RESERVED2

#define UDMA_CH1_RESERVED2   0x00020001

§ UDMA_CH1_TIMER4B

#define UDMA_CH1_TIMER4B   0x00030001

§ UDMA_CH1_RESERVED4

#define UDMA_CH1_RESERVED4   0x00040001

§ UDMA_CH1_RESERVED5

#define UDMA_CH1_RESERVED5   0x00050001

§ UDMA_CH1_I2C0TX

#define UDMA_CH1_I2C0TX   0x00060001

§ UDMA_CH1_RESERVED7

#define UDMA_CH1_RESERVED7   0x00070001

§ UDMA_CH1_RESERVED8

#define UDMA_CH1_RESERVED8   0x00080001

§ UDMA_CH2_RESERVED0

#define UDMA_CH2_RESERVED0   0x00000002

§ UDMA_CH2_TIMER3A

#define UDMA_CH2_TIMER3A   0x00010002

§ UDMA_CH2_RESERVED2

#define UDMA_CH2_RESERVED2   0x00020002

§ UDMA_CH2_RESERVED3

#define UDMA_CH2_RESERVED3   0x00030002

§ UDMA_CH2_RESERVED4

#define UDMA_CH2_RESERVED4   0x00040002

§ UDMA_CH2_RESERVED5

#define UDMA_CH2_RESERVED5   0x00050002

§ UDMA_CH2_I2C1RX

#define UDMA_CH2_I2C1RX   0x00060002

§ UDMA_CH2_RESERVED7

#define UDMA_CH2_RESERVED7   0x00070002

§ UDMA_CH2_RESERVED8

#define UDMA_CH2_RESERVED8   0x00080002

§ UDMA_CH3_RESERVED0

#define UDMA_CH3_RESERVED0   0x00000003

§ UDMA_CH3_TIMER3B

#define UDMA_CH3_TIMER3B   0x00010003

§ UDMA_CH3_RESERVED2

#define UDMA_CH3_RESERVED2   0x00020003

§ UDMA_CH3_RESERVED3

#define UDMA_CH3_RESERVED3   0x00030003

§ UDMA_CH3_RESERVED4

#define UDMA_CH3_RESERVED4   0x00040003

§ UDMA_CH3_RESERVED5

#define UDMA_CH3_RESERVED5   0x00050003

§ UDMA_CH3_I2C1TX

#define UDMA_CH3_I2C1TX   0x00060003

§ UDMA_CH3_RESERVED7

#define UDMA_CH3_RESERVED7   0x00070003

§ UDMA_CH3_RESERVED8

#define UDMA_CH3_RESERVED8   0x00080003

§ UDMA_CH4_RESERVED0

#define UDMA_CH4_RESERVED0   0x00000004

§ UDMA_CH4_TIMER2A

#define UDMA_CH4_TIMER2A   0x00010004

§ UDMA_CH4_RESERVED2

#define UDMA_CH4_RESERVED2   0x00020004

§ UDMA_CH4_GPIOA

#define UDMA_CH4_GPIOA   0x00030004

§ UDMA_CH4_RESERVED4

#define UDMA_CH4_RESERVED4   0x00040004

§ UDMA_CH4_SHAMD50CIN

#define UDMA_CH4_SHAMD50CIN   0x00050004

§ UDMA_CH4_I2C2RX

#define UDMA_CH4_I2C2RX   0x00060004

§ UDMA_CH4_RESERVED7

#define UDMA_CH4_RESERVED7   0x00070004

§ UDMA_CH4_RESERVED8

#define UDMA_CH4_RESERVED8   0x00080004

§ UDMA_CH5_RESERVED0

#define UDMA_CH5_RESERVED0   0x00000005

§ UDMA_CH5_TIMER2B

#define UDMA_CH5_TIMER2B   0x00010005

§ UDMA_CH5_RESERVED2

#define UDMA_CH5_RESERVED2   0x00020005

§ UDMA_CH5_GPIOB

#define UDMA_CH5_GPIOB   0x00030005

§ UDMA_CH5_RESERVED4

#define UDMA_CH5_RESERVED4   0x00040005

§ UDMA_CH5_SHAMD50DIN

#define UDMA_CH5_SHAMD50DIN   0x00050005

§ UDMA_CH5_I2C2TX

#define UDMA_CH5_I2C2TX   0x00060005

§ UDMA_CH5_RESERVED7

#define UDMA_CH5_RESERVED7   0x00070005

§ UDMA_CH5_RESERVED8

#define UDMA_CH5_RESERVED8   0x00080005

§ UDMA_CH6_RESERVED0

#define UDMA_CH6_RESERVED0   0x00000006

§ UDMA_CH6_TIMER2A

#define UDMA_CH6_TIMER2A   0x00010006

§ UDMA_CH6_UART5RX

#define UDMA_CH6_UART5RX   0x00020006

§ UDMA_CH6_GPIOC

#define UDMA_CH6_GPIOC   0x00030006

§ UDMA_CH6_I2C0RX

#define UDMA_CH6_I2C0RX   0x00040006

§ UDMA_CH6_SHAMD50COUT

#define UDMA_CH6_SHAMD50COUT   0x00050006

§ UDMA_CH6_RESERVED6

#define UDMA_CH6_RESERVED6   0x00060006

§ UDMA_CH6_RESERVED7

#define UDMA_CH6_RESERVED7   0x00070006

§ UDMA_CH6_RESERVED8

#define UDMA_CH6_RESERVED8   0x00080006

§ UDMA_CH7_RESERVED0

#define UDMA_CH7_RESERVED0   0x00000007

§ UDMA_CH7_TIMER2B

#define UDMA_CH7_TIMER2B   0x00010007

§ UDMA_CH7_UART5TX

#define UDMA_CH7_UART5TX   0x00020007

§ UDMA_CH7_GPIOD

#define UDMA_CH7_GPIOD   0x00030007

§ UDMA_CH7_I2C0TX

#define UDMA_CH7_I2C0TX   0x00040007

§ UDMA_CH7_RESERVED5

#define UDMA_CH7_RESERVED5   0x00050007

§ UDMA_CH7_RESERVED6

#define UDMA_CH7_RESERVED6   0x00060007

§ UDMA_CH7_RESERVED7

#define UDMA_CH7_RESERVED7   0x00070007

§ UDMA_CH7_RESERVED8

#define UDMA_CH7_RESERVED8   0x00080007

§ UDMA_CH8_UART0RX

#define UDMA_CH8_UART0RX   0x00000008

§ UDMA_CH8_UART1RX

#define UDMA_CH8_UART1RX   0x00010008

§ UDMA_CH8_RESERVED2

#define UDMA_CH8_RESERVED2   0x00020008

§ UDMA_CH8_TIMER5A

#define UDMA_CH8_TIMER5A   0x00030008

§ UDMA_CH8_I2C1RX

#define UDMA_CH8_I2C1RX   0x00040008

§ UDMA_CH8_RESERVED5

#define UDMA_CH8_RESERVED5   0x00050008

§ UDMA_CH8_RESERVED6

#define UDMA_CH8_RESERVED6   0x00060008

§ UDMA_CH8_RESERVED7

#define UDMA_CH8_RESERVED7   0x00070008

§ UDMA_CH8_RESERVED8

#define UDMA_CH8_RESERVED8   0x00080008

§ UDMA_CH9_UART0TX

#define UDMA_CH9_UART0TX   0x00000009

§ UDMA_CH9_UART1TX

#define UDMA_CH9_UART1TX   0x00010009

§ UDMA_CH9_RESERVED2

#define UDMA_CH9_RESERVED2   0x00020009

§ UDMA_CH9_TIMER5B

#define UDMA_CH9_TIMER5B   0x00030009

§ UDMA_CH9_I2C1TX

#define UDMA_CH9_I2C1TX   0x00040009

§ UDMA_CH9_RESERVED5

#define UDMA_CH9_RESERVED5   0x00050009

§ UDMA_CH9_RESERVED6

#define UDMA_CH9_RESERVED6   0x00060009

§ UDMA_CH9_RESERVED7

#define UDMA_CH9_RESERVED7   0x00070009

§ UDMA_CH9_RESERVED8

#define UDMA_CH9_RESERVED8   0x00080009

§ UDMA_CH10_SSI0RX

#define UDMA_CH10_SSI0RX   0x0000000A

§ UDMA_CH10_SSI1RX

#define UDMA_CH10_SSI1RX   0x0001000A

§ UDMA_CH10_UART6RX

#define UDMA_CH10_UART6RX   0x0002000A

§ UDMA_CH10_RESERVED3

#define UDMA_CH10_RESERVED3   0x0003000A

§ UDMA_CH10_I2C2RX

#define UDMA_CH10_I2C2RX   0x0004000A

§ UDMA_CH10_RESERVED5

#define UDMA_CH10_RESERVED5   0x0005000A

§ UDMA_CH10_RESERVED6

#define UDMA_CH10_RESERVED6   0x0006000A

§ UDMA_CH10_TIMER6A

#define UDMA_CH10_TIMER6A   0x0007000A

§ UDMA_CH10_RESERVED8

#define UDMA_CH10_RESERVED8   0x0008000A

§ UDMA_CH11_SSI0TX

#define UDMA_CH11_SSI0TX   0x0000000B

§ UDMA_CH11_SSI1TX

#define UDMA_CH11_SSI1TX   0x0001000B

§ UDMA_CH11_UART6TX

#define UDMA_CH11_UART6TX   0x0002000B

§ UDMA_CH11_RESERVED3

#define UDMA_CH11_RESERVED3   0x0003000B

§ UDMA_CH11_I2C2TX

#define UDMA_CH11_I2C2TX   0x0004000B

§ UDMA_CH11_RESERVED5

#define UDMA_CH11_RESERVED5   0x0005000B

§ UDMA_CH11_RESERVED6

#define UDMA_CH11_RESERVED6   0x0006000B

§ UDMA_CH11_TIMER6B

#define UDMA_CH11_TIMER6B   0x0007000B

§ UDMA_CH11_RESERVED8

#define UDMA_CH11_RESERVED8   0x0008000B

§ UDMA_CH12_RESERVED0

#define UDMA_CH12_RESERVED0   0x0000000C

§ UDMA_CH12_UART2RX

#define UDMA_CH12_UART2RX   0x0001000C

§ UDMA_CH12_SSI2RX

#define UDMA_CH12_SSI2RX   0x0002000C

§ UDMA_CH12_RESERVED3

#define UDMA_CH12_RESERVED3   0x0003000C

§ UDMA_CH12_GPIOK

#define UDMA_CH12_GPIOK   0x0004000C

§ UDMA_CH12_AES0CIN

#define UDMA_CH12_AES0CIN   0x0005000C

§ UDMA_CH12_RESERVED6

#define UDMA_CH12_RESERVED6   0x0006000C

§ UDMA_CH12_TIMER7A

#define UDMA_CH12_TIMER7A   0x0007000C

§ UDMA_CH12_RESERVED8

#define UDMA_CH12_RESERVED8   0x0008000C

§ UDMA_CH13_RESERVED0

#define UDMA_CH13_RESERVED0   0x0000000D

§ UDMA_CH13_UART2TX

#define UDMA_CH13_UART2TX   0x0001000D

§ UDMA_CH13_SSI2TX

#define UDMA_CH13_SSI2TX   0x0002000D

§ UDMA_CH13_RESERVED3

#define UDMA_CH13_RESERVED3   0x0003000D

§ UDMA_CH13_GPIOL

#define UDMA_CH13_GPIOL   0x0004000D

§ UDMA_CH13_AES0COUT

#define UDMA_CH13_AES0COUT   0x0005000D

§ UDMA_CH13_RESERVED6

#define UDMA_CH13_RESERVED6   0x0006000D

§ UDMA_CH13_TIMER7B

#define UDMA_CH13_TIMER7B   0x0007000D

§ UDMA_CH13_RESERVED8

#define UDMA_CH13_RESERVED8   0x0008000D

§ UDMA_CH14_ADC0_0

#define UDMA_CH14_ADC0_0   0x0000000E

§ UDMA_CH14_TIMER2A

#define UDMA_CH14_TIMER2A   0x0001000E

§ UDMA_CH14_SSI3RX

#define UDMA_CH14_SSI3RX   0x0002000E

§ UDMA_CH14_GPIOE

#define UDMA_CH14_GPIOE   0x0003000E

§ UDMA_CH14_GPIOM

#define UDMA_CH14_GPIOM   0x0004000E

§ UDMA_CH14_AES0DIN

#define UDMA_CH14_AES0DIN   0x0005000E

§ UDMA_CH14_RESERVED6

#define UDMA_CH14_RESERVED6   0x0006000E

§ UDMA_CH14_RESERVED7

#define UDMA_CH14_RESERVED7   0x0007000E

§ UDMA_CH14_RESERVED8

#define UDMA_CH14_RESERVED8   0x0008000E

§ UDMA_CH15_ADC0_1

#define UDMA_CH15_ADC0_1   0x0000000F

§ UDMA_CH15_TIMER2B

#define UDMA_CH15_TIMER2B   0x0001000F

§ UDMA_CH15_SSI3TX

#define UDMA_CH15_SSI3TX   0x0002000F

§ UDMA_CH15_GPIOF

#define UDMA_CH15_GPIOF   0x0003000F

§ UDMA_CH15_GPION

#define UDMA_CH15_GPION   0x0004000F

§ UDMA_CH15_AES0DOUT

#define UDMA_CH15_AES0DOUT   0x0005000F

§ UDMA_CH15_RESERVED6

#define UDMA_CH15_RESERVED6   0x0006000F

§ UDMA_CH15_RESERVED7

#define UDMA_CH15_RESERVED7   0x0007000F

§ UDMA_CH15_RESERVED8

#define UDMA_CH15_RESERVED8   0x0008000F

§ UDMA_CH16_ADC0_2

#define UDMA_CH16_ADC0_2   0x00000010

§ UDMA_CH16_RESERVED1

#define UDMA_CH16_RESERVED1   0x00010010

§ UDMA_CH16_UART3RX

#define UDMA_CH16_UART3RX   0x00020010

§ UDMA_CH16_RESERVED3

#define UDMA_CH16_RESERVED3   0x00030010

§ UDMA_CH16_GPIOP

#define UDMA_CH16_GPIOP   0x00040010

§ UDMA_CH16_RESERVED5

#define UDMA_CH16_RESERVED5   0x00050010

§ UDMA_CH16_RESERVED6

#define UDMA_CH16_RESERVED6   0x00060010

§ UDMA_CH16_RESERVED7

#define UDMA_CH16_RESERVED7   0x00070010

§ UDMA_CH16_RESERVED8

#define UDMA_CH16_RESERVED8   0x00080010

§ UDMA_CH17_ADC0_3

#define UDMA_CH17_ADC0_3   0x00000011

§ UDMA_CH17_RESERVED1

#define UDMA_CH17_RESERVED1   0x00010011

§ UDMA_CH17_UART3TX

#define UDMA_CH17_UART3TX   0x00020011

§ UDMA_CH17_RESERVED3

#define UDMA_CH17_RESERVED3   0x00030011

§ UDMA_CH17_RESERVED4

#define UDMA_CH17_RESERVED4   0x00040011

§ UDMA_CH17_RESERVED5

#define UDMA_CH17_RESERVED5   0x00050011

§ UDMA_CH17_RESERVED6

#define UDMA_CH17_RESERVED6   0x00060011

§ UDMA_CH17_RESERVED7

#define UDMA_CH17_RESERVED7   0x00070011

§ UDMA_CH17_RESERVED8

#define UDMA_CH17_RESERVED8   0x00080011

§ UDMA_CH18_TIMER0A

#define UDMA_CH18_TIMER0A   0x00000012

§ UDMA_CH18_TIMER1A

#define UDMA_CH18_TIMER1A   0x00010012

§ UDMA_CH18_UART4RX

#define UDMA_CH18_UART4RX   0x00020012

§ UDMA_CH18_GPIOB

#define UDMA_CH18_GPIOB   0x00030012

§ UDMA_CH18_I2C3RX

#define UDMA_CH18_I2C3RX   0x00040012

§ UDMA_CH18_RESERVED5

#define UDMA_CH18_RESERVED5   0x00050012

§ UDMA_CH18_RESERVED6

#define UDMA_CH18_RESERVED6   0x00060012

§ UDMA_CH18_RESERVED7

#define UDMA_CH18_RESERVED7   0x00070012

§ UDMA_CH18_RESERVED8

#define UDMA_CH18_RESERVED8   0x00080012

§ UDMA_CH19_TIMER0B

#define UDMA_CH19_TIMER0B   0x00000013

§ UDMA_CH19_TIMER1B

#define UDMA_CH19_TIMER1B   0x00010013

§ UDMA_CH19_UART4TX

#define UDMA_CH19_UART4TX   0x00020013

§ UDMA_CH19_GPIOG

#define UDMA_CH19_GPIOG   0x00030013

§ UDMA_CH19_I2C3TX

#define UDMA_CH19_I2C3TX   0x00040013

§ UDMA_CH19_RESERVED5

#define UDMA_CH19_RESERVED5   0x00050013

§ UDMA_CH19_RESERVED6

#define UDMA_CH19_RESERVED6   0x00060013

§ UDMA_CH19_RESERVED7

#define UDMA_CH19_RESERVED7   0x00070013

§ UDMA_CH19_RESERVED8

#define UDMA_CH19_RESERVED8   0x00080013

§ UDMA_CH20_TIMER1A

#define UDMA_CH20_TIMER1A   0x00000014

§ UDMA_CH20_EPI0RX

#define UDMA_CH20_EPI0RX   0x00010014

§ UDMA_CH20_UART7RX

#define UDMA_CH20_UART7RX   0x00020014

§ UDMA_CH20_GPIOH

#define UDMA_CH20_GPIOH   0x00030014

§ UDMA_CH20_I2C4RX

#define UDMA_CH20_I2C4RX   0x00040014

§ UDMA_CH20_DES0CIN

#define UDMA_CH20_DES0CIN   0x00050014

§ UDMA_CH20_RESERVED6

#define UDMA_CH20_RESERVED6   0x00060014

§ UDMA_CH20_RESERVED7

#define UDMA_CH20_RESERVED7   0x00070014

Referenced by uDMAInit().

§ UDMA_CH20_RESERVED8

#define UDMA_CH20_RESERVED8   0x00080014

§ UDMA_CH21_TIMER1B

#define UDMA_CH21_TIMER1B   0x00000015

§ UDMA_CH21_EPI0TX

#define UDMA_CH21_EPI0TX   0x00010015

§ UDMA_CH21_UART7TX

#define UDMA_CH21_UART7TX   0x00020015

§ UDMA_CH21_GPIOJ

#define UDMA_CH21_GPIOJ   0x00030015

§ UDMA_CH21_I2C4TX

#define UDMA_CH21_I2C4TX   0x00040015

§ UDMA_CH21_DES0DIN

#define UDMA_CH21_DES0DIN   0x00050015

§ UDMA_CH21_RESERVED6

#define UDMA_CH21_RESERVED6   0x00060015

§ UDMA_CH21_RESERVED7

#define UDMA_CH21_RESERVED7   0x00070015

Referenced by uDMAInit().

§ UDMA_CH21_RESERVED8

#define UDMA_CH21_RESERVED8   0x00080015

§ UDMA_CH22_UART1RX

#define UDMA_CH22_UART1RX   0x00000016

§ UDMA_CH22_RESERVED1

#define UDMA_CH22_RESERVED1   0x00010016

§ UDMA_CH22_RESERVED2

#define UDMA_CH22_RESERVED2   0x00020016

§ UDMA_CH22_RESERVED3

#define UDMA_CH22_RESERVED3   0x00030016

§ UDMA_CH22_I2C5RX

#define UDMA_CH22_I2C5RX   0x00040016

§ UDMA_CH22_DES0DOUT

#define UDMA_CH22_DES0DOUT   0x00050016

§ UDMA_CH22_RESERVED6

#define UDMA_CH22_RESERVED6   0x00060016

§ UDMA_CH22_RESERVED7

#define UDMA_CH22_RESERVED7   0x00070016

Referenced by uDMAInit().

§ UDMA_CH22_I2C8RX

#define UDMA_CH22_I2C8RX   0x00080016

§ UDMA_CH23_UART1TX

#define UDMA_CH23_UART1TX   0x00000017

§ UDMA_CH23_RESERVED1

#define UDMA_CH23_RESERVED1   0x00010017

§ UDMA_CH23_RESERVED2

#define UDMA_CH23_RESERVED2   0x00020017

§ UDMA_CH23_RESERVED3

#define UDMA_CH23_RESERVED3   0x00030017

§ UDMA_CH23_I2C5TX

#define UDMA_CH23_I2C5TX   0x00040017

§ UDMA_CH23_RESERVED5

#define UDMA_CH23_RESERVED5   0x00050017

§ UDMA_CH23_RESERVED6

#define UDMA_CH23_RESERVED6   0x00060017

§ UDMA_CH23_RESERVED7

#define UDMA_CH23_RESERVED7   0x00070017

Referenced by uDMAInit().

§ UDMA_CH23_I2C8TX

#define UDMA_CH23_I2C8TX   0x00080017

§ UDMA_CH24_SSI1RX

#define UDMA_CH24_SSI1RX   0x00000018

§ UDMA_CH24_ADC1_0

#define UDMA_CH24_ADC1_0   0x00010018

§ UDMA_CH24_RESERVED2

#define UDMA_CH24_RESERVED2   0x00020018

§ UDMA_CH24_RESERVED3

#define UDMA_CH24_RESERVED3   0x00030018

§ UDMA_CH24_GPIOQ

#define UDMA_CH24_GPIOQ   0x00040018

§ UDMA_CH24_RESERVED5

#define UDMA_CH24_RESERVED5   0x00050018

§ UDMA_CH24_RESERVED6

#define UDMA_CH24_RESERVED6   0x00060018

§ UDMA_CH24_RESERVED7

#define UDMA_CH24_RESERVED7   0x00070018

Referenced by uDMAInit().

§ UDMA_CH24_I2C9RX

#define UDMA_CH24_I2C9RX   0x00080018

§ UDMA_CH25_SSI1TX

#define UDMA_CH25_SSI1TX   0x00000019

§ UDMA_CH25_ADC1_1

#define UDMA_CH25_ADC1_1   0x00010019

§ UDMA_CH25_RESERVED2

#define UDMA_CH25_RESERVED2   0x00020019

§ UDMA_CH25_RESERVED3

#define UDMA_CH25_RESERVED3   0x00030019

§ UDMA_CH25_GPIOR

#define UDMA_CH25_GPIOR   0x00040019

§ UDMA_CH25_RESERVED5

#define UDMA_CH25_RESERVED5   0x00050019

§ UDMA_CH25_RESERVED6

#define UDMA_CH25_RESERVED6   0x00060019

§ UDMA_CH25_RESERVED7

#define UDMA_CH25_RESERVED7   0x00070019

Referenced by uDMAInit().

§ UDMA_CH25_I2C9TX

#define UDMA_CH25_I2C9TX   0x00080019

§ UDMA_CH26_RESERVED0

#define UDMA_CH26_RESERVED0   0x0000001A

§ UDMA_CH26_ADC1_2

#define UDMA_CH26_ADC1_2   0x0001001A

§ UDMA_CH26_RESERVED2

#define UDMA_CH26_RESERVED2   0x0002001A

§ UDMA_CH26_RESERVED3

#define UDMA_CH26_RESERVED3   0x0003001A

§ UDMA_CH26_GPIOS

#define UDMA_CH26_GPIOS   0x0004001A

§ UDMA_CH26_RESERVED5

#define UDMA_CH26_RESERVED5   0x0005001A

§ UDMA_CH26_RESERVED6

#define UDMA_CH26_RESERVED6   0x0006001A

§ UDMA_CH26_RESERVED7

#define UDMA_CH26_RESERVED7   0x0007001A

§ UDMA_CH26_I2C6RX

#define UDMA_CH26_I2C6RX   0x0008001A

§ UDMA_CH27_RESERVED0

#define UDMA_CH27_RESERVED0   0x0000001B

§ UDMA_CH27_ADC1_3

#define UDMA_CH27_ADC1_3   0x0001001B

§ UDMA_CH27_RESERVED2

#define UDMA_CH27_RESERVED2   0x0002001B

§ UDMA_CH27_RESERVED3

#define UDMA_CH27_RESERVED3   0x0003001B

§ UDMA_CH27_RESERVED4

#define UDMA_CH27_RESERVED4   0x0004001B

§ UDMA_CH27_RESERVED5

#define UDMA_CH27_RESERVED5   0x0005001B

§ UDMA_CH27_GPIOT

#define UDMA_CH27_GPIOT   0x0006001B

§ UDMA_CH27_RESERVED7

#define UDMA_CH27_RESERVED7   0x0007001B

§ UDMA_CH27_I2C6TX

#define UDMA_CH27_I2C6TX   0x0008001B

§ UDMA_CH28_RESERVED0

#define UDMA_CH28_RESERVED0   0x0000001C

§ UDMA_CH28_RESERVED1

#define UDMA_CH28_RESERVED1   0x0001001C

§ UDMA_CH28_RESERVED2

#define UDMA_CH28_RESERVED2   0x0002001C

§ UDMA_CH28_RESERVED3

#define UDMA_CH28_RESERVED3   0x0003001C

§ UDMA_CH28_RESERVED4

#define UDMA_CH28_RESERVED4   0x0004001C

§ UDMA_CH28_RESERVED5

#define UDMA_CH28_RESERVED5   0x0005001C

§ UDMA_CH28_RESERVED6

#define UDMA_CH28_RESERVED6   0x0006001C

§ UDMA_CH28_RESERVED7

#define UDMA_CH28_RESERVED7   0x0007001C

§ UDMA_CH28_I2C7RX

#define UDMA_CH28_I2C7RX   0x0008001C

§ UDMA_CH29_RESERVED0

#define UDMA_CH29_RESERVED0   0x0000001D

§ UDMA_CH29_RESERVED1

#define UDMA_CH29_RESERVED1   0x0001001D

§ UDMA_CH29_RESERVED2

#define UDMA_CH29_RESERVED2   0x0002001D

§ UDMA_CH29_RESERVED3

#define UDMA_CH29_RESERVED3   0x0003001D

§ UDMA_CH29_RESERVED4

#define UDMA_CH29_RESERVED4   0x0004001D

§ UDMA_CH29_RESERVED5

#define UDMA_CH29_RESERVED5   0x0005001D

§ UDMA_CH29_RESERVED6

#define UDMA_CH29_RESERVED6   0x0006001D

§ UDMA_CH29_RESERVED7

#define UDMA_CH29_RESERVED7   0x0007001D

§ UDMA_CH29_I2C7TX

#define UDMA_CH29_I2C7TX   0x0008001D

§ UDMA_CH30_SW

#define UDMA_CH30_SW   0x0000001E

§ UDMA_CH30_RESERVED1

#define UDMA_CH30_RESERVED1   0x0001001E

§ UDMA_CH30_RESERVED2

#define UDMA_CH30_RESERVED2   0x0002001E

§ UDMA_CH30_RESERVED3

#define UDMA_CH30_RESERVED3   0x0003001E

§ UDMA_CH30_RESERVED4

#define UDMA_CH30_RESERVED4   0x0004001E

§ UDMA_CH30_RESERVED5

#define UDMA_CH30_RESERVED5   0x0005001E

§ UDMA_CH30_RESERVED6

#define UDMA_CH30_RESERVED6   0x0006001E

§ UDMA_CH30_EPI0RX

#define UDMA_CH30_EPI0RX   0x0007001E

§ UDMA_CH30_1WIRE0

#define UDMA_CH30_1WIRE0   0x0008001E

§ UDMA_CH31_RESERVED0

#define UDMA_CH31_RESERVED0   0x0000001F

§ UDMA_CH31_RESERVED1

#define UDMA_CH31_RESERVED1   0x0001001F

§ UDMA_CH31_RESERVED2

#define UDMA_CH31_RESERVED2   0x0002001F

§ UDMA_CH31_RESERVED3

#define UDMA_CH31_RESERVED3   0x0003001F

§ UDMA_CH31_RESERVED4

#define UDMA_CH31_RESERVED4   0x0004001F

§ UDMA_CH31_RESERVED5

#define UDMA_CH31_RESERVED5   0x0005001F

§ UDMA_CH31_RESERVED6

#define UDMA_CH31_RESERVED6   0x0006001F

§ UDMA_CH31_EPI0RX

#define UDMA_CH31_EPI0RX   0x0007001F

§ UDMA_CH31_RESERVED8

#define UDMA_CH31_RESERVED8   0x0008001F
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