130 #ifndef ti_drivers_spi_SPIMSP432E4DMA__include 131 #define ti_drivers_spi_SPIMSP432E4DMA__include 140 #include <ti/devices/msp432e4/inc/msp432.h> 142 #include <ti/devices/msp432e4/driverlib/pin_map.h> 145 #include <ti/drivers/dpl/HwiP.h> 146 #include <ti/drivers/dpl/SemaphoreP.h> 153 #define SPIMSP432E4_PA2_SSI0CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_SSI0CLK) 158 #define SPIMSP432E4_PA3_SSI0FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_SSI0FSS) 163 #define SPIMSP432E4_PA4_SSI0XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_SSI0XDAT0) 168 #define SPIMSP432E4_PA5_SSI0XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_SSI0XDAT1) 173 #define SPIMSP432E4_PB5_SSI1CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_SSI1CLK) 178 #define SPIMSP432E4_PB4_SSI0FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_SSI1FSS) 183 #define SPIMSP432E4_PE4_SSI1XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 4, GPIO_PE4_SSI1XDAT0) 188 #define SPIMSP432E4_PE5_SSI1XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 5, GPIO_PE5_SSI1XDAT1) 193 #define SPIMSP432E4_PD3_SSI2CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 3, GPIO_PD3_SSI2CLK) 198 #define SPIMSP432E4_PG7_SSI2CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 7, GPIO_PG7_SSI2CLK) 203 #define SPIMSP432E4_PD2_SSI2FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 2, GPIO_PD2_SSI2FSS) 208 #define SPIMSP432E4_PG6_SSI2FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 6, GPIO_PG6_SSI2FSS) 213 #define SPIMSP432E4_PD1_SSI2XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 1, GPIO_PD1_SSI2XDAT0) 218 #define SPIMSP432E4_PG5_SSI2XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_SSI2XDAT0) 223 #define SPIMSP432E4_PD0_SSI2XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 0, GPIO_PD0_SSI2XDAT1) 228 #define SPIMSP432E4_PG4_SSI2XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_SSI2XDAT1) 233 #define SPIMSP432E4_PQ0_SSI3CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 0, GPIO_PQ0_SSI3CLK) 238 #define SPIMSP432E4_PF3_SSI3CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 3, GPIO_PF3_SSI3CLK) 243 #define SPIMSP432E4_PQ1_SSI3FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 1, GPIO_PQ1_SSI3FSS) 248 #define SPIMSP432E4_PF2_SSI3FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 2, GPIO_PF2_SSI3FSS) 253 #define SPIMSP432E4_PQ2_SSI3XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 2, GPIO_PQ2_SSI3XDAT0) 258 #define SPIMSP432E4_PF1_SSI3XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 1, GPIO_PF1_SSI3XDAT0) 263 #define SPIMSP432E4_PQ3_SSI3XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 3, GPIO_PQ3_SSI3XDAT1) 268 #define SPIMSP432E4_PF0_SSI3XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 0, GPIO_PF0_SSI3XDAT1) SPIMSP432E4DMA Object.
Definition: SPIMSP432E4DMA.h:379
uint32_t intNum
Definition: SPIMSP432E4DMA.h:347
uint32_t txDmaChannel
Definition: SPIMSP432E4DMA.h:359
SPI_Transaction * transaction
Definition: SPIMSP432E4DMA.h:383
uint32_t transferTimeout
Definition: SPIMSP432E4DMA.h:390
UDMAMSP432E4 Global configuration.
Definition: UDMAMSP432E4.h:151
void(* SPI_CallbackFxn)(SPI_Handle handle, SPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in SPI_MODE_CALLBACK.
Definition: SPI.h:561
enum SPI_Mode_ SPI_Mode
Definitions for various SPI modes of operation.
uint32_t xdat1PinMask
Definition: SPIMSP432E4DMA.h:371
A SPI_Transaction data structure is used with SPI_transfer(). It indicates how many SPI_FrameFormat f...
Definition: SPI.h:543
uDMA driver implementation for MSP432E4.
uint16_t minDmaTransferSize
Definition: SPIMSP432E4DMA.h:362
SPIMSP432E4DMA Hardware attributes.
Definition: SPIMSP432E4DMA.h:343
bool cancelInProgress
Definition: SPIMSP432E4DMA.h:395
uint32_t baseAddr
Definition: SPIMSP432E4DMA.h:345
UDMAMSP432E4_Handle dmaHandle
Definition: SPIMSP432E4DMA.h:384
uint32_t dataSize
Definition: SPIMSP432E4DMA.h:389
uint16_t defaultTxBufValue
Definition: SPIMSP432E4DMA.h:354
SPI_Mode spiMode
Definition: SPIMSP432E4DMA.h:392
size_t currentXferAmt
Definition: SPIMSP432E4DMA.h:387
uint32_t intPriority
Definition: SPIMSP432E4DMA.h:349
uint32_t xdat0PinMask
Definition: SPIMSP432E4DMA.h:369
uint32_t bitRate
Definition: SPIMSP432E4DMA.h:388
enum SPI_TransferMode_ SPI_TransferMode
SPI transfer mode determines the whether the SPI controller operates synchronously or asynchronously...
The definition of a SPI function table that contains the required set of functions to control a speci...
Definition: SPI.h:675
struct SPIMSP432E4DMA_Object SPIMSP432E4DMA_Object
SPIMSP432E4DMA Object.
SemaphoreP_Handle transferComplete
Definition: SPIMSP432E4DMA.h:381
uint32_t rxDmaChannel
Definition: SPIMSP432E4DMA.h:357
HwiP_Handle hwiHandle
Definition: SPIMSP432E4DMA.h:380
uint16_t * scratchBufPtr
Definition: SPIMSP432E4DMA.h:352
uint32_t fssPinMask
Definition: SPIMSP432E4DMA.h:367
uint32_t clkPinMask
Definition: SPIMSP432E4DMA.h:365
SPI_CallbackFxn transferCallbackFxn
Definition: SPIMSP432E4DMA.h:382
const SPI_FxnTable SPIMSP432E4DMA_fxnTable
SPI_TransferMode transferMode
Definition: SPIMSP432E4DMA.h:393
size_t amtDataXferred
Definition: SPIMSP432E4DMA.h:386
bool isOpen
Definition: SPIMSP432E4DMA.h:396
struct SPIMSP432E4DMA_HWAttrs SPIMSP432E4DMA_HWAttrs
SPIMSP432E4DMA Hardware attributes.
uint8_t format
Definition: SPIMSP432E4DMA.h:397