Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).
295 uint32_t ccfg_ModeConfReg ;
298 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
302 HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
303 ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
310 ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
319 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
322 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
327 uint32_t ui32EfuseData ;
328 uint32_t orgResetCtl ;
331 ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM );
334 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M ) >>
335 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S ) ;
340 HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_SOCLDOCTL1) =
341 ((((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M) >>
342 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S) <<
343 ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S) |
345 (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M) >>
346 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S) <<
347 ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S));
353 HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_REFSYSCTL0) =
354 (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M) >>
355 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S) <<
356 ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S);
360 HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL2 << 1)) =
361 (ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M << 8) |
362 (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M) >>
363 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S) <<
364 ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S);
367 ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM );
369 orgResetCtl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
370 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) =
371 ( orgResetCtl & ~( AON_PMCTL_RESETCTL_CLK_LOSS_EN |
372 AON_PMCTL_RESETCTL_VDD_LOSS_EN |
373 AON_PMCTL_RESETCTL_VDDR_LOSS_EN |
374 AON_PMCTL_RESETCTL_VDDS_LOSS_EN ));
375 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC );
379 if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) != 0 ) ||
380 (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) == 0 ) )
382 if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
383 AON_PMCTL_PWRCTL_EXT_REG_MODE)
388 HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
389 (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
390 (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M) >>
391 FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S) <<
392 ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
399 HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
400 (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
401 (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M) >>
402 FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S) <<
403 ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
406 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
407 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
410 FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
411 FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ;
415 Step_VBG(((int32_t)( ui32EfuseData << ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S )))
416 >> ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W ));
419 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF );
420 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF );
421 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = orgResetCtl;
422 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC );
427 uint32_t ui32TrimValue ;
430 trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF );
431 ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >>
432 FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
436 if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) {
437 HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
439 HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
443 uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S );
444 HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) =
453 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
456 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
463 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
static void Step_VBG(int32_t targetSigned)
Definition: setup.c:255
#define ADI_4_AUX_O_LPMBIAS
Definition: setup.c:47
void SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg)
Third part of configuration required when waking up from shutdown.
Definition: setup_rom.c:324
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S
Definition: setup.c:51
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M
Definition: setup.c:50
#define AUX_SYSIF_OPMODE_TARGET_PDA
Definition: aux_sysif.h:99
void SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg)
First part of configuration required when waking up from shutdown.
Definition: setup_rom.c:167
void AUXSYSIFOpModeChange(uint32_t targetOpMode)
Changes the AUX operational mode to the requested target mode.
Definition: aux_sysif.c:67
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S
Definition: setup.c:49
static void Step_RCOSCHF_CTRIM(uint32_t toCode)
Definition: setup.c:233
void SetupStepVddrTrimTo(uint32_t toCode)
Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max) ...
Definition: setup_rom.c:119
void SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)
Second part of configuration required when waking up from shutdown.
Definition: setup_rom.c:222
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M
Definition: setup.c:48