CC13xx Driver Library
RF Core

Data Structures

struct  rfTrim_t
 

Functions

static void RFCClockEnable (void)
 Enable the RF core clocks. More...
 
static void RFCClockDisable (void)
 Disable the RF core clocks. More...
 
static void RFCCpeIntClear (uint32_t ui32Mask)
 Clear HW interrupt flags. More...
 
static void RFCHwIntClear (uint32_t ui32Mask)
 Clear CPE interrupt flags. More...
 
static void RFCCpe0IntSelect (uint32_t ui32Mask)
 Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). More...
 
static void RFCCpe1IntSelect (uint32_t ui32Mask)
 Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). More...
 
static void RFCCpeIntEnable (uint32_t ui32Mask)
 Enable CPEx interrupt sources. More...
 
static void RFCCpe0IntSelectClearEnable (uint32_t ui32Mask)
 Select, clear, and enable interrupt sources to CPE0. More...
 
static void RFCCpe1IntSelectClearEnable (uint32_t ui32Mask)
 Select, clear, and enable interrupt sources to CPE1. More...
 
static void RFCHwIntEnable (uint32_t ui32Mask)
 Enable HW interrupt sources. More...
 
static void RFCCpeIntDisable (uint32_t ui32Mask)
 Disable CPE interrupt sources. More...
 
static void RFCHwIntDisable (uint32_t ui32Mask)
 Disable HW interrupt sources. More...
 
uint32_t RFCCpeIntGetAndClear (uint32_t ui32Mask)
 Get and clear CPE interrupt flags. More...
 
static void RFCAckIntClear (void)
 Clear ACK interrupt flag. More...
 
uint32_t RFCDoorbellSendTo (uint32_t pOp)
 Send a radio operation to the doorbell and wait for an acknowledgment. More...
 
void RFCSynthPowerDown (void)
 This function implements a fast way to turn off the synthesizer. More...
 
void RFCCpePatchReset (void)
 Reset previously patched CPE RAM to a state where it can be patched again. More...
 
uint8_t RFCOverrideSearch (const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth)
 
uint8_t RFCOverrideUpdate (rfc_radioOp_t *pOpSetup, uint32_t *pParams)
 Function to update override list. More...
 
uint32_t RFCHwIntGetAndClear (uint32_t ui32Mask)
 Get and clear HW interrupt flags. More...
 
void RFCRfTrimRead (rfc_radioOp_t *pOpSetup, rfTrim_t *rfTrim)
 Get the type of currently selected PA. More...
 
void RFCRfTrimSet (rfTrim_t *rfTrim)
 Write preloaded RF trim values directly into CPE. More...
 
uint8_t RFCRTrim (rfc_radioOp_t *pOpSetup)
 Check Override RTrim vs FCFG RTrim. More...
 
void RFCAdi3VcoLdoVoltageMode (bool bEnable)
 Function to set VCOLDO reference to voltage mode. More...
 

Detailed Description

Function Documentation

static void RFCAckIntClear ( void  )
inlinestatic

Clear ACK interrupt flag.

Referenced by RFCDoorbellSendTo().

321 {
322  // Clear any pending interrupts.
323  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0;
324 }
void RFCAdi3VcoLdoVoltageMode ( bool  bEnable)

Function to set VCOLDO reference to voltage mode.

483 {
484  if (bEnable)
485  {
486  // First make sure the REFSYSCTL0 mux output is not further muxed out
487  HWREGB(0x40086200) = 0x0;
488 
489  // Set the REFSYSCTL0 mux as desired for VCOLDO voltage mode
491  }
492  else
493  {
494  // Revert the mux override
496  }
497 }
static void RFCClockDisable ( void  )
inlinestatic

Disable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

When disabling clocks it is the programmers responsibility that the RF core clocks are safely gated. I.e. the RF core should be safely 'parked'.

Returns
None
155 {
156  // Disable all clocks
157  HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0;
158 }
static void RFCClockEnable ( void  )
inlinestatic

Enable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

Returns
None
130 {
131  // Enable basic clocks to get the CPE run
132  HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM
135 }
static void RFCCpe0IntSelect ( uint32_t  ui32Mask)
inlinestatic

Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector).

Referenced by RFCCpe0IntSelectClearEnable().

197 {
198  // Multiplex RF Core interrupts to CPE0 IRQ.
199  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask;
200 }
static void RFCCpe0IntSelectClearEnable ( uint32_t  ui32Mask)
inlinestatic

Select, clear, and enable interrupt sources to CPE0.

236 {
237  // Multiplex RF Core interrupts to CPE0 IRQ.
238  RFCCpe0IntSelect(ui32Mask);
239 
240  // Clear the masked interrupts.
241  RFCCpeIntClear(ui32Mask);
242 
243  // Enable the masked interrupts.
244  RFCCpeIntEnable(ui32Mask);
245 }
static void RFCCpeIntClear(uint32_t ui32Mask)
Clear HW interrupt flags.
Definition: rfc.h:167
static void RFCCpeIntEnable(uint32_t ui32Mask)
Enable CPEx interrupt sources.
Definition: rfc.h:222
static void RFCCpe0IntSelect(uint32_t ui32Mask)
Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector).
Definition: rfc.h:196

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static void RFCCpe1IntSelect ( uint32_t  ui32Mask)
inlinestatic

Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector).

Referenced by RFCCpe1IntSelectClearEnable().

210 {
211  // Multiplex RF Core interrupts to CPE1 IRQ.
212  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask;
213 }
static void RFCCpe1IntSelectClearEnable ( uint32_t  ui32Mask)
inlinestatic

Select, clear, and enable interrupt sources to CPE1.

255 {
256  // Multiplex RF Core interrupts to CPE1 IRQ.
257  RFCCpe1IntSelect(ui32Mask);
258 
259  // Clear the masked interrupts.
260  RFCCpeIntClear(ui32Mask);
261 
262  // Enable the masked interrupts.
263  RFCCpeIntEnable(ui32Mask);
264 }
static void RFCCpe1IntSelect(uint32_t ui32Mask)
Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector).
Definition: rfc.h:209
static void RFCCpeIntClear(uint32_t ui32Mask)
Clear HW interrupt flags.
Definition: rfc.h:167
static void RFCCpeIntEnable(uint32_t ui32Mask)
Enable CPEx interrupt sources.
Definition: rfc.h:222

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static void RFCCpeIntClear ( uint32_t  ui32Mask)
inlinestatic

Clear HW interrupt flags.

Referenced by RFCCpe0IntSelectClearEnable(), RFCCpe1IntSelectClearEnable(), and RFCCpeIntGetAndClear().

168 {
169  // Clear the masked pending interrupts.
170  do
171  {
172  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask;
173  }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask);
174 }
static void RFCCpeIntDisable ( uint32_t  ui32Mask)
inlinestatic

Disable CPE interrupt sources.

287 {
288  // Disable the masked interrupts
289  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask;
290 }
static void RFCCpeIntEnable ( uint32_t  ui32Mask)
inlinestatic

Enable CPEx interrupt sources.

Referenced by RFCCpe0IntSelectClearEnable(), and RFCCpe1IntSelectClearEnable().

223 {
224  // Enable CPE interrupts from RF Core.
225  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask;
226 }
uint32_t RFCCpeIntGetAndClear ( uint32_t  ui32Mask)

Get and clear CPE interrupt flags.

108 {
109  // Read the CPE interrupt flags which match the provided bitmask
110  uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask;
111 
112  // Clear the interrupt flags
113  RFCCpeIntClear(ui32Ifg);
114 
115  // Return with the interrupt flags
116  return (ui32Ifg);
117 }
static void RFCCpeIntClear(uint32_t ui32Mask)
Clear HW interrupt flags.
Definition: rfc.h:167

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void RFCCpePatchReset ( void  )

Reset previously patched CPE RAM to a state where it can be patched again.

180 {
181  uint8_t *pPatchTab = (uint8_t *) (_CPERAM_START + _PARSER_PATCH_TAB_OFFSET);
182  uint32_t *pIrqPatch = (uint32_t *)(_CPERAM_START + _IRQPATCH_OFFSET);
183 
184  memset(pPatchTab, 0xFF, _IRQPATCH_OFFSET - _PARSER_PATCH_TAB_OFFSET);
185 
186  int i;
187  for (i = 0; i < sizeof(rfc_defaultIrqAddr)/sizeof(rfc_defaultIrqAddr[0]); i++)
188  {
189  pIrqPatch[i * 2 + 1] = rfc_defaultIrqAddr[i];
190  }
191 }
static const uint16_t rfc_defaultIrqAddr[]
Definition: rfc.c:85
#define _IRQPATCH_OFFSET
Definition: rfc.c:78
#define _CPERAM_START
Definition: rfc.c:75
#define _PARSER_PATCH_TAB_OFFSET
Definition: rfc.c:76
uint32_t RFCDoorbellSendTo ( uint32_t  pOp)

Send a radio operation to the doorbell and wait for an acknowledgment.

127 {
128  // Wait until the doorbell becomes available
129  while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0);
130  RFCAckIntClear();
131 
132  // Submit the command to the CM0 through the doorbell
133  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp;
134 
135  // Wait until the CM0 starts to parse the command
136  while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG));
137  RFCAckIntClear();
138 
139  // Return with the content of status register
140  return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA));
141 }
static void RFCAckIntClear(void)
Clear ACK interrupt flag.
Definition: rfc.h:320

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static void RFCHwIntClear ( uint32_t  ui32Mask)
inlinestatic

Clear CPE interrupt flags.

Referenced by RFCHwIntGetAndClear().

184 {
185  // Clear the masked pending interrupts.
186  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask;
187 }
static void RFCHwIntDisable ( uint32_t  ui32Mask)
inlinestatic

Disable HW interrupt sources.

300 {
301  // Disable the masked interrupts
302  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask;
303 }
static void RFCHwIntEnable ( uint32_t  ui32Mask)
inlinestatic

Enable HW interrupt sources.

274 {
275  // Enable the masked interrupts
276  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask;
277 }
uint32_t RFCHwIntGetAndClear ( uint32_t  ui32Mask)

Get and clear HW interrupt flags.

239 {
240  // Read the CPE interrupt flags which match the provided bitmask
241  uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask;
242 
243  // Clear the interupt flags
244  RFCHwIntClear(ui32Ifg);
245 
246  // Return with the interrupt flags
247  return (ui32Ifg);
248 }
static void RFCHwIntClear(uint32_t ui32Mask)
Clear CPE interrupt flags.
Definition: rfc.h:183

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uint8_t RFCOverrideSearch ( const uint32_t *  pOverride,
const uint32_t  pattern,
const uint32_t  mask,
const uint8_t  searchDepth 
)

Referenced by RFCRTrim().

201 {
202  // Search from start of the override list, to look for first override entry that matches search pattern
203  uint8_t override_index;
204  for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++)
205  {
206  // Compare the value to the given pattern
207  if((pOverride[override_index] & mask) == pattern)
208  {
209  // Return with the index of override in case of match
210  return override_index;
211  }
212  }
213 
214  // Return with an invalid index
215  return 0xFF;
216 }
#define END_OVERRIDE
End of string for override register.
Definition: rf_mailbox.h:327
uint8_t RFCOverrideUpdate ( rfc_radioOp_t pOpSetup,
uint32_t *  pParams 
)

Function to update override list.

225 {
226  /* Handle RTrim values. */
227  return RFCRTrim(pOpSetup);
228 
229 }
uint8_t RFCRTrim(rfc_radioOp_t *pOpSetup)
Check Override RTrim vs FCFG RTrim.
Definition: rfc.c:352

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void RFCRfTrimRead ( rfc_radioOp_t pOpSetup,
rfTrim_t rfTrim 
)

Get the type of currently selected PA.

Read RF trim from flash using CM3.

257 {
258  // Definition of position and bitmask of divider value
259  const uint32_t CONFIG_MISC_ADC_DIVIDER = 27;
260  const uint32_t CONFIG_MISC_ADC_DIVIDER_BM = 0xF8000000U;
261 
262  // Local variable
263  int32_t divider;
264 
265  // Based on the type of setup command, decode the divider value
266  switch (pOpSetup->commandNo)
267  {
268  case CMD_RADIO_SETUP: // Use the loDivider value
269  divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
270  break;
271  case CMD_PROP_RADIO_DIV_SETUP: // Use the loDivider value
272  divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
273  break;
274  default: // Use 2.4 GHz by default
275  divider = 0;
276  break;
277  }
278 
279  // Read trim values from FCFG1
280  pRfTrim->configIfAdc = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_IF_ADC);
281  switch (divider)
282  {
283  case 5:
284  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV5);
285  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV5);
286  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV5)
287  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (5U << CONFIG_MISC_ADC_DIVIDER);
288  break;
289 
290  case 6:
291  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV6);
292  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV6);
293  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
294  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (6U << CONFIG_MISC_ADC_DIVIDER);
295  break;
296 
297  case 10:
298  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV10);
299  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV10);
300  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
301  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (10U << CONFIG_MISC_ADC_DIVIDER);
302  break;
303 
304  case 12:
305  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV12);
306  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV12);
307  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
308  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (12U << CONFIG_MISC_ADC_DIVIDER);
309  break;
310 
311  case 15:
312  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV15);
313  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV15);
314  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
315  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (15U << CONFIG_MISC_ADC_DIVIDER);
316  break;
317 
318  case 30:
319  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV30);
320  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV30);
321  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
322  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (30U << CONFIG_MISC_ADC_DIVIDER);
323  break;
324 
325  default:
326  pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND);
327  pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH);
328  // Make sure configMiscAdc is not 0 by setting an unused bit to 1
329  pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
330  & ~CONFIG_MISC_ADC_DIVIDER_BM) | (2U << CONFIG_MISC_ADC_DIVIDER);
331  break;
332  }
333 }
struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t
Definition: rf_prop_cmd.h:73
struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t
Definition: rf_common_cmd.h:68
#define CMD_PROP_RADIO_DIV_SETUP
Definition: rf_prop_cmd.h:552
#define CMD_RADIO_SETUP
Definition: rf_common_cmd.h:169
void RFCRfTrimSet ( rfTrim_t rfTrim)

Write preloaded RF trim values directly into CPE.

342 {
343  memcpy((void*)&HWREG(0x21000018), (void*)pRfTrim, sizeof(rfTrim_t));
344 }
Definition: rfc.h:74
uint8_t RFCRTrim ( rfc_radioOp_t pOpSetup)

Check Override RTrim vs FCFG RTrim.

Referenced by RFCOverrideUpdate().

353 {
354  int32_t divider;
355  uint32_t fcfg1_rtrim;
356  uint32_t *pOverride;
357  int32_t override_index;
358  uint32_t override_value;
359  uint32_t override_rtrim = 0;
360 
361  // Based on the type of setup command, decode the divider and overrides
362  switch (pOpSetup->commandNo)
363  {
364  case CMD_RADIO_SETUP:
365  divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
366  pOverride = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
367  break;
369  divider = 2;
370  pOverride = ((rfc_CMD_PROP_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
371  break;
373  divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
374  pOverride = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->pRegOverride;
375  break;
376  default:
377  return 1;
378  }
379 
380  if (pOverride == 0)
381  {
382  // There is no override list provided
383  return 1;
384  }
385 
386  // Search for an RTRIM value within the override list.
388 
389  // If we found it, decode the value.
390  if(override_index < RFC_MAX_SEARCH_DEPTH)
391  {
392  override_value = pOverride[override_index];
393  override_rtrim = (override_value & 0xF0000) >> 16;
394  }
395  else
396  {
397  // There is no RTRIM value within the first items of the override list
398  return 1;
399  }
400 
401  // Read trim from FCFG1
402  switch (divider)
403  {
404  case 2:
405  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
407  break;
408  case 5:
409  // Legacy value
410  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_MISC_OTP_DATA)
412  break;
413  case 6:
414  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
416  break;
417  case 10:
418  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
420  break;
421  case 12:
422  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
424  break;
425  case 15:
426  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
428  break;
429  case 30:
430  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
432  break;
433  default:
434  fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
436  break;
437  }
438 
439  // Check for value matching early device samples
440  if(fcfg1_rtrim == 0xF)
441  {
442  // Set to default value
443  switch (divider)
444  {
445  case 5:
446  case 10:
447  case 15:
448  case 30:
449  pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x7 << 16);
450  break;
451  case 2:
452  case 6:
453  case 12:
454  default:
455  pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x4 << 16);
456  break;
457  }
458  }
459  else
460  {
461  // Test Override vs FCFG1 limit.
462  if(override_rtrim >= fcfg1_rtrim)
463  {
464  ; // Do nothing
465  }
466  else
467  {
468  // Set override to FCFG1 limit value
469  pOverride[override_index] = (override_value & 0xFFF0FFFF) | (fcfg1_rtrim << 16);
470  }
471  }
472 
473  return 0;
474 }
#define RFC_RTRIM_MASK
Definition: rfc.c:82
#define CMD_PROP_RADIO_SETUP
Definition: rf_prop_cmd.h:453
struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t
Definition: rf_prop_cmd.h:73
struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t
Definition: rf_common_cmd.h:68
#define CMD_PROP_RADIO_DIV_SETUP
Definition: rf_prop_cmd.h:552
#define RFC_RTRIM_PATTERN
Definition: rfc.c:81
uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth)
Definition: rfc.c:200
struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t
Definition: rf_prop_cmd.h:72
#define CMD_RADIO_SETUP
Definition: rf_common_cmd.h:169
#define RFC_MAX_SEARCH_DEPTH
Definition: rfc.h:82

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void RFCSynthPowerDown ( void  )

This function implements a fast way to turn off the synthesizer.

151 {
152  // Definition of reserved words
153  const uint32_t RFC_RESERVED0 = 0x40044108;
154  const uint32_t RFC_RESERVED1 = 0x40044114;
155  const uint32_t RFC_RESERVED2 = 0x4004410C;
156  const uint32_t RFC_RESERVED3 = 0x40044100;
157 
158  // Disable CPE clock, enable FSCA clock.
159  HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN)
161 
162  HWREG(RFC_RESERVED0) = 3;
163  HWREG(RFC_RESERVED1) = 0x1030;
164  HWREG(RFC_RESERVED2) = 1;
165  HWREG(RFC_RESERVED1) = 0x50;
166  HWREG(RFC_RESERVED2) = 1;
167  HWREG(RFC_RESERVED1) = 0x650;
168  HWREG(RFC_RESERVED2) = 1;
169  HWREG(RFC_RESERVED3) = 1;
170 
171 }

Macro Definition Documentation

#define RFC_MAX_SEARCH_DEPTH   5

Referenced by RFCRTrim().