PDMCC26XX_I2S Audio Clock configuration. More...

Data Fields
uint16_t	bclkDiv:10

uint16_t	bclkSource:1

uint16_t	mclkDiv:10

uint16_t	reserved:5

uint16_t	sampleOnPositiveEdge:1

uint16_t	wclkDiv

uint16_t	wclkInverted:1

uint16_t	wclkPhase:2

uint16_t	wclkSource:2

Detailed Description

PDMCC26XX_I2S Audio Clock configuration.

These fields are used by the driver to set up the I2S module

A sample structure is shown below (single PDM microphone):

const PDMCC26XX_I2S_AudioClockConfig PDMCC26XX_I2Sobjects[] = {
        16, // Word clock division
        PDMCC26XX_I2S_SampleEdge_Negative,
        PDMCC26XX_I2S_WordClockPhase_Dual,
        PDMCC26XX_I2S_ClockSource_Inverted,
        PDMCC26XX_I2S_WordClockSource_Int,
        47, // Bit clock division
        0, // Reserved
        PDMCC26XX_I2S_BitClockSource_Int
        6, // Master clock division
};

Field Documentation

§ bclkDiv

uint16_t bclkDiv

I2S Bit Clock divider override

§ bclkSource

uint16_t bclkSource

I2S Bit Clock source (PDMCC26XX_I2S_BitClockSource_Ext or PDMCC26XX_I2S_BitClockSource_Int)

§ mclkDiv

uint16_t mclkDiv

I2S Master Clock divider override

§ reserved

uint16_t reserved

Reserved bit field

§ sampleOnPositiveEdge

uint16_t sampleOnPositiveEdge

I2S Sample Edge. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge

§ wclkDiv

uint16_t wclkDiv

I2S Word Clock divider override

§ wclkInverted

uint16_t wclkInverted

I2S Invert Word Clock (PDMCC26XX_I2S_ClockSource_Inverted or PDMCC26XX_I2S_ClockSource_Normal)

§ wclkPhase

uint16_t wclkPhase

I2S Word Clock Phase(PDMCC26XX_I2S_WordClockPhase_Dual, PDMCC26XX_I2S_WordClockPhase_Single or PDMCC26XX_I2S_WordClockPhase_UserDefined)

§ wclkSource

uint16_t wclkSource

I2S Word Clock source (PDMCC26XX_I2S_WordClockSource_Ext or PDMCC26XX_I2S_WordClockSource_Int)

The documentation for this struct was generated from the following file:

PDMCC26XX_util.h

Data Fields