Introduction

This files defines SPI MCAL configuration structures

Data Structures
struct	Spi_ChannelConfigType
	SPI Channel configuration structure. More...

struct	Spi_McspiExternalDeviceConfigType
	SPI Job configuration structure specific to McSPI peripheral. More...

struct	Spi_ExternalDeviceConfigType
	SPI external device specific configuration structure . More...

struct	Spi_JobConfigType
	SPI Job configuration structure. More...

struct	Spi_SeqConfigType
	SPI Sequence configuration structure. More...

struct	Spi_HwUnitConfigType
	SPI Hardware unit configuration structure. More...

struct	Spi_ConfigType
	SPI config structure. More...

struct	Spi_ChannelConfigType_PC
	SPI channel config structure parameters Pre-Compile only. More...

struct	Spi_JobConfigType_PC
	SPI job config structure parameters Pre-Compile only. More...

struct	Spi_SeqConfigType_PC
	SPI sequence config structure parameters Pre-Compile only. More...

struct	Spi_RegisterReadbackType
	SPI register readback structure. More...

Variables
const uint32	Spi_HwUnitBaseAddr [SPI_HW_UNIT_CNT]

Typedefs
typedef void(*	Spi_CacheWbInv) (uint8 *BufPtr, uint16 LenByte)
	Cache write-back invalidate function. More...

typedef void(*	Spi_CacheWb) (uint8 *BufPtr, uint16 LenByte)
	Cache write-back function. More...

typedef void(*	Spi_CacheInv) (uint8 *BufPtr, uint16 LenByte)
	Cache invalidate function. More...

Enumerations
enum	Spi_StatusType { SPI_UNINIT = 0U, SPI_IDLE = 1U, SPI_BUSY = 2U }
	This type defines a range of specific status for SPI Handler/Driver. More...

enum	Spi_JobResultType { SPI_JOB_OK = 0U, SPI_JOB_PENDING = 1U, SPI_JOB_FAILED = 2U, SPI_JOB_QUEUED = 3U }
	This type defines a range of specific Jobs status for SPI Handler/Driver. More...

enum	Spi_SeqResultType { SPI_SEQ_OK = 0U, SPI_SEQ_PENDING = 1U, SPI_SEQ_FAILED = 2U, SPI_SEQ_CANCELLED = 3U }
	This type defines a range of specific Sequences status for SPI Handler/Driver. More...

enum	Spi_HwUnitResultType { SPI_HW_UNIT_OK = 0U, SPI_HW_UNIT_PENDING = 1U, SPI_HW_UNIT_FAILED = 2U }
	This type defines a range of specific HW unit status for SPI Handler/Driver. More...

enum	Spi_AsyncModeType { SPI_POLLING_MODE = 0U, SPI_INTERRUPT_MODE = 1U }
	Specifies the asynchronous mechanism mode for SPI busses handled asynchronously in LEVEL 2. More...

enum	Spi_TransferType { SPI_MSB = 0U, SPI_LSB = 1U }
	Word transfer order - MSB first or LSB first. More...

enum	Spi_LevelType { SPI_LOW = STD_LOW, SPI_HIGH }
	Type for SPI Chip Select Polarity and Clock Idle Level. More...

enum	Spi_CsPinType { SPI_CS0 = 0U, SPI_CS1, SPI_CS2, SPI_CS3 }
	SPI Chip Select Pin. More...

enum	Spi_ClkMode { SPI_CLK_MODE_0 = 0x00U, SPI_CLK_MODE_1 = 0x01U, SPI_CLK_MODE_2 = 0x02U, SPI_CLK_MODE_3 = 0x03U }
	SPI Clock Mode - sets the clock polarity and phase. Note: These values are a direct register mapping. So don't change value. More...

enum	Spi_TxRxMode { SPI_TX_RX_MODE_BOTH = 0x00U, SPI_TX_RX_MODE_TX_ONLY = 0x02U }
	SPI TX/RX Mode. More...

enum	Spi_JobPriorityType { SPI_JOB_PRIORITY_0 = 0U, SPI_JOB_PRIORITY_1, SPI_JOB_PRIORITY_2, SPI_JOB_PRIORITY_3 }
	SPI Job Priority. More...

enum	Spi_CsModeType { SPI_SINGLE = 0U, SPI_CONTINUOUS = 1U }
	SPI Chip Select Mode. More...

enum	Spi_DataDelayType { SPI_DATADELAY_0 = 0U, SPI_DATADELAY_1 = 1U, SPI_DATADELAY_2 = 2U, SPI_DATADELAY_3 = 3U }
	Spi_DataDelayType defines the number of interface clock cycles between CS toggling and first or last edge of MCSPI clock. More...

enum	Spi_DataLineReceiveType { DATA_LINE_0_RECEPTION = 0U, DATA_LINE_1_RECEPTION = 1U }
	Spi_DataLineReceiveType defines the lines selected for reception. More...

enum	Spi_DataLineTransmitType { DATA_LINE_NO_TRANSMISSION = 0x3U, DATA_LINE_0_TRANSMISSION = 0x2U, DATA_LINE_1_TRANSMISSION = 0x1U, DATA_LINE_BOTH_TRANSMISSION = 0x0U }
	Spi_DataLineTransmitType defines the lines selected for transmission. More...

enum	Mcspi_IrqStatusType { SPI_NO_EVENT = 0U, SPI_EVENT_PENDING = 1U, SPI_STATUS_READ_FAIL = 2U }
	Irq status and std return type. More...

Macros
#define	SPI_VARIANT_POST_BUILD (STD_ON)
	SPI Build Variant. Build variants.(i.e Pre Compile,Post Build or Link time) More...

#define	SPI_CHANNELBUFFERS (SPI_IB_EB)
	Pre Compile config macro name. More...

#define	SPI_IB_MAX_LENGTH (64U)
	Internal Buffer length in bytes - applicable only for SPI_IB. More...

#define	SPI_DEV_ERROR_DETECT (STD_ON)
	Enable/disable SPI dev detect error. More...

#define	SPI_JOB_LOG (STD_ON)
	Enable/disable SPI job log. More...

#define	SPI_MAX_JOB_LOG (100U)
	Maximum job log entries when logging is ON. More...

#define	SPI_MAX_HW_DMA_UNIT (0U)
	Enable/disable SPI DMA Support. More...

#define	SPI_DMA_ENABLE (STD_OFF)
	Enable/disable SPI DMA Support. More...

#define	SPI_LEVEL_0 (0U)
	Basic Synchronous functions. More...

#define	SPI_LEVEL_1 (1U)
	Basic Asynchronous functions. More...

#define	SPI_LEVEL_2 (2U)
	Synchronous and Asynchronous functions. More...

#define	SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)
	Concurrent sync transmit support - by defualt this is off. More...

#define	SPI_SCALEABILITY (SPI_LEVEL_2)
	Scalability level. More...

#define	SPI_VERSION_INFO_API (STD_ON)
	Enable/disable SPI get version info API. More...

#define	SPI_HW_STATUS_API (STD_ON)
	Enable/disable SPI HW Status API. More...

#define	SPI_CANCEL_API (STD_ON)
	Enable/disable SPI cancel API. More...

#define	SPI_MAX_CHANNELS_PER_JOB (1U)
	Maximum channels allowed per job. More...

#define	SPI_MAX_JOBS_PER_SEQ (1U)
	Maximum jobs allowed per sequence. More...

#define	SPI_MAX_CHANNELS (1U)
	Maximum channels across all jobs/sequence/hwunit. More...

#define	SPI_MAX_JOBS (1U)
	Maximum jobs across all sequence/hwunit. More...

#define	SPI_MAX_SEQ (1U)
	Maximum sequence across all hwunit. More...

#define	SPI_MAX_HW_UNIT (8U)
	Maximum HW unit - This should match the sum for the below units ISR which are ON. More...

#define	SPI_MAX_EXT_DEV (11U)
	Maximum external device cfg. More...

#define	SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)
	Enable/disable SPI MCU MCSPI0 unit ISR. More...

#define	SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)
	Enable/disable SPI MCU MCSPI1 unit ISR. More...

#define	SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)
	Enable/disable SPI MCU MCSPI2 unit ISR. More...

#define	SPI_UNIT_MCSPI0_ACTIVE (STD_ON)
	Enable/disable SPI MCSPI0 unit ISR. More...

#define	SPI_UNIT_MCSPI1_ACTIVE (STD_ON)
	Enable/disable SPI MCSPI1 unit ISR. More...

#define	SPI_UNIT_MCSPI2_ACTIVE (STD_ON)
	Enable/disable SPI MCSPI2 unit ISR. More...

#define	SPI_UNIT_MCSPI3_ACTIVE (STD_ON)
	Enable/disable SPI MCSPI3 unit ISR. More...

#define	SPI_UNIT_MCSPI4_ACTIVE (STD_ON)
	Enable/disable SPI MCSPI4 unit ISR. More...

#define	SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)
	Enable/disable SPI MCSPI5 unit ISR. More...

#define	SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)
	Enable/disable SPI MCSPI6 unit ISR. More...

#define	SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)
	Enable/disable SPI MCSPI7 unit ISR. More...

#define	SPI_ISR_TYPE (SPI_ISR_CAT1)
	ISR type. More...

#define	SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)
	OS counter ID - used for timeout in case of error. More...

#define	SPI_TIMEOUT_DURATION (32000U)
	SPI timeout - used in McSPI IP reset Each tick is 31.25us (for 32K Counter). Wait for 100ms which comes to below value. More...

#define	SPI_REGISTER_READBACK_API (STD_ON)
	Enable/disable SPI register read back API. More...

#define	SPI_SAFETY_API (STD_ON)
	Enable/disable SPI safety API. More...

#define	SpiConf_SpiChannel_SpiChannel_0 (0U)
	Symbolic Name Channel Id - 0 SpiChannel_0. More...

#define	SpiConf_SpiExternalDevice_CS0 (SPI_CS0)
	Symbolic Name Chip Select - 0. More...

#define	SpiConf_SpiJob_SpiJob_0 (0U)
	Symbolic Name Job Id - 0 SpiJob_0. More...

#define	SpiConf_SpiSequence_SpiSequence_0 (0U)
	Symbolic Name Sequence Id - 0 SpiSequence_0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)
	Symbolic Name HW Unit - 0. More...

#define	SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)
	Symbolic Name HW Unit - 0. More...

#define	SPI_HW_UNIT_CNT (11U)
	Total HW units - used for array allocation. This should be +1 of the max unit number. More...

SPI DEM Error codes to report
Pre-compile switches for enabling/disabling DEM events
#define	DemConf_DemEventParameter_SPI_DEM_NO_EVENT (0xFFFFU)

#define	SPI_DEM_NO_EVENT DemConf_DemEventParameter_SPI_DEM_NO_EVENT

#define	SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
	Hardware failed. More...

SPI HW unit Info
#define	SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)
	MCU MCSPI0 instance. More...

#define	SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)
	MCU MCSPI1 instance. More...

#define	SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)
	MCU MCSPI2 instance. More...

#define	SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)
	MCSPI0 instance. More...

#define	SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)
	MCSPI1 instance. More...

#define	SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)
	MCSPI2 instance. More...

#define	SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)
	MCSPI3 instance. More...

#define	SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)
	MCSPI4 instance. More...

#define	SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)
	MCSPI5 instance. More...

#define	SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)
	MCSPI6 instance. More...

#define	SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)
	MCSPI7 instance. More...

Macro Definition Documentation

◆ SPI_VARIANT_POST_BUILD

#define SPI_VARIANT_POST_BUILD (STD_ON)

SPI Build Variant. Build variants.(i.e Pre Compile,Post Build or Link time)

◆ SPI_CHANNELBUFFERS

#define SPI_CHANNELBUFFERS (SPI_IB_EB)

Pre Compile config macro name.

Buffer mode - Internal or External or Both

◆ SPI_IB_MAX_LENGTH

#define SPI_IB_MAX_LENGTH (64U)

Internal Buffer length in bytes - applicable only for SPI_IB.

◆ SPI_DEV_ERROR_DETECT

#define SPI_DEV_ERROR_DETECT (STD_ON)

Enable/disable SPI dev detect error.

◆ SPI_JOB_LOG

#define SPI_JOB_LOG (STD_ON)

Enable/disable SPI job log.

◆ SPI_MAX_JOB_LOG

#define SPI_MAX_JOB_LOG (100U)

Maximum job log entries when logging is ON.

◆ SPI_MAX_HW_DMA_UNIT

#define SPI_MAX_HW_DMA_UNIT (0U)

Enable/disable SPI DMA Support.

◆ SPI_DMA_ENABLE

#define SPI_DMA_ENABLE (STD_OFF)

Enable/disable SPI DMA Support.

◆ SPI_LEVEL_0

#define SPI_LEVEL_0 (0U)

Basic Synchronous functions.

◆ SPI_LEVEL_1

#define SPI_LEVEL_1 (1U)

Basic Asynchronous functions.

◆ SPI_LEVEL_2

#define SPI_LEVEL_2 (2U)

Synchronous and Asynchronous functions.

◆ SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT

#define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)

Concurrent sync transmit support - by defualt this is off.

◆ SPI_SCALEABILITY

#define SPI_SCALEABILITY (SPI_LEVEL_2)

Scalability level.

◆ SPI_VERSION_INFO_API

#define SPI_VERSION_INFO_API (STD_ON)

Enable/disable SPI get version info API.

◆ SPI_HW_STATUS_API

#define SPI_HW_STATUS_API (STD_ON)

Enable/disable SPI HW Status API.

◆ SPI_CANCEL_API

#define SPI_CANCEL_API (STD_ON)

Enable/disable SPI cancel API.

◆ SPI_MAX_CHANNELS_PER_JOB

#define SPI_MAX_CHANNELS_PER_JOB (1U)

Maximum channels allowed per job.

◆ SPI_MAX_JOBS_PER_SEQ

#define SPI_MAX_JOBS_PER_SEQ (1U)

Maximum jobs allowed per sequence.

◆ SPI_MAX_CHANNELS

#define SPI_MAX_CHANNELS (1U)

Maximum channels across all jobs/sequence/hwunit.

◆ SPI_MAX_JOBS

#define SPI_MAX_JOBS (1U)

Maximum jobs across all sequence/hwunit.

◆ SPI_MAX_SEQ

#define SPI_MAX_SEQ (1U)

Maximum sequence across all hwunit.

◆ SPI_MAX_HW_UNIT

#define SPI_MAX_HW_UNIT (8U)

Maximum HW unit - This should match the sum for the below units ISR which are ON.

◆ SPI_MAX_EXT_DEV

#define SPI_MAX_EXT_DEV (11U)

Maximum external device cfg.

◆ SPI_UNIT_MCU_MCSPI0_ACTIVE

#define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)

Enable/disable SPI MCU MCSPI0 unit ISR.

◆ SPI_UNIT_MCU_MCSPI1_ACTIVE

#define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)

Enable/disable SPI MCU MCSPI1 unit ISR.

◆ SPI_UNIT_MCU_MCSPI2_ACTIVE

#define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)

Enable/disable SPI MCU MCSPI2 unit ISR.

◆ SPI_UNIT_MCSPI0_ACTIVE

#define SPI_UNIT_MCSPI0_ACTIVE (STD_ON)

Enable/disable SPI MCSPI0 unit ISR.

◆ SPI_UNIT_MCSPI1_ACTIVE

#define SPI_UNIT_MCSPI1_ACTIVE (STD_ON)

Enable/disable SPI MCSPI1 unit ISR.

◆ SPI_UNIT_MCSPI2_ACTIVE

#define SPI_UNIT_MCSPI2_ACTIVE (STD_ON)

Enable/disable SPI MCSPI2 unit ISR.

◆ SPI_UNIT_MCSPI3_ACTIVE

#define SPI_UNIT_MCSPI3_ACTIVE (STD_ON)

Enable/disable SPI MCSPI3 unit ISR.

◆ SPI_UNIT_MCSPI4_ACTIVE

#define SPI_UNIT_MCSPI4_ACTIVE (STD_ON)

Enable/disable SPI MCSPI4 unit ISR.

◆ SPI_UNIT_MCSPI5_ACTIVE

#define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)

Enable/disable SPI MCSPI5 unit ISR.

◆ SPI_UNIT_MCSPI6_ACTIVE

#define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)

Enable/disable SPI MCSPI6 unit ISR.

◆ SPI_UNIT_MCSPI7_ACTIVE

#define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)

Enable/disable SPI MCSPI7 unit ISR.

◆ SPI_ISR_TYPE

#define SPI_ISR_TYPE (SPI_ISR_CAT1)

ISR type.

◆ SPI_OS_COUNTER_ID

#define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)

OS counter ID - used for timeout in case of error.

◆ SPI_TIMEOUT_DURATION

#define SPI_TIMEOUT_DURATION (32000U)

SPI timeout - used in McSPI IP reset Each tick is 31.25us (for 32K Counter). Wait for 100ms which comes to below value.

◆ SPI_REGISTER_READBACK_API

#define SPI_REGISTER_READBACK_API (STD_ON)

Enable/disable SPI register read back API.

◆ SPI_SAFETY_API

#define SPI_SAFETY_API (STD_ON)

Enable/disable SPI safety API.

◆ SpiConf_SpiChannel_SpiChannel_0

#define SpiConf_SpiChannel_SpiChannel_0 (0U)

Symbolic Name Channel Id - 0 SpiChannel_0.

◆ SpiConf_SpiExternalDevice_CS0

#define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)

Symbolic Name Chip Select - 0.

◆ SpiConf_SpiJob_SpiJob_0

#define SpiConf_SpiJob_SpiJob_0 (0U)

Symbolic Name Job Id - 0 SpiJob_0.

◆ SpiConf_SpiSequence_SpiSequence_0

#define SpiConf_SpiSequence_SpiSequence_0 (0U)

Symbolic Name Sequence Id - 0 SpiSequence_0.

◆ SpiConf_SpiExternalDevice_HwUnitId0

#define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId1

#define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId2

#define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId3

#define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId4

#define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId5

#define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId6

#define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)

Symbolic Name HW Unit - 0.

◆ SpiConf_SpiExternalDevice_HwUnitId7

#define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)

Symbolic Name HW Unit - 0.

◆ DemConf_DemEventParameter_SPI_DEM_NO_EVENT

#define DemConf_DemEventParameter_SPI_DEM_NO_EVENT (0xFFFFU)

◆ SPI_DEM_NO_EVENT

#define SPI_DEM_NO_EVENT DemConf_DemEventParameter_SPI_DEM_NO_EVENT

◆ SPI_E_HARDWARE_ERROR

#define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)

Hardware failed.

◆ SPI_UNIT_MCU_MCSPI0

#define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)

MCU MCSPI0 instance.

◆ SPI_UNIT_MCU_MCSPI1

#define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)

MCU MCSPI1 instance.

◆ SPI_UNIT_MCU_MCSPI2

#define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)

MCU MCSPI2 instance.

◆ SPI_UNIT_MCSPI0

#define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)

MCSPI0 instance.

◆ SPI_UNIT_MCSPI1

#define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)

MCSPI1 instance.

◆ SPI_UNIT_MCSPI2

#define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)

MCSPI2 instance.

◆ SPI_UNIT_MCSPI3

#define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)

MCSPI3 instance.

◆ SPI_UNIT_MCSPI4

#define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)

MCSPI4 instance.

◆ SPI_UNIT_MCSPI5

#define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)

MCSPI5 instance.

◆ SPI_UNIT_MCSPI6

#define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)

MCSPI6 instance.

◆ SPI_UNIT_MCSPI7

#define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)

MCSPI7 instance.

◆ SPI_HW_UNIT_CNT

#define SPI_HW_UNIT_CNT (11U)

Total HW units - used for array allocation. This should be +1 of the max unit number.

Typedef Documentation

◆ Spi_CacheWbInv

typedef void(* Spi_CacheWbInv) (uint8 *BufPtr, uint16 LenByte)

Cache write-back invalidate function.

Pointer to a function that performs the cache write-back invalidate operation. This function is to be called on TX buffers before they are given to the Spi controller hardware.

◆ Spi_CacheWb

typedef void(* Spi_CacheWb) (uint8 *BufPtr, uint16 LenByte)

Cache write-back function.

Pointer to a function that performs the cache write-back operation. This function is to be called on TX buffers before they are given to the Spi controller hardware.

◆ Spi_CacheInv

typedef void(* Spi_CacheInv) (uint8 *BufPtr, uint16 LenByte)

Cache invalidate function.

Pointer to a function that performs the cache invalidate operation. This function is to be called on RX buffers after they have been retrieved from the Spi controller hardware.

Enumeration Type Documentation

◆ Spi_StatusType

enum Spi_StatusType

This type defines a range of specific status for SPI Handler/Driver.

Enumerator
SPI_UNINIT	The SPI Handler/Driver is not initialized or not usable
SPI_IDLE	The SPI Handler/Driver is not currently transmitting any Job
SPI_BUSY	The SPI Handler/Driver is performing a SPI Job (transmit)

◆ Spi_JobResultType

enum Spi_JobResultType

This type defines a range of specific Jobs status for SPI Handler/Driver.

Enumerator
SPI_JOB_OK	The last transmission of the Job has been finished successfully
SPI_JOB_PENDING	The SPI Handler/Driver is performing a SPI Job. The meaning of this status is equal to SPI_BUSY
SPI_JOB_FAILED	The last transmission of the Job has failed
SPI_JOB_QUEUED	An asynchronous transmit Job has been accepted, while actual transmission for this Job has not started yet

◆ Spi_SeqResultType

enum Spi_SeqResultType

This type defines a range of specific Sequences status for SPI Handler/Driver.

Enumerator
SPI_SEQ_OK	The last transmission of the Sequence has been finished successfully
SPI_SEQ_PENDING	The SPI Handler/Driver is performing a SPI Sequence. The meaning of this status is equal to SPI_BUSY
SPI_SEQ_FAILED	The last transmission of the Sequence has failed
SPI_SEQ_CANCELLED	The last transmission of the Sequence has been canceled by user

◆ Spi_HwUnitResultType

enum Spi_HwUnitResultType

This type defines a range of specific HW unit status for SPI Handler/Driver.

Enumerator
SPI_HW_UNIT_OK	HW unit result is ok
SPI_HW_UNIT_PENDING	HW unit result is pending
SPI_HW_UNIT_FAILED	HW unit result is failed

◆ Spi_AsyncModeType

enum Spi_AsyncModeType

Specifies the asynchronous mechanism mode for SPI busses handled asynchronously in LEVEL 2.

Enumerator
SPI_POLLING_MODE	The asynchronous mechanism is ensured by polling, so interrupts related to SPI busses handled asynchronously are disabled
SPI_INTERRUPT_MODE	The asynchronous mechanism is ensured by interrupt, so interrupts related to SPI busses handled asynchronously are enabled

◆ Spi_TransferType

enum Spi_TransferType

Word transfer order - MSB first or LSB first.

Enumerator
SPI_MSB	MSB is transferred first. Only this is supported
SPI_LSB	LSB is transferred first. This is not supported

◆ Spi_LevelType

enum Spi_LevelType

Type for SPI Chip Select Polarity and Clock Idle Level.

Enumerator
SPI_LOW	Low clock or chip select
SPI_HIGH	High clock or chip select

◆ Spi_CsPinType

enum Spi_CsPinType

SPI Chip Select Pin.

Enumerator
SPI_CS0	Chip select 0
SPI_CS1	Chip select 1
SPI_CS2	Chip select 2
SPI_CS3	Chip select 3

◆ Spi_ClkMode

enum Spi_ClkMode

SPI Clock Mode - sets the clock polarity and phase. Note: These values are a direct register mapping. So don't change value.

Enumerator
SPI_CLK_MODE_0	SPI Clock Phase = 0 (rising edge latch), Polarity = 0 (Active HIGH)
SPI_CLK_MODE_1	SPI Clock Phase = 1 (falling edge latch), Polarity = 0 (Active HIGH)
SPI_CLK_MODE_2	SPI Clock Phase = 0 (rising edge latch), Polarity = 1 (Active LOW)
SPI_CLK_MODE_3	SPI Clock Phase = 1 (falling edge latch), Polarity = 1 (Active LOW)

◆ Spi_TxRxMode

enum Spi_TxRxMode

SPI TX/RX Mode.

Note:

These values are a direct register mapping. So don't change value.
RX only mode doesn't make sense in master mode because to receive data the master has to generate clock, which means it should transmit. Hence this mode is not supported. The user can alternatively set the TX buffer pointer to NULL and set the default TX value (defaultTxData) to make TX data line at the desired level.

Enumerator
SPI_TX_RX_MODE_BOTH	Both TX and RX are enabled
SPI_TX_RX_MODE_TX_ONLY	Only TX is enabled

◆ Spi_JobPriorityType

enum Spi_JobPriorityType

SPI Job Priority.

Enumerator
SPI_JOB_PRIORITY_0	Job priority 0 - low
SPI_JOB_PRIORITY_1	Job priority 1
SPI_JOB_PRIORITY_2	Job priority 2
SPI_JOB_PRIORITY_3	Job priority 3 - High

◆ Spi_CsModeType

enum Spi_CsModeType

SPI Chip Select Mode.

Enumerator
SPI_SINGLE	Chip select mode - single. Active only when transfer is on.
SPI_CONTINUOUS	Chip select mode - continuous. Active throughout.

◆ Spi_DataDelayType

enum Spi_DataDelayType

Spi_DataDelayType defines the number of interface clock cycles between CS toggling and first or last edge of MCSPI clock.

Enumerator
SPI_DATADELAY_0	0.5 clock cycles delay
SPI_DATADELAY_1	1.5 clock cycles delay
SPI_DATADELAY_2	2.5 clock cycles delay
SPI_DATADELAY_3	3.5 clock cycles delay

◆ Spi_DataLineReceiveType

enum Spi_DataLineReceiveType

Spi_DataLineReceiveType defines the lines selected for reception.

Enumerator
DATA_LINE_0_RECEPTION	Data line 0 (SPIDAT[0]) selected for reception
DATA_LINE_1_RECEPTION	Data line 1 (SPIDAT[1]) selected for reception

◆ Spi_DataLineTransmitType

enum Spi_DataLineTransmitType

Spi_DataLineTransmitType defines the lines selected for transmission.

Enumerator
DATA_LINE_NO_TRANSMISSION	No transmission on data lines
DATA_LINE_0_TRANSMISSION	Data line 0 (SPIDAT[0]) selected for transmission
DATA_LINE_1_TRANSMISSION	Data line 1 (SPIDAT[1]) selected for transmission
DATA_LINE_BOTH_TRANSMISSION	Data line 0 and 1 (SPIDAT[0] & SPIDAT[1]) selected for transmission

◆ Mcspi_IrqStatusType

enum Mcspi_IrqStatusType

Irq status and std return type.

Enumerator
SPI_NO_EVENT	No event ocuurs in Overflow/Under flow
SPI_EVENT_PENDING	Event occurs in Overflow/Under flow
SPI_STATUS_READ_FAIL	The status reading fails

Variable Documentation

◆ Spi_HwUnitBaseAddr

const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]

Introduction

Data Structures

Variables

Typedefs

Enumerations

Macros

SPI DEM Error codes to report

SPI HW unit Info

Macro Definition Documentation

◆ SPI_VARIANT_POST_BUILD

◆ SPI_CHANNELBUFFERS

◆ SPI_IB_MAX_LENGTH

◆ SPI_DEV_ERROR_DETECT

◆ SPI_JOB_LOG

◆ SPI_MAX_JOB_LOG

◆ SPI_MAX_HW_DMA_UNIT

◆ SPI_DMA_ENABLE

◆ SPI_LEVEL_0

◆ SPI_LEVEL_1

◆ SPI_LEVEL_2

◆ SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT

◆ SPI_SCALEABILITY

◆ SPI_VERSION_INFO_API

◆ SPI_HW_STATUS_API

◆ SPI_CANCEL_API

◆ SPI_MAX_CHANNELS_PER_JOB

◆ SPI_MAX_JOBS_PER_SEQ

◆ SPI_MAX_CHANNELS

◆ SPI_MAX_JOBS

◆ SPI_MAX_SEQ

◆ SPI_MAX_HW_UNIT

◆ SPI_MAX_EXT_DEV

◆ SPI_UNIT_MCU_MCSPI0_ACTIVE

◆ SPI_UNIT_MCU_MCSPI1_ACTIVE

◆ SPI_UNIT_MCU_MCSPI2_ACTIVE

◆ SPI_UNIT_MCSPI0_ACTIVE

◆ SPI_UNIT_MCSPI1_ACTIVE

◆ SPI_UNIT_MCSPI2_ACTIVE

◆ SPI_UNIT_MCSPI3_ACTIVE

◆ SPI_UNIT_MCSPI4_ACTIVE

◆ SPI_UNIT_MCSPI5_ACTIVE

◆ SPI_UNIT_MCSPI6_ACTIVE

◆ SPI_UNIT_MCSPI7_ACTIVE

◆ SPI_ISR_TYPE

◆ SPI_OS_COUNTER_ID

◆ SPI_TIMEOUT_DURATION

◆ SPI_REGISTER_READBACK_API

◆ SPI_SAFETY_API

◆ SpiConf_SpiChannel_SpiChannel_0

◆ SpiConf_SpiExternalDevice_CS0

◆ SpiConf_SpiJob_SpiJob_0

◆ SpiConf_SpiSequence_SpiSequence_0

◆ SpiConf_SpiExternalDevice_HwUnitId0

◆ SpiConf_SpiExternalDevice_HwUnitId1

◆ SpiConf_SpiExternalDevice_HwUnitId2

◆ SpiConf_SpiExternalDevice_HwUnitId3

◆ SpiConf_SpiExternalDevice_HwUnitId4

◆ SpiConf_SpiExternalDevice_HwUnitId5

◆ SpiConf_SpiExternalDevice_HwUnitId6

◆ SpiConf_SpiExternalDevice_HwUnitId7

◆ DemConf_DemEventParameter_SPI_DEM_NO_EVENT

◆ SPI_DEM_NO_EVENT

◆ SPI_E_HARDWARE_ERROR

◆ SPI_UNIT_MCU_MCSPI0

◆ SPI_UNIT_MCU_MCSPI1

◆ SPI_UNIT_MCU_MCSPI2

◆ SPI_UNIT_MCSPI0

◆ SPI_UNIT_MCSPI1

◆ SPI_UNIT_MCSPI2

◆ SPI_UNIT_MCSPI3

◆ SPI_UNIT_MCSPI4

◆ SPI_UNIT_MCSPI5

◆ SPI_UNIT_MCSPI6

◆ SPI_UNIT_MCSPI7

◆ SPI_HW_UNIT_CNT

Typedef Documentation

◆ Spi_CacheWbInv

◆ Spi_CacheWb

◆ Spi_CacheInv

Enumeration Type Documentation