I2SCC32XXDMA Hardware attributes. More...

#include <I2SCC32XXDMA.h>

Data Fields
uint32_t	baseAddr

uint32_t	intNum

uint32_t	intPriority

unsigned long	rxChannelIndex

unsigned long	txChannelIndex

uint16_t	xr0Pin

uint16_t	xr1Pin

uint16_t	clkxPin

uint16_t	clkPin

uint16_t	fsxPin

Detailed Description

I2SCC32XXDMA Hardware attributes.

These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For CC32XXWare these definitions are found in:

inc/hw_memmap.h
inc/hw_ints.h

intPriority is the I2S peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

const I2SCC32XXDMA_HWAttrsV1 i2sCC32XXHWAttrs[] = {
    {
        .baseAddr = I2S_BASE,
        .intNum = INT_I2S,
        .intPriority = (~0),
        .rxChannelIndex = UDMA_CH4_I2S_RX,
        .txChannelIndex = UDMA_CH5_I2S_TX,
        .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0,
        .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1,
        .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX,
        .clkPin = I2SCC32XXDMA_PIN_53_McACLK,
        .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX,
    }
};

Field Documentation

§ baseAddr

uint32_t I2SCC32XXDMA_HWAttrsV1::baseAddr

I2S Peripheral's base address

§ intNum

uint32_t I2SCC32XXDMA_HWAttrsV1::intNum

I2S Peripheral's interrupt vector

§ intPriority

uint32_t I2SCC32XXDMA_HWAttrsV1::intPriority

I2S Peripheral's interrupt priority

§ rxChannelIndex

unsigned long I2SCC32XXDMA_HWAttrsV1::rxChannelIndex

uDMA controlTable receive channel index

§ txChannelIndex

unsigned long I2SCC32XXDMA_HWAttrsV1::txChannelIndex

uDMA controlTable transmit channel index

§ xr0Pin

uint16_t I2SCC32XXDMA_HWAttrsV1::xr0Pin

I2S audio port data 0 pin

§ xr1Pin

uint16_t I2SCC32XXDMA_HWAttrsV1::xr1Pin

I2S audio port data 1 pin

§ clkxPin

uint16_t I2SCC32XXDMA_HWAttrsV1::clkxPin

I2S audio port clock O pin

§ clkPin

uint16_t I2SCC32XXDMA_HWAttrsV1::clkPin

I2S audio port data pin

§ fsxPin

uint16_t I2SCC32XXDMA_HWAttrsV1::fsxPin

I2S audio port frame sync

The documentation for this struct was generated from the following file:

I2SCC32XXDMA.h

Data Fields