EDMA3 Resource Manager Enums
[EDMA3 Resource Manager Symbols]

Enumerations
enum	EDMA3_RM_TccStatus {   EDMA3_RM_XFER_COMPLETE = 1,   EDMA3_RM_E_CC_DMA_EVT_MISS = 2,   EDMA3_RM_E_CC_QDMA_EVT_MISS = 3 }
	This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. More...
enum	EDMA3_RM_GlobalError {   EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1,   EDMA3_RM_E_CC_TCC = 2,   EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3,   EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4,   EDMA3_RM_E_TC_INVALID_ADDR = 5,   EDMA3_RM_E_TC_TR_ERROR = 6 }
	This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. More...
enum	EDMA3_RM_ResType {   EDMA3_RM_RES_DMA_CHANNEL = 1,   EDMA3_RM_RES_QDMA_CHANNEL = 2,   EDMA3_RM_RES_TCC = 3,   EDMA3_RM_RES_PARAM_SET = 4 }
	EDMA3 Resource Type. More...
enum	EDMA3_RM_HW_CHANNEL_EVENT {   EDMA3_RM_HW_CHANNEL_EVENT_0 = 0,   EDMA3_RM_HW_CHANNEL_EVENT_1,   EDMA3_RM_HW_CHANNEL_EVENT_2,   EDMA3_RM_HW_CHANNEL_EVENT_3,   EDMA3_RM_HW_CHANNEL_EVENT_4,   EDMA3_RM_HW_CHANNEL_EVENT_5,   EDMA3_RM_HW_CHANNEL_EVENT_6,   EDMA3_RM_HW_CHANNEL_EVENT_7,   EDMA3_RM_HW_CHANNEL_EVENT_8,   EDMA3_RM_HW_CHANNEL_EVENT_9,   EDMA3_RM_HW_CHANNEL_EVENT_10,   EDMA3_RM_HW_CHANNEL_EVENT_11,   EDMA3_RM_HW_CHANNEL_EVENT_12,   EDMA3_RM_HW_CHANNEL_EVENT_13,   EDMA3_RM_HW_CHANNEL_EVENT_14,   EDMA3_RM_HW_CHANNEL_EVENT_15,   EDMA3_RM_HW_CHANNEL_EVENT_16,   EDMA3_RM_HW_CHANNEL_EVENT_17,   EDMA3_RM_HW_CHANNEL_EVENT_18,   EDMA3_RM_HW_CHANNEL_EVENT_19,   EDMA3_RM_HW_CHANNEL_EVENT_20,   EDMA3_RM_HW_CHANNEL_EVENT_21,   EDMA3_RM_HW_CHANNEL_EVENT_22,   EDMA3_RM_HW_CHANNEL_EVENT_23,   EDMA3_RM_HW_CHANNEL_EVENT_24,   EDMA3_RM_HW_CHANNEL_EVENT_25,   EDMA3_RM_HW_CHANNEL_EVENT_26,   EDMA3_RM_HW_CHANNEL_EVENT_27,   EDMA3_RM_HW_CHANNEL_EVENT_28,   EDMA3_RM_HW_CHANNEL_EVENT_29,   EDMA3_RM_HW_CHANNEL_EVENT_30,   EDMA3_RM_HW_CHANNEL_EVENT_31,   EDMA3_RM_HW_CHANNEL_EVENT_32,   EDMA3_RM_HW_CHANNEL_EVENT_33,   EDMA3_RM_HW_CHANNEL_EVENT_34,   EDMA3_RM_HW_CHANNEL_EVENT_35,   EDMA3_RM_HW_CHANNEL_EVENT_36,   EDMA3_RM_HW_CHANNEL_EVENT_37,   EDMA3_RM_HW_CHANNEL_EVENT_38,   EDMA3_RM_HW_CHANNEL_EVENT_39,   EDMA3_RM_HW_CHANNEL_EVENT_40,   EDMA3_RM_HW_CHANNEL_EVENT_41,   EDMA3_RM_HW_CHANNEL_EVENT_42,   EDMA3_RM_HW_CHANNEL_EVENT_43,   EDMA3_RM_HW_CHANNEL_EVENT_44,   EDMA3_RM_HW_CHANNEL_EVENT_45,   EDMA3_RM_HW_CHANNEL_EVENT_46,   EDMA3_RM_HW_CHANNEL_EVENT_47,   EDMA3_RM_HW_CHANNEL_EVENT_48,   EDMA3_RM_HW_CHANNEL_EVENT_49,   EDMA3_RM_HW_CHANNEL_EVENT_50,   EDMA3_RM_HW_CHANNEL_EVENT_51,   EDMA3_RM_HW_CHANNEL_EVENT_52,   EDMA3_RM_HW_CHANNEL_EVENT_53,   EDMA3_RM_HW_CHANNEL_EVENT_54,   EDMA3_RM_HW_CHANNEL_EVENT_55,   EDMA3_RM_HW_CHANNEL_EVENT_56,   EDMA3_RM_HW_CHANNEL_EVENT_57,   EDMA3_RM_HW_CHANNEL_EVENT_58,   EDMA3_RM_HW_CHANNEL_EVENT_59,   EDMA3_RM_HW_CHANNEL_EVENT_60,   EDMA3_RM_HW_CHANNEL_EVENT_61,   EDMA3_RM_HW_CHANNEL_EVENT_62,   EDMA3_RM_HW_CHANNEL_EVENT_63 }
	DMA Channels assigned to different Hardware Events. More...
enum	EDMA3_RM_QdmaTrigWord {   EDMA3_RM_QDMA_TRIG_OPT = 0,   EDMA3_RM_QDMA_TRIG_SRC = 1,   EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2,   EDMA3_RM_QDMA_TRIG_DST = 3,   EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4,   EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5,   EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6,   EDMA3_RM_QDMA_TRIG_CCNT = 7,   EDMA3_RM_QDMA_TRIG_DEFAULT = 7 }
	QDMA Trigger Word. More...
enum	EDMA3_RM_Cntrlr_PhyAddr {   EDMA3_RM_CC_PHY_ADDR = 0,   EDMA3_RM_TC0_PHY_ADDR,   EDMA3_RM_TC1_PHY_ADDR,   EDMA3_RM_TC2_PHY_ADDR,   EDMA3_RM_TC3_PHY_ADDR,   EDMA3_RM_TC4_PHY_ADDR,   EDMA3_RM_TC5_PHY_ADDR,   EDMA3_RM_TC6_PHY_ADDR,   EDMA3_RM_TC7_PHY_ADDR }
	CC/TC Physical Address. More...
enum	EDMA3_RM_IoctlCmd { ,   EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION,   EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,   EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION,   EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION }
	EDMA3 Resource Manager IOCTL commands. More...

---

Enumeration Type Documentation

enum EDMA3_RM_TccStatus

This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status.

Enumerator:

EDMA3_RM_XFER_COMPLETE	DMA Transfer successfully completed (true completion mode) or submitted to the TC (early completion mode).
EDMA3_RM_E_CC_DMA_EVT_MISS	Channel Controller has reported an error DMA missed events:- for all 64 DMA channels. These get latched in the event missed registers (EMR/EMRH).
EDMA3_RM_E_CC_QDMA_EVT_MISS	QDMA missed events:- for all QDMA channels. These get latched in the QDMA event missed register (QEMR).

enum EDMA3_RM_GlobalError

This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer.

Enumerator:

EDMA3_RM_E_CC_QUE_THRES_EXCEED	Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl
EDMA3_RM_E_CC_TCC	TCC error:- for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the CCERR.
EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR	Transfer Controller has reported an error Detection of a Read error signaled by the source or destination address
EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR	Detection of a Write error signaled by the source or destination address
EDMA3_RM_E_TC_INVALID_ADDR	Attempt to read or write to an invalid address in the configuration memory map.
EDMA3_RM_E_TC_TR_ERROR	Detection of a FIFO mode TR violating the FIFO mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes).

enum EDMA3_RM_ResType

EDMA3 Resource Type.

Enumerator:

EDMA3_RM_RES_DMA_CHANNEL	DMA Channel resource
EDMA3_RM_RES_QDMA_CHANNEL	QDMA Channel resource
EDMA3_RM_RES_TCC	TCC resource
EDMA3_RM_RES_PARAM_SET	Parameter RAM Set resource

enum EDMA3_RM_HW_CHANNEL_EVENT

DMA Channels assigned to different Hardware Events.

They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. for eg, the sample SoC specific file "soc.h" can have these defines:

define EDMA3_RM_HW_CHANNEL_MCBSP_TX EDMA3_RM_HW_CHANNEL_EVENT_2 define EDMA3_RM_HW_CHANNEL_MCBSP_RX EDMA3_RM_HW_CHANNEL_EVENT_3

These defines will be used by the MCBSP driver. The same event EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:

EDMA3_RM_HW_CHANNEL_EVENT_0	Channel assigned to EDMA3 Event 0
EDMA3_RM_HW_CHANNEL_EVENT_1	Channel assigned to EDMA3 Event 1
EDMA3_RM_HW_CHANNEL_EVENT_2	Channel assigned to EDMA3 Event 2
EDMA3_RM_HW_CHANNEL_EVENT_3	Channel assigned to EDMA3 Event 3
EDMA3_RM_HW_CHANNEL_EVENT_4	Channel assigned to EDMA3 Event 4
EDMA3_RM_HW_CHANNEL_EVENT_5	Channel assigned to EDMA3 Event 5
EDMA3_RM_HW_CHANNEL_EVENT_6	Channel assigned to EDMA3 Event 6
EDMA3_RM_HW_CHANNEL_EVENT_7	Channel assigned to EDMA3 Event 7
EDMA3_RM_HW_CHANNEL_EVENT_8	Channel assigned to EDMA3 Event 8
EDMA3_RM_HW_CHANNEL_EVENT_9	Channel assigned to EDMA3 Event 9
EDMA3_RM_HW_CHANNEL_EVENT_10	Channel assigned to EDMA3 Event 10
EDMA3_RM_HW_CHANNEL_EVENT_11	Channel assigned to EDMA3 Event 11
EDMA3_RM_HW_CHANNEL_EVENT_12	Channel assigned to EDMA3 Event 12
EDMA3_RM_HW_CHANNEL_EVENT_13	Channel assigned to EDMA3 Event 13
EDMA3_RM_HW_CHANNEL_EVENT_14	Channel assigned to EDMA3 Event 14
EDMA3_RM_HW_CHANNEL_EVENT_15	Channel assigned to EDMA3 Event 15
EDMA3_RM_HW_CHANNEL_EVENT_16	Channel assigned to EDMA3 Event 16
EDMA3_RM_HW_CHANNEL_EVENT_17	Channel assigned to EDMA3 Event 17
EDMA3_RM_HW_CHANNEL_EVENT_18	Channel assigned to EDMA3 Event 18
EDMA3_RM_HW_CHANNEL_EVENT_19	Channel assigned to EDMA3 Event 19
EDMA3_RM_HW_CHANNEL_EVENT_20	Channel assigned to EDMA3 Event 20
EDMA3_RM_HW_CHANNEL_EVENT_21	Channel assigned to EDMA3 Event 21
EDMA3_RM_HW_CHANNEL_EVENT_22	Channel assigned to EDMA3 Event 22
EDMA3_RM_HW_CHANNEL_EVENT_23	Channel assigned to EDMA3 Event 23
EDMA3_RM_HW_CHANNEL_EVENT_24	Channel assigned to EDMA3 Event 24
EDMA3_RM_HW_CHANNEL_EVENT_25	Channel assigned to EDMA3 Event 25
EDMA3_RM_HW_CHANNEL_EVENT_26	Channel assigned to EDMA3 Event 26
EDMA3_RM_HW_CHANNEL_EVENT_27	Channel assigned to EDMA3 Event 27
EDMA3_RM_HW_CHANNEL_EVENT_28	Channel assigned to EDMA3 Event 28
EDMA3_RM_HW_CHANNEL_EVENT_29	Channel assigned to EDMA3 Event 29
EDMA3_RM_HW_CHANNEL_EVENT_30	Channel assigned to EDMA3 Event 30
EDMA3_RM_HW_CHANNEL_EVENT_31	Channel assigned to EDMA3 Event 31
EDMA3_RM_HW_CHANNEL_EVENT_32	Channel assigned to EDMA3 Event 32
EDMA3_RM_HW_CHANNEL_EVENT_33	Channel assigned to EDMA3 Event 33
EDMA3_RM_HW_CHANNEL_EVENT_34	Channel assigned to EDMA3 Event 34
EDMA3_RM_HW_CHANNEL_EVENT_35	Channel assigned to EDMA3 Event 35
EDMA3_RM_HW_CHANNEL_EVENT_36	Channel assigned to EDMA3 Event 36
EDMA3_RM_HW_CHANNEL_EVENT_37	Channel assigned to EDMA3 Event 37
EDMA3_RM_HW_CHANNEL_EVENT_38	Channel assigned to EDMA3 Event 38
EDMA3_RM_HW_CHANNEL_EVENT_39	Channel assigned to EDMA3 Event 39
EDMA3_RM_HW_CHANNEL_EVENT_40	Channel assigned to EDMA3 Event 40
EDMA3_RM_HW_CHANNEL_EVENT_41	Channel assigned to EDMA3 Event 41
EDMA3_RM_HW_CHANNEL_EVENT_42	Channel assigned to EDMA3 Event 42
EDMA3_RM_HW_CHANNEL_EVENT_43	Channel assigned to EDMA3 Event 43
EDMA3_RM_HW_CHANNEL_EVENT_44	Channel assigned to EDMA3 Event 44
EDMA3_RM_HW_CHANNEL_EVENT_45	Channel assigned to EDMA3 Event 45
EDMA3_RM_HW_CHANNEL_EVENT_46	Channel assigned to EDMA3 Event 46
EDMA3_RM_HW_CHANNEL_EVENT_47	Channel assigned to EDMA3 Event 47
EDMA3_RM_HW_CHANNEL_EVENT_48	Channel assigned to EDMA3 Event 48
EDMA3_RM_HW_CHANNEL_EVENT_49	Channel assigned to EDMA3 Event 49
EDMA3_RM_HW_CHANNEL_EVENT_50	Channel assigned to EDMA3 Event 50
EDMA3_RM_HW_CHANNEL_EVENT_51	Channel assigned to EDMA3 Event 51
EDMA3_RM_HW_CHANNEL_EVENT_52	Channel assigned to EDMA3 Event 52
EDMA3_RM_HW_CHANNEL_EVENT_53	Channel assigned to EDMA3 Event 53
EDMA3_RM_HW_CHANNEL_EVENT_54	Channel assigned to EDMA3 Event 54
EDMA3_RM_HW_CHANNEL_EVENT_55	Channel assigned to EDMA3 Event 55
EDMA3_RM_HW_CHANNEL_EVENT_56	Channel assigned to EDMA3 Event 56
EDMA3_RM_HW_CHANNEL_EVENT_57	Channel assigned to EDMA3 Event 57
EDMA3_RM_HW_CHANNEL_EVENT_58	Channel assigned to EDMA3 Event 58
EDMA3_RM_HW_CHANNEL_EVENT_59	Channel assigned to EDMA3 Event 59
EDMA3_RM_HW_CHANNEL_EVENT_60	Channel assigned to EDMA3 Event 60
EDMA3_RM_HW_CHANNEL_EVENT_61	Channel assigned to EDMA3 Event 61
EDMA3_RM_HW_CHANNEL_EVENT_62	Channel assigned to EDMA3 Event 62
EDMA3_RM_HW_CHANNEL_EVENT_63	Channel assigned to EDMA3 Event 63

enum EDMA3_RM_QdmaTrigWord

QDMA Trigger Word.

Use this enum to set the QDMA trigger word to any of the 8 DWords(uint32_t) within a Parameter RAM set

Enumerator:

EDMA3_RM_QDMA_TRIG_OPT	Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC	Set the SRC field (Offset Address 4h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_ACNT_BCNT	Set the (ACNT + BCNT) field (Offset Address 8h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_DST	Set the DST field (Offset Address Ch Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX	Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD	Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX	Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_CCNT	Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_DEFAULT	Default Trigger Word

enum EDMA3_RM_Cntrlr_PhyAddr

CC/TC Physical Address.

Use this enum to get the physical address of the Channel Controller or the Transfer Controller. The address returned could be used by the advanced users to set/get some specific registers direclty.

Enumerator:

EDMA3_RM_CC_PHY_ADDR	Channel Controller Physical Address
EDMA3_RM_TC0_PHY_ADDR	Transfer Controller 0 Physical Address
EDMA3_RM_TC1_PHY_ADDR	Transfer Controller 1 Physical Address
EDMA3_RM_TC2_PHY_ADDR	Transfer Controller 2 Physical Address
EDMA3_RM_TC3_PHY_ADDR	Transfer Controller 3 Physical Address
EDMA3_RM_TC4_PHY_ADDR	Transfer Controller 4 Physical Address
EDMA3_RM_TC5_PHY_ADDR	Transfer Controller 5 Physical Address
EDMA3_RM_TC6_PHY_ADDR	Transfer Controller 6 Physical Address
EDMA3_RM_TC7_PHY_ADDR	Transfer Controller 7 Physical Address

enum EDMA3_RM_IoctlCmd

EDMA3 Resource Manager IOCTL commands.

Enumerator:

EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION	PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option. For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1; To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0; For all other values, it will return error. By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.
EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION	To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired;
EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION	Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending upon this option. For e.g., To modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)1; To NOT modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)0; For all other values, it will return error. By default, Registers or PaRAM Sets will be programmed during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.
EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION	To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). If the value read is '1', it means that the registers/PaRAMs are getting programmed during allocation. If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed during allocation. For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired;