Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
#include <edma3_drv.h>
Data Fields | |
| uint32_t | numDmaChannels |
| uint32_t | numQdmaChannels |
| uint32_t | numTccs |
| uint32_t | numPaRAMSets |
| uint32_t | numEvtQueue |
| uint32_t | numTcs |
| uint32_t | numRegions |
| uint32_t | dmaChPaRAMMapExists |
| Channel mapping existence. | |
| uint32_t | memProtectionExists |
| void * | globalRegs |
| void * | tcRegs [EDMA3_MAX_TC] |
| uint32_t | xferCompleteInt |
| uint32_t | ccError |
| uint32_t | tcError [EDMA3_MAX_TC] |
| uint32_t | evtQPri [EDMA3_MAX_EVT_QUE] |
| EDMA3 TC priority setting. | |
| uint32_t | evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE] |
| Event Queues Watermark Levels. | |
| uint32_t | tcDefaultBurstSize [EDMA3_MAX_TC] |
| Default Burst Size (DBS) of TCs. | |
| uint32_t | dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH] |
| Mapping from DMA channels to PaRAM Sets. | |
| uint32_t | dmaChannelTccMap [EDMA3_MAX_DMA_CH] |
| Mapping from DMA channels to TCCs. | |
| uint32_t | dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS] |
| Mapping from DMA channels to Hardware Events. | |
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.
Number of DMA Channels supported by the underlying EDMA3 Controller.
Number of QDMA Channels supported by the underlying EDMA3 Controller
| uint32_t EDMA3_DRV_GblConfigParams::numTccs |
Number of Interrupt Channels supported by the underlying EDMA3 Controller
Number of PaRAM Sets supported by the underlying EDMA3 Controller
Number of Event Queues in the underlying EDMA3 Controller
| uint32_t EDMA3_DRV_GblConfigParams::numTcs |
Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
Number of Regions in the underlying EDMA3 Controller
Channel mapping existence.
A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.
A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels).
Existence of memory protection feature
Base address of EDMA3 CC memory mapped registers.
| void* EDMA3_DRV_GblConfigParams::tcRegs[EDMA3_MAX_TC] |
Base address of EDMA3 TCs memory mapped registers.
EDMA3 transfer completion interrupt line (could be different for ARM and DSP)
| uint32_t EDMA3_DRV_GblConfigParams::ccError |
EDMA3 CC error interrupt line (could be different for ARM and DSP)
| uint32_t EDMA3_DRV_GblConfigParams::tcError[EDMA3_MAX_TC] |
EDMA3 TCs error interrupt line (could be different for ARM and DSP)
| uint32_t EDMA3_DRV_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE] |
EDMA3 TC priority setting.
User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)
| uint32_t EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE] |
Event Queues Watermark Levels.
To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).
| uint32_t EDMA3_DRV_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC] |
Default Burst Size (DBS) of TCs.
An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes.
| uint32_t EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH] |
Mapping from DMA channels to PaRAM Sets.
If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use.
| uint32_t EDMA3_DRV_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH] |
Mapping from DMA channels to TCCs.
This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel.
| uint32_t EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS] |
Mapping from DMA channels to Hardware Events.
Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also.
1.6.1