Defines | |
| #define | EDMA3_LLD_DRV_VERSION_ID (0x020B0002) |
| This is the EDMA3 LLD Version. Versions numbers are encoded in the following format: 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD). | |
| #define | EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.11.00.02" |
| This is the version string which describes the EDMA3 LLD along with the date and build information. | |
| #define | EDMA3_DRV_E_BASE (-128) |
| EDMA3 Driver Error Codes Base define. | |
| #define | EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE) |
| #define | EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1) |
| #define | EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2) |
| #define | EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3) |
| #define | EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4) |
| #define | EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5) |
| #define | EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6) |
| #define | EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7) |
| #define | EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8) |
| #define | EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9) |
| #define | EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10) |
| #define | EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11) |
| #define | EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12) |
| #define | EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13) |
| #define | EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14) |
| #define | EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15) |
| #define | EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16) |
| #define | EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP |
| #define | EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP |
| #define | EDMA3_DRV_DMA_CHANNEL_ANY 1002u |
| #define | EDMA3_DRV_QDMA_CHANNEL_ANY 1003u |
| #define | EDMA3_DRV_TCC_ANY 1004u |
| #define | EDMA3_DRV_LINK_CHANNEL 1005u |
| #define | EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u |
| #define | EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) |
| QDMA Channel defines. | |
| #define | EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u) |
| #define | EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u) |
| #define | EDMA3_DRV_CHANNEL_CLEAN 0x0000u |
| Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from EDMA3_DRV_getChannelStatus(). | |
| #define | EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u |
| #define | EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u |
| #define | EDMA3_DRV_CHANNEL_ERR 0x0004u |
| #define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE) |
EDMA3 Driver Object Not Deleted yet. So it cannot be created.
| #define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1) |
EDMA3 Driver Object Not Closed yet. So it cannot be deleted.
| #define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2) |
EDMA3 Driver Object Not Opened yet So it cannot be closed.
| #define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3) |
While closing EDMA3 Driver, Resource Manager Close Failed.
| #define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4) |
The requested DMA Channel not available
| #define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5) |
The requested QDMA Channel not available
| #define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6) |
The requested PaRAM Set not available
| #define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7) |
The requested TCC not available
| #define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8) |
The registration of TCC failed
| #define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9) |
The binding of Channel and PaRAM Set failed
| #define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10) |
The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned.
| #define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11) |
Invalid Parameter passed to API
| #define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12) |
Invalid State of EDMA3 HW Obj
| #define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13) |
EDMA3 Driver instance already exists for the specified region
| #define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14) |
FIFO width not supported by the requested TC
| #define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15) |
Semaphore related error
| #define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16) |
EDMA3 Driver Instance does not exist, it is not opened yet
| #define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP |
This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.
This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets.
| #define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP |
This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.
This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs.
| #define EDMA3_DRV_DMA_CHANNEL_ANY 1002u |
Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned.
| #define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u |
Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned.
| #define EDMA3_DRV_TCC_ANY 1004u |
Used to specify any available TCC while requesting one. Used in the API EDMA3_DRV_requestChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned.
| #define EDMA3_DRV_LINK_CHANNEL 1005u |
Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.
| #define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u |
Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.
| #define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) |
QDMA Channel defines.
They should be used while requesting a specific QDMA channel in API EDMA3_DRV_requestChannel() as the argument (*pLch). Please note that these defines should ONLY be used in the API EDMA3_DRV_requestChannel() and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0
| #define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u) |
QDMA Channel 1
| #define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u) |
QDMA Channel 2
| #define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u) |
QDMA Channel 3
| #define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u) |
QDMA Channel 4
| #define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u) |
QDMA Channel 5
| #define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u) |
QDMA Channel 6
| #define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u) |
QDMA Channel 7
| #define EDMA3_DRV_CHANNEL_CLEAN 0x0000u |
Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from EDMA3_DRV_getChannelStatus().
Channel is clean; no pending event, completion interrupt and event miss interrupt
| #define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u |
Pending event is detected on the DMA channel
| #define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u |
Transfer completion interrupt is detected on the DMA/QDMA channel
| #define EDMA3_DRV_CHANNEL_ERR 0x0004u |
Event miss error interrupt is detected on the DMA/QDMA channel
1.6.1