EDMA3 Driver Enums
[EDMA3 Driver Symbols]


Enumerations

enum  EDMA3_DRV_HW_CHANNEL_EVENT {
  EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
  EDMA3_DRV_HW_CHANNEL_EVENT_1,
  EDMA3_DRV_HW_CHANNEL_EVENT_2,
  EDMA3_DRV_HW_CHANNEL_EVENT_3,
  EDMA3_DRV_HW_CHANNEL_EVENT_4,
  EDMA3_DRV_HW_CHANNEL_EVENT_5,
  EDMA3_DRV_HW_CHANNEL_EVENT_6,
  EDMA3_DRV_HW_CHANNEL_EVENT_7,
  EDMA3_DRV_HW_CHANNEL_EVENT_8,
  EDMA3_DRV_HW_CHANNEL_EVENT_9,
  EDMA3_DRV_HW_CHANNEL_EVENT_10,
  EDMA3_DRV_HW_CHANNEL_EVENT_11,
  EDMA3_DRV_HW_CHANNEL_EVENT_12,
  EDMA3_DRV_HW_CHANNEL_EVENT_13,
  EDMA3_DRV_HW_CHANNEL_EVENT_14,
  EDMA3_DRV_HW_CHANNEL_EVENT_15,
  EDMA3_DRV_HW_CHANNEL_EVENT_16,
  EDMA3_DRV_HW_CHANNEL_EVENT_17,
  EDMA3_DRV_HW_CHANNEL_EVENT_18,
  EDMA3_DRV_HW_CHANNEL_EVENT_19,
  EDMA3_DRV_HW_CHANNEL_EVENT_20,
  EDMA3_DRV_HW_CHANNEL_EVENT_21,
  EDMA3_DRV_HW_CHANNEL_EVENT_22,
  EDMA3_DRV_HW_CHANNEL_EVENT_23,
  EDMA3_DRV_HW_CHANNEL_EVENT_24,
  EDMA3_DRV_HW_CHANNEL_EVENT_25,
  EDMA3_DRV_HW_CHANNEL_EVENT_26,
  EDMA3_DRV_HW_CHANNEL_EVENT_27,
  EDMA3_DRV_HW_CHANNEL_EVENT_28,
  EDMA3_DRV_HW_CHANNEL_EVENT_29,
  EDMA3_DRV_HW_CHANNEL_EVENT_30,
  EDMA3_DRV_HW_CHANNEL_EVENT_31,
  EDMA3_DRV_HW_CHANNEL_EVENT_32,
  EDMA3_DRV_HW_CHANNEL_EVENT_33,
  EDMA3_DRV_HW_CHANNEL_EVENT_34,
  EDMA3_DRV_HW_CHANNEL_EVENT_35,
  EDMA3_DRV_HW_CHANNEL_EVENT_36,
  EDMA3_DRV_HW_CHANNEL_EVENT_37,
  EDMA3_DRV_HW_CHANNEL_EVENT_38,
  EDMA3_DRV_HW_CHANNEL_EVENT_39,
  EDMA3_DRV_HW_CHANNEL_EVENT_40,
  EDMA3_DRV_HW_CHANNEL_EVENT_41,
  EDMA3_DRV_HW_CHANNEL_EVENT_42,
  EDMA3_DRV_HW_CHANNEL_EVENT_43,
  EDMA3_DRV_HW_CHANNEL_EVENT_44,
  EDMA3_DRV_HW_CHANNEL_EVENT_45,
  EDMA3_DRV_HW_CHANNEL_EVENT_46,
  EDMA3_DRV_HW_CHANNEL_EVENT_47,
  EDMA3_DRV_HW_CHANNEL_EVENT_48,
  EDMA3_DRV_HW_CHANNEL_EVENT_49,
  EDMA3_DRV_HW_CHANNEL_EVENT_50,
  EDMA3_DRV_HW_CHANNEL_EVENT_51,
  EDMA3_DRV_HW_CHANNEL_EVENT_52,
  EDMA3_DRV_HW_CHANNEL_EVENT_53,
  EDMA3_DRV_HW_CHANNEL_EVENT_54,
  EDMA3_DRV_HW_CHANNEL_EVENT_55,
  EDMA3_DRV_HW_CHANNEL_EVENT_56,
  EDMA3_DRV_HW_CHANNEL_EVENT_57,
  EDMA3_DRV_HW_CHANNEL_EVENT_58,
  EDMA3_DRV_HW_CHANNEL_EVENT_59,
  EDMA3_DRV_HW_CHANNEL_EVENT_60,
  EDMA3_DRV_HW_CHANNEL_EVENT_61,
  EDMA3_DRV_HW_CHANNEL_EVENT_62,
  EDMA3_DRV_HW_CHANNEL_EVENT_63
}
 DMA Channels assigned to different Hardware Events. More...
enum  EDMA3_DRV_OptField {
  EDMA3_DRV_OPT_FIELD_SAM = 0,
  EDMA3_DRV_OPT_FIELD_DAM = 1,
  EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
  EDMA3_DRV_OPT_FIELD_STATIC = 3,
  EDMA3_DRV_OPT_FIELD_FWID = 4,
  EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
  EDMA3_DRV_OPT_FIELD_TCC = 6,
  EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
  EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
  EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
  EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
}
 OPT Field Offset. More...
enum  EDMA3_DRV_AddrMode {
  EDMA3_DRV_ADDR_MODE_INCR = 0,
  EDMA3_DRV_ADDR_MODE_FIFO = 1
}
 EDMA Addressing modes. More...
enum  EDMA3_DRV_SyncType {
  EDMA3_DRV_SYNC_A = 0,
  EDMA3_DRV_SYNC_AB = 1
}
 EDMA Transfer Synchronization type. More...
enum  EDMA3_DRV_StaticMode {
  EDMA3_DRV_STATIC_DIS = 0,
  EDMA3_DRV_STATIC_EN = 1
}
 True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. More...
enum  EDMA3_DRV_FifoWidth {
  EDMA3_DRV_W8BIT = 0,
  EDMA3_DRV_W16BIT = 1,
  EDMA3_DRV_W32BIT = 2,
  EDMA3_DRV_W64BIT = 3,
  EDMA3_DRV_W128BIT = 4,
  EDMA3_DRV_W256BIT = 5
}
 EDMA3 FIFO width. More...
enum  EDMA3_DRV_TccMode {
  EDMA3_DRV_TCCMODE_NORMAL = 0,
  EDMA3_DRV_TCCMODE_EARLY = 1
}
 Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. More...
enum  EDMA3_DRV_TcintEn {
  EDMA3_DRV_TCINTEN_DIS = 0,
  EDMA3_DRV_TCINTEN_EN = 1
}
 Transfer complete interrupt enable. More...
enum  EDMA3_DRV_ItcintEn {
  EDMA3_DRV_ITCINTEN_DIS = 0,
  EDMA3_DRV_ITCINTEN_EN = 1
}
 Intermediate Transfer complete interrupt enable. More...
enum  EDMA3_DRV_TcchEn {
  EDMA3_DRV_TCCHEN_DIS = 0,
  EDMA3_DRV_TCCHEN_EN = 1
}
 Transfer complete chaining enable. More...
enum  EDMA3_DRV_ItcchEn {
  EDMA3_DRV_ITCCHEN_DIS = 0,
  EDMA3_DRV_ITCCHEN_EN = 1
}
 Intermediate Transfer complete chaining enable. More...
enum  EDMA3_DRV_TrigMode {
  EDMA3_DRV_TRIG_MODE_MANUAL = 0,
  EDMA3_DRV_TRIG_MODE_QDMA = 1,
  EDMA3_DRV_TRIG_MODE_EVENT = 2,
  EDMA3_DRV_TRIG_MODE_NONE = 3
}
 EDMA Trigger Mode Selection. More...
enum  EDMA3_DRV_PaRAMEntry {
  EDMA3_DRV_PARAM_ENTRY_OPT = 0,
  EDMA3_DRV_PARAM_ENTRY_SRC = 1,
  EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
  EDMA3_DRV_PARAM_ENTRY_DST = 3,
  EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
  EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
  EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
  EDMA3_DRV_PARAM_ENTRY_CCNT = 7
}
 PaRAM Set Entry type. More...
enum  EDMA3_DRV_PaRAMField {
  EDMA3_DRV_PARAM_FIELD_OPT = 0,
  EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,
  EDMA3_DRV_PARAM_FIELD_ACNT = 2,
  EDMA3_DRV_PARAM_FIELD_BCNT = 3,
  EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,
  EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,
  EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,
  EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,
  EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,
  EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,
  EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,
  EDMA3_DRV_PARAM_FIELD_CCNT = 11
}
 PaRAM Set Field type. More...
enum  EDMA3_DRV_IoctlCmd { ,
  EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
  EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION
}
 EDMA3 Driver IOCTL commands. More...
enum  EDMA3_DRV_Tc_Err {
  EDMA3_DRV_TC_ERR_BUSERR_DIS = 0,
  EDMA3_DRV_TC_ERR_BUSERR_EN,
  EDMA3_DRV_TC_ERR_TRERR_DIS,
  EDMA3_DRV_TC_ERR_TRERR_EN,
  EDMA3_DRV_TC_ERR_MMRAERR_DIS,
  EDMA3_DRV_TC_ERR_MMRAERR_EN,
  EDMA3_DRV_TC_ERR_DIS,
  EDMA3_DRV_TC_ERR_EN
}
 TC Error Enablers. More...

Enumeration Type Documentation

enum EDMA3_DRV_HW_CHANNEL_EVENT

DMA Channels assigned to different Hardware Events.

They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. for eg, the sample SoC specific file "soc.h" can have these defines:

define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3

These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
EDMA3_DRV_HW_CHANNEL_EVENT_0  Channel assigned to EDMA3 Event 0
EDMA3_DRV_HW_CHANNEL_EVENT_1  Channel assigned to EDMA3 Event 1
EDMA3_DRV_HW_CHANNEL_EVENT_2  Channel assigned to EDMA3 Event 2
EDMA3_DRV_HW_CHANNEL_EVENT_3  Channel assigned to EDMA3 Event 3
EDMA3_DRV_HW_CHANNEL_EVENT_4  Channel assigned to EDMA3 Event 4
EDMA3_DRV_HW_CHANNEL_EVENT_5  Channel assigned to EDMA3 Event 5
EDMA3_DRV_HW_CHANNEL_EVENT_6  Channel assigned to EDMA3 Event 6
EDMA3_DRV_HW_CHANNEL_EVENT_7  Channel assigned to EDMA3 Event 7
EDMA3_DRV_HW_CHANNEL_EVENT_8  Channel assigned to EDMA3 Event 8
EDMA3_DRV_HW_CHANNEL_EVENT_9  Channel assigned to EDMA3 Event 9
EDMA3_DRV_HW_CHANNEL_EVENT_10  Channel assigned to EDMA3 Event 10
EDMA3_DRV_HW_CHANNEL_EVENT_11  Channel assigned to EDMA3 Event 11
EDMA3_DRV_HW_CHANNEL_EVENT_12  Channel assigned to EDMA3 Event 12
EDMA3_DRV_HW_CHANNEL_EVENT_13  Channel assigned to EDMA3 Event 13
EDMA3_DRV_HW_CHANNEL_EVENT_14  Channel assigned to EDMA3 Event 14
EDMA3_DRV_HW_CHANNEL_EVENT_15  Channel assigned to EDMA3 Event 15
EDMA3_DRV_HW_CHANNEL_EVENT_16  Channel assigned to EDMA3 Event 16
EDMA3_DRV_HW_CHANNEL_EVENT_17  Channel assigned to EDMA3 Event 17
EDMA3_DRV_HW_CHANNEL_EVENT_18  Channel assigned to EDMA3 Event 18
EDMA3_DRV_HW_CHANNEL_EVENT_19  Channel assigned to EDMA3 Event 19
EDMA3_DRV_HW_CHANNEL_EVENT_20  Channel assigned to EDMA3 Event 20
EDMA3_DRV_HW_CHANNEL_EVENT_21  Channel assigned to EDMA3 Event 21
EDMA3_DRV_HW_CHANNEL_EVENT_22  Channel assigned to EDMA3 Event 22
EDMA3_DRV_HW_CHANNEL_EVENT_23  Channel assigned to EDMA3 Event 23
EDMA3_DRV_HW_CHANNEL_EVENT_24  Channel assigned to EDMA3 Event 24
EDMA3_DRV_HW_CHANNEL_EVENT_25  Channel assigned to EDMA3 Event 25
EDMA3_DRV_HW_CHANNEL_EVENT_26  Channel assigned to EDMA3 Event 26
EDMA3_DRV_HW_CHANNEL_EVENT_27  Channel assigned to EDMA3 Event 27
EDMA3_DRV_HW_CHANNEL_EVENT_28  Channel assigned to EDMA3 Event 28
EDMA3_DRV_HW_CHANNEL_EVENT_29  Channel assigned to EDMA3 Event 29
EDMA3_DRV_HW_CHANNEL_EVENT_30  Channel assigned to EDMA3 Event 30
EDMA3_DRV_HW_CHANNEL_EVENT_31  Channel assigned to EDMA3 Event 31
EDMA3_DRV_HW_CHANNEL_EVENT_32  Channel assigned to EDMA3 Event 32
EDMA3_DRV_HW_CHANNEL_EVENT_33  Channel assigned to EDMA3 Event 33
EDMA3_DRV_HW_CHANNEL_EVENT_34  Channel assigned to EDMA3 Event 34
EDMA3_DRV_HW_CHANNEL_EVENT_35  Channel assigned to EDMA3 Event 35
EDMA3_DRV_HW_CHANNEL_EVENT_36  Channel assigned to EDMA3 Event 36
EDMA3_DRV_HW_CHANNEL_EVENT_37  Channel assigned to EDMA3 Event 37
EDMA3_DRV_HW_CHANNEL_EVENT_38  Channel assigned to EDMA3 Event 38
EDMA3_DRV_HW_CHANNEL_EVENT_39  Channel assigned to EDMA3 Event 39
EDMA3_DRV_HW_CHANNEL_EVENT_40  Channel assigned to EDMA3 Event 40
EDMA3_DRV_HW_CHANNEL_EVENT_41  Channel assigned to EDMA3 Event 41
EDMA3_DRV_HW_CHANNEL_EVENT_42  Channel assigned to EDMA3 Event 42
EDMA3_DRV_HW_CHANNEL_EVENT_43  Channel assigned to EDMA3 Event 43
EDMA3_DRV_HW_CHANNEL_EVENT_44  Channel assigned to EDMA3 Event 44
EDMA3_DRV_HW_CHANNEL_EVENT_45  Channel assigned to EDMA3 Event 45
EDMA3_DRV_HW_CHANNEL_EVENT_46  Channel assigned to EDMA3 Event 46
EDMA3_DRV_HW_CHANNEL_EVENT_47  Channel assigned to EDMA3 Event 47
EDMA3_DRV_HW_CHANNEL_EVENT_48  Channel assigned to EDMA3 Event 48
EDMA3_DRV_HW_CHANNEL_EVENT_49  Channel assigned to EDMA3 Event 49
EDMA3_DRV_HW_CHANNEL_EVENT_50  Channel assigned to EDMA3 Event 50
EDMA3_DRV_HW_CHANNEL_EVENT_51  Channel assigned to EDMA3 Event 51
EDMA3_DRV_HW_CHANNEL_EVENT_52  Channel assigned to EDMA3 Event 52
EDMA3_DRV_HW_CHANNEL_EVENT_53  Channel assigned to EDMA3 Event 53
EDMA3_DRV_HW_CHANNEL_EVENT_54  Channel assigned to EDMA3 Event 54
EDMA3_DRV_HW_CHANNEL_EVENT_55  Channel assigned to EDMA3 Event 55
EDMA3_DRV_HW_CHANNEL_EVENT_56  Channel assigned to EDMA3 Event 56
EDMA3_DRV_HW_CHANNEL_EVENT_57  Channel assigned to EDMA3 Event 57
EDMA3_DRV_HW_CHANNEL_EVENT_58  Channel assigned to EDMA3 Event 58
EDMA3_DRV_HW_CHANNEL_EVENT_59  Channel assigned to EDMA3 Event 59
EDMA3_DRV_HW_CHANNEL_EVENT_60  Channel assigned to EDMA3 Event 60
EDMA3_DRV_HW_CHANNEL_EVENT_61  Channel assigned to EDMA3 Event 61
EDMA3_DRV_HW_CHANNEL_EVENT_62  Channel assigned to EDMA3 Event 62
EDMA3_DRV_HW_CHANNEL_EVENT_63  Channel assigned to EDMA3 Event 63

enum EDMA3_DRV_OptField

OPT Field Offset.

Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set.

Enumerator:
EDMA3_DRV_OPT_FIELD_SAM  Source addressing mode (INCR / FIFO) (Bit 0)
EDMA3_DRV_OPT_FIELD_DAM  Destination addressing mode (INCR / FIFO) (Bit 1)
EDMA3_DRV_OPT_FIELD_SYNCDIM  Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2)
EDMA3_DRV_OPT_FIELD_STATIC  The STATIC field PaRAM set is static/non-static? (Bit 3)
EDMA3_DRV_OPT_FIELD_FWID  FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10)
EDMA3_DRV_OPT_FIELD_TCCMODE  Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11)
EDMA3_DRV_OPT_FIELD_TCC  Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17)
EDMA3_DRV_OPT_FIELD_TCINTEN  Transfer complete interrupt enable/disable. (Bit 20)
EDMA3_DRV_OPT_FIELD_ITCINTEN  Intermediate transfer complete interrupt enable/disable. (Bit 21)
EDMA3_DRV_OPT_FIELD_TCCHEN  Transfer complete chaining enable/disable (Bit 22)
EDMA3_DRV_OPT_FIELD_ITCCHEN  Intermediate transfer completion chaining enable/disable (Bit 23)

enum EDMA3_DRV_AddrMode

EDMA Addressing modes.

The EDMA3 TC supports two addressing modes

  1. Increment transfer
  2. FIFO transfer

The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register.

Enumerator:
EDMA3_DRV_ADDR_MODE_INCR  Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
EDMA3_DRV_ADDR_MODE_FIFO  FIFO mode. Source addressing within an array wraps around upon reaching FIFO width.

enum EDMA3_DRV_SyncType

EDMA Transfer Synchronization type.

Two types of Synchronization of transfers are possible

  1. A Synchronized
  2. AB Syncronized

A Sync

  1. Each Array is submitted as one TR
  2. (BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)
  3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)

  • AB Sync
    1. Each Frame is submitted as one TR
    2. Only CCNT number of sync events are needed to completely service a PaRAM set
    3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)

Note:
ABC sync transfers can be achieved logically by chaining multiple AB sync transfers
Enumerator:
EDMA3_DRV_SYNC_A  A-synchronized. Each event triggers the transfer of a single array of ACNT bytes
EDMA3_DRV_SYNC_AB  AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes

enum EDMA3_DRV_StaticMode

True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted.

Enumerator:
EDMA3_DRV_STATIC_DIS  PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers
EDMA3_DRV_STATIC_EN  PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.

enum EDMA3_DRV_FifoWidth

EDMA3 FIFO width.

The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode.

Enumerator:
EDMA3_DRV_W8BIT  FIFO width is 8-bit.
EDMA3_DRV_W16BIT  FIFO width is 16-bit.
EDMA3_DRV_W32BIT  FIFO width is 32-bit.
EDMA3_DRV_W64BIT  FIFO width is 64-bit.
EDMA3_DRV_W128BIT  FIFO width is 128-bit.
EDMA3_DRV_W256BIT  FIFO width is 256-bit.

enum EDMA3_DRV_TccMode

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation.

Enumerator:
EDMA3_DRV_TCCMODE_NORMAL  A transfer is considered completed after transfer of data
EDMA3_DRV_TCCMODE_EARLY  A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.

enum EDMA3_DRV_TcintEn

Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_TCINTEN_DIS  Transfer complete interrupt is disabled
EDMA3_DRV_TCINTEN_EN  Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_ItcintEn

Intermediate Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_ITCINTEN_DIS  Intermediate Transfer complete interrupt is disabled
EDMA3_DRV_ITCINTEN_EN  Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_TcchEn

Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_TCCHEN_DIS  Transfer complete chaining is disabled
EDMA3_DRV_TCCHEN_EN  Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_ItcchEn

Intermediate Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_ITCCHEN_DIS  Intermediate Transfer complete chaining is disabled
EDMA3_DRV_ITCCHEN_EN  Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_TrigMode

EDMA Trigger Mode Selection.

Use this enum to select the EDMA trigger mode while enabling the EDMA transfer

Enumerator:
EDMA3_DRV_TRIG_MODE_MANUAL  Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH).
EDMA3_DRV_TRIG_MODE_QDMA  Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered).
EDMA3_DRV_TRIG_MODE_EVENT  Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request.
EDMA3_DRV_TRIG_MODE_NONE  Used to specify the trigger mode NONE

enum EDMA3_DRV_PaRAMEntry

PaRAM Set Entry type.

Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:
EDMA3_DRV_PARAM_ENTRY_OPT  The OPT field (Offset Address 0x0 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC  The SRC field (Offset Address 0x4 Bytes)
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT  The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
EDMA3_DRV_PARAM_ENTRY_DST  The DST field (Offset Address 0xC Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX  The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD  The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX  The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
EDMA3_DRV_PARAM_ENTRY_CCNT  The (CCNT+RSVD) field (Offset Address 0x1C Bytes)

enum EDMA3_DRV_PaRAMField

PaRAM Set Field type.

Use this enum to set or get any of the PaRAM set fields

Enumerator:
EDMA3_DRV_PARAM_FIELD_OPT  OPT field of PaRAM Set
EDMA3_DRV_PARAM_FIELD_SRCADDR  Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_ACNT  Number of bytes in each Array (ACNT).
EDMA3_DRV_PARAM_FIELD_BCNT  Number of Arrays in each Frame (BCNT).
EDMA3_DRV_PARAM_FIELD_DESTADDR  Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_SRCBIDX  Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_DESTBIDX  Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_LINKADDR  Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD  Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
EDMA3_DRV_PARAM_FIELD_SRCCIDX  Index between consecutive frames of a Source Block (SRCCIDX).
EDMA3_DRV_PARAM_FIELD_DESTCIDX  Index between consecutive frames of a Dest Block (DSTCIDX).
EDMA3_DRV_PARAM_FIELD_CCNT  Number of Frames in a block (CCNT).

enum EDMA3_DRV_IoctlCmd

EDMA3 Driver IOCTL commands.

Enumerator:
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION  PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

For all other values, it will return error.

By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION  To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., unsigned short isParamClearingDone; cmdArg =

enum EDMA3_DRV_Tc_Err

TC Error Enablers.

Use this enum to enable/disable the specific EDMA3 Transfer Controller Interrupts.

Enumerator:
EDMA3_DRV_TC_ERR_BUSERR_DIS  Interrupt disable for bus error
EDMA3_DRV_TC_ERR_BUSERR_EN  Interrupt enable for bus error
EDMA3_DRV_TC_ERR_TRERR_DIS  Interrupt disable for transfer request error
EDMA3_DRV_TC_ERR_TRERR_EN  Interrupt enable for transfer request error
EDMA3_DRV_TC_ERR_MMRAERR_DIS  Interrupt disable for MMR address error
EDMA3_DRV_TC_ERR_MMRAERR_EN  Interrupt enable for MMR address error
EDMA3_DRV_TC_ERR_DIS  Disable all TC error interrupts
EDMA3_DRV_TC_ERR_EN  Enable all TC error interrupts

Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by  doxygen 1.5.5