Internal Interface Definition for EDMA3 Driver


Data Structures

struct  EDMA3_DRV_ChBoundResources
 EDMA3 Channel-Bound resources. More...

Modules

 Boundary Values
 Object Maintenance

Defines

#define EDMA3_DRV_OPT_SAM_CLR_MASK   (~EDMA3_CCRL_OPT_SAM_MASK)
#define EDMA3_DRV_OPT_SAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
#define EDMA3_DRV_OPT_DAM_CLR_MASK   (~EDMA3_CCRL_OPT_DAM_MASK)
#define EDMA3_DRV_OPT_DAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK   (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype)   (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
#define EDMA3_DRV_OPT_STATIC_CLR_MASK   (~EDMA3_CCRL_OPT_STATIC_MASK)
#define EDMA3_DRV_OPT_STATIC_SET_MASK(en)   (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
#define EDMA3_DRV_OPT_FWID_CLR_MASK   (~EDMA3_CCRL_OPT_FWID_MASK)
#define EDMA3_DRV_OPT_FWID_SET_MASK(width)   (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK   (~EDMA3_CCRL_OPT_TCCMODE_MASK)
#define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early)   (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
#define EDMA3_DRV_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc)   (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCINTEN_MASK)
#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten)   (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten)   (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCCHEN_MASK)
#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen)   (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)   (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)   ((mode)&1u)
#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)   (((mode)&(1u<<1u))>>1u)
#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)   (((synctype)&(1u<<2u))>>2u)
#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)   (((en)&(1u<<3u))>>3u)
#define EDMA3_DRV_OPT_FWID_GET_MASK(width)   (((width)&(0x7u<<8u))>>8u)
#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)   (((early)&(1u<<11u))>>11u)
#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)   (((tcc)&(0x3fu<<12u))>>12u)
#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)   (((tcinten)&(1u<<20u))>>20u)
#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)   (((tcchen)&(1u<<22u))>>22u)
#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)   (((itcchen)&(1u<<23u))>>23u)
#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)   (~(0x7u<<(((chNum)%8u)*4u)))
#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << (((chNum)%8u)*4u))
#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)   (~(0x7u<<((chNum)*4u)))
#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
#define EDMA3_DRV_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)   (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
#define EDMA3_DRV_ACNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_CCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNTRELD_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_SRCBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_SRCCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_QPRIORITY_MAX_VAL   (7u)
#define EDMA3_DRV_QPRIORITY_MIN_VAL   (0u)

Enumerations

enum  EDMA3_DRV_ChannelType {
  EDMA3_DRV_CHANNEL_TYPE_NONE,
  EDMA3_DRV_CHANNEL_TYPE_DMA = 1,
  EDMA3_DRV_CHANNEL_TYPE_QDMA = 2,
  EDMA3_DRV_CHANNEL_TYPE_LINK = 3
}
 EDMA3 Channel Type. More...

Detailed Description

Include EDMA3 Driver header file

Documentation of the Internal Interface of EDMA3 Driver

Define Documentation

#define EDMA3_DRV_ACNT_MAX_VAL   (0xFFFFu)

Max value of ACnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_BCNT_MAX_VAL   (0xFFFFu)

Max value of BCnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_BCNTRELD_MAX_VAL   (0xFFFFu)

Max value of BCntReld

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_CCNT_MAX_VAL   (0xFFFFu)

Max value of CCnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_DMAQNUM_CLR_MASK ( chNum   )     (~(0x7u<<(((chNum)%8u)*4u)))

DMAQNUM bits Clear

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_DMAQNUM_SET_MASK ( chNum,
queNum   )     ((0x7u & (queNum)) << (((chNum)%8u)*4u))

DMAQNUM bits Set

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_DSTBIDX_MAX_VAL   (0x7FFF)

Max value of DestBIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTBIDX_MIN_VAL   (-32768)

Min value of DestBIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTCIDX_MAX_VAL   (0x7FFF)

Max value of DestCIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTCIDX_MIN_VAL   (-32768)

Min value of DestCIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_OPT_DAM_CLR_MASK   (~EDMA3_CCRL_OPT_DAM_MASK)

OPT-DAM bit Clear

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_DAM_GET_MASK ( mode   )     (((mode)&(1u<<1u))>>1u)

OPT-DAM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_DAM_SET_MASK ( mode   )     (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)

OPT-DAM bit Set

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_FWID_CLR_MASK   (~EDMA3_CCRL_OPT_FWID_MASK)

OPT-FWID bitfield Clear

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_FWID_GET_MASK ( width   )     (((width)&(0x7u<<8u))>>8u)

OPT-FWID bitfield Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_FWID_SET_MASK ( width   )     (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)

OPT-FWID bitfield Set

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCCHEN_MASK)

OPT-ITCCHEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK ( itcchen   )     (((itcchen)&(1u<<23u))>>23u)

OPT-ITCCHEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK ( itcchen   )     (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)

OPT-ITCCHEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCINTEN_MASK)

OPT-ITCINTEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK ( itcinten   )     (((itcinten)&(1u<<21u))>>21u)

OPT-ITCINTEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK ( itcinten   )     (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)

OPT-ITCINTEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_SAM_CLR_MASK   (~EDMA3_CCRL_OPT_SAM_MASK)

Parameter RAM Set field OPT bit-field defines OPT-SAM bit Clear

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_SAM_GET_MASK ( mode   )     ((mode)&1u)

OPT-SAM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_SAM_SET_MASK ( mode   )     (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)

OPT-SAM bit Set

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_STATIC_CLR_MASK   (~EDMA3_CCRL_OPT_STATIC_MASK)

OPT-STATIC bit Clear

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_STATIC_GET_MASK ( en   )     (((en)&(1u<<3u))>>3u)

OPT-STATIC bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_STATIC_SET_MASK ( en   )     (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)

OPT-STATIC bit Set

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK   (~EDMA3_CCRL_OPT_SYNCDIM_MASK)

OPT-SYNCDIM bit Clear

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK ( synctype   )     (((synctype)&(1u<<2u))>>2u)

OPT-SYNCDIM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK ( synctype   )     (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)

OPT-SYNCDIM bit Set

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)

OPT-TCC bitfield Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCC_GET_MASK ( tcc   )     (((tcc)&(0x3fu<<12u))>>12u)

OPT-TCC bitfield Get

Referenced by EDMA3_DRV_getOptField(), and EDMA3_DRV_linkChannel().

#define EDMA3_DRV_OPT_TCC_SET_MASK ( tcc   )     (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)

OPT-TCC bitfield Set

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCCHEN_MASK)

OPT-TCCHEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

#define EDMA3_DRV_OPT_TCCHEN_GET_MASK ( tcchen   )     (((tcchen)&(1u<<22u))>>22u)

OPT-TCCHEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCCHEN_SET_MASK ( tcchen   )     (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)

OPT-TCCHEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK   (~EDMA3_CCRL_OPT_TCCMODE_MASK)

OPT-TCCMODE bit Clear

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCMODE_GET_MASK ( early   )     (((early)&(1u<<11u))>>11u)

OPT-TCCMODE bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCCMODE_SET_MASK ( early   )     (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)

OPT-TCCMODE bit Set

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCINTEN_MASK)

OPT-TCINTEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCINTEN_GET_MASK ( tcinten   )     (((tcinten)&(1u<<20u))>>20u)

OPT-TCINTEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCINTEN_SET_MASK ( tcinten   )     (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)

OPT-TCINTEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)

QCHMAP-TrigWord bitfield Clear

Referenced by EDMA3_DRV_setQdmaTrigWord().

#define EDMA3_DRV_QCH_TRWORD_SET_MASK ( paRAMId   )     (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)

QCHMAP-TrigWord bitfield Set

Referenced by EDMA3_DRV_setQdmaTrigWord().

#define EDMA3_DRV_QDMAQNUM_CLR_MASK ( chNum   )     (~(0x7u<<((chNum)*4u)))

QDMAQNUM bits Clear

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_QDMAQNUM_SET_MASK ( chNum,
queNum   )     ((0x7u & (queNum)) << ((chNum)*4u))

QDMAQNUM bits Set

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_QPRIORITY_MAX_VAL   (7u)

Max value of Queue Priority

Referenced by EDMA3_DRV_setEvtQPriority().

#define EDMA3_DRV_QPRIORITY_MIN_VAL   (0u)

Min value of Queue Priority

#define EDMA3_DRV_SRCBIDX_MAX_VAL   (0x7FFF)

Max value of SrcBIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCBIDX_MIN_VAL   (-32768)

Min value of SrcBIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCCIDX_MAX_VAL   (0x7FFF)

Max value of SrcCIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCCIDX_MIN_VAL   (-32768)

Min value of SrcCIdx

Referenced by EDMA3_DRV_setSrcIndex().

Enumeration Type Documentation

enum EDMA3_DRV_ChannelType

EDMA3 Channel Type.

Enumerator:
EDMA3_DRV_CHANNEL_TYPE_NONE  Invalid Channel
EDMA3_DRV_CHANNEL_TYPE_DMA  DMA Channel
EDMA3_DRV_CHANNEL_TYPE_QDMA  QDMA Channel
EDMA3_DRV_CHANNEL_TYPE_LINK  LINK Channel

Generated on Tue Jul 7 19:18:48 2009 for EDMA3 Driver by  doxygen 1.5.9