61 #define IRQN_COMMAND_DONE 0
62 #define IRQN_LAST_COMMAND_DONE 1
63 #define IRQN_FG_COMMAND_DONE 2
64 #define IRQN_LAST_FG_COMMAND_DONE 3
65 #define IRQN_TX_DONE 4
67 #define IRQN_TX_CTRL 6
68 #define IRQN_TX_CTRL_ACK 7
69 #define IRQN_TX_CTRL_ACK_ACK 8
70 #define IRQN_TX_RETRANS 9
71 #define IRQN_TX_ENTRY_DONE 10
72 #define IRQN_TX_BUFFER_CHANGED 11
74 #define IRQN_RX_NOK 17
75 #define IRQN_RX_IGNORED 18
76 #define IRQN_RX_EMPTY 19
77 #define IRQN_RX_CTRL 20
78 #define IRQN_RX_CTRL_ACK 21
79 #define IRQN_RX_BUF_FULL 22
80 #define IRQN_RX_ENTRY_DONE 23
81 #define IRQN_RX_DATA_WRITTEN 24
82 #define IRQN_RX_N_DATA_WRITTEN 25
83 #define IRQN_RX_ABORTED 26
84 #define IRQN_RX_COLLISION_DETECTED 27
85 #define IRQN_SYNTH_NO_LOCK 28
86 #define IRQN_MODULES_UNLOCKED 29
87 #define IRQN_BOOT_DONE 30
89 #define IRQN_INTERNAL_ERROR 31
91 #define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
92 #define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
93 #define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
94 #define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
96 #define IRQ_TX_DONE (1U << IRQN_TX_DONE)
97 #define IRQ_TX_ACK (1U << IRQN_TX_ACK)
98 #define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
99 #define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
100 #define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
101 #define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
103 #define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
104 #define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
106 #define IRQ_RX_OK (1U << IRQN_RX_OK)
107 #define IRQ_RX_NOK (1U << IRQN_RX_NOK)
108 #define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
109 #define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
110 #define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
111 #define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
112 #define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
113 #define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
114 #define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
115 #define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
116 #define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
117 #define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED)
118 #define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
119 #define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
120 #define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
121 #define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
129 #define CMDSTA_Pending 0x00
130 #define CMDSTA_Done 0x01
132 #define CMDSTA_IllegalPointer 0x81
133 #define CMDSTA_UnknownCommand 0x82
134 #define CMDSTA_UnknownDirCommand 0x83
135 #define CMDSTA_ContextError 0x85
137 #define CMDSTA_SchedulingError 0x86
139 #define CMDSTA_ParError 0x87
141 #define CMDSTA_QueueError 0x88
143 #define CMDSTA_QueueBusy 0x89
153 #define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
156 #define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
159 #define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
169 #define TRIG_ABSTIME 2
170 #define TRIG_REL_SUBMIT 3
171 #define TRIG_REL_START 4
172 #define TRIG_REL_PREVSTART 5
173 #define TRIG_REL_FIRSTSTART 6
174 #define TRIG_REL_PREVEND 7
175 #define TRIG_REL_EVT1 8
176 #define TRIG_REL_EVT2 9
177 #define TRIG_EXTERNAL 10
178 #define TRIG_PAST_BM 0x80
185 #define COND_ALWAYS 0
187 #define COND_STOP_ON_FALSE 2
188 #define COND_STOP_ON_TRUE 3
190 #define COND_SKIP_ON_FALSE 4
192 #define COND_SKIP_ON_TRUE 5
204 #define PENDING 0x0001
205 #define ACTIVE 0x0002
206 #define SKIPPED 0x0003
207 #define DONE_OK 0x0400
211 #define DONE_COUNTDOWN 0x0401
212 #define DONE_RXERR 0x0402
213 #define DONE_TIMEOUT 0x0403
214 #define DONE_STOPPED 0x0404
215 #define DONE_ABORT 0x0405
216 #define DONE_FAILED 0x0406
217 #define ERROR_PAST_START 0x0800
221 #define ERROR_START_TRIG 0x0801
222 #define ERROR_CONDITION 0x0802
223 #define ERROR_PAR 0x0803
224 #define ERROR_POINTER 0x0804
225 #define ERROR_CMDID 0x0805
226 #define ERROR_WRONG_BG 0x0806
228 #define ERROR_NO_SETUP 0x0807
229 #define ERROR_NO_FS 0x0808
230 #define ERROR_SYNTH_PROG 0x0809
231 #define ERROR_TXUNF 0x080A
232 #define ERROR_RXOVF 0x080B
233 #define ERROR_NO_RX 0x080C
234 #define ERROR_PENDING 0x080D
241 #define DATA_ENTRY_TYPE_GEN 0
242 #define DATA_ENTRY_TYPE_MULTI 1
243 #define DATA_ENTRY_TYPE_PTR 2
244 #define DATA_ENTRY_TYPE_PARTIAL 3
250 #define DATA_ENTRY_PENDING 0
251 #define DATA_ENTRY_ACTIVE 1
252 #define DATA_ENTRY_BUSY 2
253 #define DATA_ENTRY_FINISHED 3
254 #define DATA_ENTRY_UNFINISHED 4
262 #define ADI_VAL_MASK(addr, mask, value) \
263 (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
264 ((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
265 #define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
267 #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
269 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
270 #define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
272 (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
273 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
274 #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
276 (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
277 #define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
279 (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
280 (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
283 #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
284 #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
286 (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
287 #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
289 ((uint32_t)(val) << 16))
290 #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
292 (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
293 #define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
294 #define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
295 ((uint32_t)(length) << 16) | (1U << 30))
296 #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
297 ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
298 #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
299 ((uint32_t)(length) << 16) | (3U << 30))
300 #define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \
301 (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \
302 (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
303 #define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
304 (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
305 (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
306 (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
307 (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
308 (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
309 (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
310 (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
311 (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
312 0x09) << 4)) // Use illegal value for illegal address range
313 #define END_OVERRIDE 0xFFFFFFFF
318 #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
319 #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
322 #define LOWORD(value) ((value) & 0xFFFF)
323 #define HIWORD(value) ((value) >> 16)
uint8_t * pCurrEntry
Pointer to the data queue entry to be used, NULL for an empty queue.
uint8_t * pLastEntry
Pointer to the last entry in the queue, NULL for a circular queue.
uint32_t ratmr_t
Type definition for RAT.
Type definition for a data queue.