CC13xx Driver Library
cpu.h
Go to the documentation of this file.
1 /******************************************************************************
2 * Filename: cpu.h
3 * Revised: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015)
4 * Revision: 44151
5 *
6 * Description: Defines and prototypes for the CPU instruction wrapper
7 * functions.
8 *
9 * Copyright (c) 2015, Texas Instruments Incorporated
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1) Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2) Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
23 * be used to endorse or promote products derived from this software without
24 * specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 ******************************************************************************/
39 
40 //*****************************************************************************
41 //
46 //
47 //*****************************************************************************
48 
49 #ifndef __CPU_H__
50 #define __CPU_H__
51 
52 //*****************************************************************************
53 //
54 // If building with a C++ compiler, make all of the definitions in this header
55 // have a C binding.
56 //
57 //*****************************************************************************
58 #ifdef __cplusplus
59 extern "C"
60 {
61 #endif
62 
63 #include <stdbool.h>
64 #include <stdint.h>
65 #include <inc/hw_types.h>
66 
67 //*****************************************************************************
68 //
69 // Support for DriverLib in ROM:
70 // This section renames all functions that are not "static inline", so that
71 // calling these functions will default to implementation in flash. At the end
72 // of this file a second renaming will change the defaults to implementation in
73 // ROM for available functions.
74 //
75 // To force use of the implementation in flash, e.g. for debugging:
76 // - Globally: Define DRIVERLIB_NOROM at project level
77 // - Per function: Use prefix "NOROM_" when calling the function
78 //
79 //*****************************************************************************
80 #if !defined(DOXYGEN)
81  #define CPUcpsid NOROM_CPUcpsid
82  #define CPUprimask NOROM_CPUprimask
83  #define CPUcpsie NOROM_CPUcpsie
84  #define CPUbasepriGet NOROM_CPUbasepriGet
85  #define CPUdelay NOROM_CPUdelay
86 #endif
87 
88 //*****************************************************************************
89 //
90 // API Functions and prototypes
91 //
92 //*****************************************************************************
93 
94 //*****************************************************************************
95 //
102 //
103 //*****************************************************************************
104 extern uint32_t CPUcpsid(void);
105 
106 //*****************************************************************************
107 //
116 //
117 //*****************************************************************************
118 extern uint32_t CPUprimask(void);
119 
120 //*****************************************************************************
121 //
128 //
129 //*****************************************************************************
130 extern uint32_t CPUcpsie(void);
131 
132 //*****************************************************************************
133 //
140 //
141 //*****************************************************************************
142 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
143 __STATIC_INLINE void
144 CPUwfi(void)
145 {
146  //
147  // Wait for the next interrupt.
148  //
149  __asm(" wfi\n");
150 }
151 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
152 __asm __STATIC_INLINE void
153 CPUwfi(void)
154 {
155  //
156  // Wait for the next interrupt.
157  //
158  wfi;
159  bx lr
160 }
161 #elif defined(__TI_COMPILER_VERSION__)
162 __STATIC_INLINE void
163 CPUwfi(void)
164 {
165  //
166  // Wait for the next interrupt.
167  //
168  __asm(" wfi\n");
169 }
170 #else
171 __STATIC_INLINE void __attribute__((always_inline))
172 CPUwfi(void)
173 {
174  //
175  // Wait for the next interrupt.
176  //
177  __asm(" wfi\n");
178 }
179 #endif
180 
181 //*****************************************************************************
182 //
189 //
190 //*****************************************************************************
191 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
192 __STATIC_INLINE void
193 CPUwfe(void)
194 {
195  //
196  // Wait for the next event.
197  //
198  __asm(" wfe\n");
199 }
200 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
201 __asm __STATIC_INLINE void
202 CPUwfe(void)
203 {
204  //
205  // Wait for the next event.
206  //
207  wfe;
208  bx lr
209 }
210 #elif defined(__TI_COMPILER_VERSION__)
211 __STATIC_INLINE void
212 CPUwfe(void)
213 {
214  //
215  // Wait for the next event.
216  //
217  __asm(" wfe\n");
218 }
219 #else
220 __STATIC_INLINE void __attribute__((always_inline))
221 CPUwfe(void)
222 {
223  //
224  // Wait for the next event.
225  //
226  __asm(" wfe\n");
227 }
228 #endif
229 
230 //*****************************************************************************
231 //
238 //
239 //*****************************************************************************
240 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
241 __STATIC_INLINE void
242 CPUsev(void)
243 {
244  //
245  // Send event.
246  //
247  __asm(" sev\n");
248 }
249 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
250 __asm __STATIC_INLINE void
251 CPUsev(void)
252 {
253  //
254  // Send event.
255  //
256  sev;
257  bx lr
258 }
259 #elif defined(__TI_COMPILER_VERSION__)
260 __STATIC_INLINE void
261 CPUsev(void)
262 {
263  //
264  // Send event.
265  //
266  __asm(" sev\n");
267 }
268 #else
269 __STATIC_INLINE void __attribute__((always_inline))
270 CPUsev(void)
271 {
272  //
273  // Send event.
274  //
275  __asm(" sev\n");
276 }
277 #endif
278 
279 
280 //*****************************************************************************
281 //
290 //
291 //*****************************************************************************
292 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
293 __STATIC_INLINE void
294 CPUbasepriSet(uint32_t ui32NewBasepri)
295 {
296  //
297  // Set the BASEPRI register.
298  //
299  __asm(" msr BASEPRI, r0\n");
300 }
301 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
302 __asm __STATIC_INLINE void
303 CPUbasepriSet(uint32_t ui32NewBasepri)
304 {
305  //
306  // Set the BASEPRI register.
307  //
308  msr BASEPRI, r0;
309  bx lr
310 }
311 #elif defined(__TI_COMPILER_VERSION__)
312 __STATIC_INLINE void
313 CPUbasepriSet(uint32_t ui32NewBasepri)
314 {
315  //
316  // Set the BASEPRI register.
317  //
318  __asm(" msr BASEPRI, r0\n");
319 }
320 #else
321 #pragma GCC diagnostic push
322 #pragma GCC diagnostic ignored "-Wattributes"
323 __STATIC_INLINE void __attribute__ ((naked))
324 CPUbasepriSet(uint32_t ui32NewBasepri)
325 {
326  //
327  // Set the BASEPRI register.
328  //
329  __asm(" msr BASEPRI, r0\n"
330  " bx lr\n");
331 }
332 #pragma GCC diagnostic pop
333 #endif
334 
335 //*****************************************************************************
336 //
343 //
344 //*****************************************************************************
345 extern uint32_t CPUbasepriGet(void);
346 
347 //*****************************************************************************
348 //
360 //
361 //*****************************************************************************
362 extern void CPUdelay(uint32_t ui32Count);
363 
364 //*****************************************************************************
365 //
366 // Support for DriverLib in ROM:
367 // Redirect to implementation in ROM when available.
368 //
369 //*****************************************************************************
370 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
371  #include <driverlib/rom.h>
372  #ifdef ROM_CPUcpsid
373  #undef CPUcpsid
374  #define CPUcpsid ROM_CPUcpsid
375  #endif
376  #ifdef ROM_CPUprimask
377  #undef CPUprimask
378  #define CPUprimask ROM_CPUprimask
379  #endif
380  #ifdef ROM_CPUcpsie
381  #undef CPUcpsie
382  #define CPUcpsie ROM_CPUcpsie
383  #endif
384  #ifdef ROM_CPUbasepriGet
385  #undef CPUbasepriGet
386  #define CPUbasepriGet ROM_CPUbasepriGet
387  #endif
388  #ifdef ROM_CPUdelay
389  #undef CPUdelay
390  #define CPUdelay ROM_CPUdelay
391  #endif
392 #endif
393 
394 //*****************************************************************************
395 //
396 // Mark the end of the C bindings section for C++ compilers.
397 //
398 //*****************************************************************************
399 #ifdef __cplusplus
400 }
401 #endif
402 
403 #endif // __CPU_H__
404 
405 //*****************************************************************************
406 //
410 //
411 //*****************************************************************************
uint32_t CPUprimask(void)
Get the current interrupt state.
Definition: cpu.c:146
static void CPUbasepriSet(uint32_t ui32NewBasepri)
Update the interrupt priority disable level.
Definition: cpu.h:294
static void CPUwfi(void)
Wait for interrupt.
Definition: cpu.h:144
uint32_t CPUcpsid(void)
Disable all external interrupts.
Definition: cpu.c:68
static void CPUwfe(void)
Wait for event.
Definition: cpu.h:193
uint32_t CPUcpsie(void)
Enable all external interrupts.
Definition: cpu.c:220
static void CPUsev(void)
Send event.
Definition: cpu.h:242
uint32_t CPUbasepriGet(void)
Get the interrupt priority disable level.
Definition: cpu.c:298
void CPUdelay(uint32_t ui32Count)
Provide a small delay.
Definition: cpu.c:372