dm6437_hal_pci.h File Reference

---

Detailed Description

Hardware Abstraction Layer for PC-DM64LC PCI interface. Defines interfaces to initialize the PCI interface.

============================================================================

Path:

/gpp/inc/sys/arch/DM6437/

Version:

1.65.02.09 ============================================================================

Copyright:

Copyright (C) 2002-2012, Texas Instruments Incorporated - https://www.ti.com/

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================

#include <dsplink.h>
#include <dm6437_hal.h>

Include dependency graph for dm6437_hal_pci.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	DM6437_devRegs_tag
struct	DM6437_pllRegs_tag
struct	DM6437_ddrRegs
struct	DM6437_pscRegs_tag
struct	DM6437_paramEntry_tags
struct	DM6437_edmaRegs_tag
struct	DM6437_pciRegs_tag
struct	DM6437_HalPciPhyObj_tag
Defines
#define	NUM_BARS   6
	Number of BAR registers. ============================================================================.
#define	PCI33_DMA_MAXTHROUGHPUT   132u
	Maximum through put of PCI interface. ============================================================================.
#define	DDR_REGS_BAR_NO   1u
	Number for the BAR register used for DDR EMIF register access. ============================================================================.
#define	CFG_REGS_BAR_NO   2u
	Number for the BAR register used for register access. ============================================================================.
#define	RWMEM_BAR_NO   4u
	Number for the BAR register used for L1DRAM access. ============================================================================.
#define	SHMEM_BAR_NO   5u
	Number for the BAR register used for shared memory access. ============================================================================.
#define	LPSC_GEM   39u
	Module number for GEM. ============================================================================.
#define	LPSC_EDMA_TPCC   2u
	Module number for EDMA TPCC. ============================================================================.
#define	LPSC_EDMA_TPTC0   3u
	Module number for EDMA TPTC0. ============================================================================.
#define	LPSC_EDMA_TPTC1   4u
	Module number for EDMA TPTC1. ============================================================================.
#define	LPSC_EDMA_TPTC2   5u
	Module number for EDMA TPTC2. ============================================================================.
#define	LPSC_DDR   13u
	Module number for DDR. ============================================================================.
#define	DM6437_PCIMEM_BASE   0x30000000u
	PCI memory base in GEM memory space. ============================================================================.
#define	DM6437_DEVREG_BASE   0x40000u
	Base address of Device config registers. ============================================================================.
#define	DM6437_PLL0REG_BASE   0x40800u
	Base address of PLL0 registers. ============================================================================.
#define	DM6437_PLL1REG_BASE   0x40C00u
	Base address of PLL1 registers. ============================================================================.
#define	DM6437_EDMAREG_BASE   0x0u
	Base address of EDMA registers. ============================================================================.
#define	DM6437_DDRREG_BASE   0x0u
	Base address of DDR PHY registers. ============================================================================.
#define	DM6437_PSCREG_BASE   0x41000u
	Base address of PSC registers. ============================================================================.
#define	DM6437_PCIREG_BASE   0x1A000u
	Base address of PCI backend registers. ============================================================================.
#define	DM6437_SOFTINT0_MASK   0x01000000u
	Mask for generating soft int0 (DSP->GPP) ============================================================================.
#define	DM6437_SOFTINT1_MASK   0x02000000u
	Mask for generating soft int1 (GPP->DSP) ============================================================================.
#define	DM6437_LRESET_MASK   0x00000100u
	Mask for reseting/releasing GEM. ============================================================================.
#define	DM6437_INTSTATUS_MASK   0x00080000u
	Bitmask for Interrupt status (DSP->GPP) ============================================================================.
#define	DM6437_BOOTCMPLTBC_MASK   0x00000001u
	Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================.
#define	DM6437_PCIADLEN   0x00800000u
	Length each segment of addressable PCI Space.. ============================================================================.
#define	DM6437_PCIADWRBITMASK   0xFF800000u
	Mask indicating writeable bits in PCI Address Window registers. ============================================================================.
#define	DM6437_PAGEWRBITMASK   0xFF800000u
	Mask indicating writeable bits in PCI Base Address Mask Register5. ============================================================================.
Typedefs
DM6437_devRegs
Register Overlay Structure for Device config registers. ============================================================================ ============================================================================
typedef struct DM6437_devRegs_tag	DM6437_devRegs
DM6437_pllRegs
Register Overlay Structure for PLL. ============================================================================ ============================================================================
typedef struct DM6437_pllRegs_tag	DM6437_pllRegs
DM6437_pscRegs
Register Overlay Structure for PSC. ============================================================================ ============================================================================
typedef struct DM6437_pscRegs_tag	DM6437_pscRegs
DM6437_paramEntry
Register Overlay Structure for PARAMENTRY. ============================================================================ ============================================================================
typedef struct DM6437_paramEntry_tags	DM6437_paramEntry
DM6437_edmaRegs
Register Overlay Structure for EDMA. ============================================================================ ============================================================================
typedef struct DM6437_edmaRegs_tag	DM6437_edmaRegs
DM6437_pciRegs
PCI Back end register overlay structure. ============================================================================ ============================================================================
typedef struct DM6437_pciRegs_tag	DM6437_pciRegs

---

Define Documentation

#define NUM_BARS   6

Number of BAR registers. ============================================================================.

============================================================================

Constant:

NUM_BARS

#define PCI33_DMA_MAXTHROUGHPUT   132u

Maximum through put of PCI interface. ============================================================================.

============================================================================

Constant:

PCI33_DMA_MAXTHROUGHPUT

#define DDR_REGS_BAR_NO   1u

Number for the BAR register used for DDR EMIF register access. ============================================================================.

============================================================================

Constant:

DDR_REGS_BAR_NO

#define CFG_REGS_BAR_NO   2u

Number for the BAR register used for register access. ============================================================================.

============================================================================

Constant:

CFG_REGS_BAR_NO

#define RWMEM_BAR_NO   4u

Number for the BAR register used for L1DRAM access. ============================================================================.

============================================================================

Constant:

RWMEM_BAR_NO

#define SHMEM_BAR_NO   5u

Number for the BAR register used for shared memory access. ============================================================================.

============================================================================

Constant:

SHMEM_BAR_NO

#define LPSC_GEM   39u

Module number for GEM. ============================================================================.

============================================================================

Constant:

LPSC_GEM

#define LPSC_EDMA_TPCC   2u

Module number for EDMA TPCC. ============================================================================.

============================================================================

Constant:

LPSC_EDMA_TPCC

#define LPSC_EDMA_TPTC0   3u

Module number for EDMA TPTC0. ============================================================================.

============================================================================

Constant:

LPSC_EDMA_TPTC0

#define LPSC_EDMA_TPTC1   4u

Module number for EDMA TPTC1. ============================================================================.

============================================================================

Constant:

LPSC_EDMA_TPTC1

#define LPSC_EDMA_TPTC2   5u

Module number for EDMA TPTC2. ============================================================================.

============================================================================

Constant:

LPSC_EDMA_TPTC2

#define LPSC_DDR   13u

Module number for DDR. ============================================================================.

============================================================================

Constant:

LPSC_DDR

#define DM6437_PCIMEM_BASE   0x30000000u

PCI memory base in GEM memory space. ============================================================================.

============================================================================

Constant:

DM6437_PCIMEM_BASE

#define DM6437_DEVREG_BASE   0x40000u

Base address of Device config registers. ============================================================================.

============================================================================

Constant:

DM6437_DEVREG_BASE

#define DM6437_PLL0REG_BASE   0x40800u

Base address of PLL0 registers. ============================================================================.

============================================================================

Constant:

DM6437_PLLREG_BASE

#define DM6437_PLL1REG_BASE   0x40C00u

Base address of PLL1 registers. ============================================================================.

============================================================================

Constant:

DM6437_PLLREG_BASE

#define DM6437_EDMAREG_BASE   0x0u

Base address of EDMA registers. ============================================================================.

============================================================================

Constant:

DM6437_EDMAREG_BASE

#define DM6437_DDRREG_BASE   0x0u

Base address of DDR PHY registers. ============================================================================.

============================================================================

Constant:

DM6437_DDRREG_BASE

#define DM6437_PSCREG_BASE   0x41000u

Base address of PSC registers. ============================================================================.

============================================================================

Constant:

DM6437_PSCREG_BASE

#define DM6437_PCIREG_BASE   0x1A000u

Base address of PCI backend registers. ============================================================================.

============================================================================

Constant:

DM6437_PCIREG_BASE

#define DM6437_SOFTINT0_MASK   0x01000000u

Mask for generating soft int0 (DSP->GPP) ============================================================================.

============================================================================

Constant:

DM6437_SOFTINT0_MASK

#define DM6437_SOFTINT1_MASK   0x02000000u

Mask for generating soft int1 (GPP->DSP) ============================================================================.

============================================================================

Constant:

DM6437_SOFTINT1_MASK

#define DM6437_LRESET_MASK   0x00000100u

Mask for reseting/releasing GEM. ============================================================================.

============================================================================

Constant:

DM6437_LRESET_MASK

#define DM6437_INTSTATUS_MASK   0x00080000u

Bitmask for Interrupt status (DSP->GPP) ============================================================================.

============================================================================

Constant:

DM6437_INTSTATUS_MASK

#define DM6437_BOOTCMPLTBC_MASK   0x00000001u

Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================.

============================================================================

Constant:

DM6437_BOOTCMPLTBC_MASK

#define DM6437_PCIADLEN   0x00800000u

Length each segment of addressable PCI Space.. ============================================================================.

============================================================================

Constant:

DM6437_PCIADLEN

#define DM6437_PCIADWRBITMASK   0xFF800000u

Mask indicating writeable bits in PCI Address Window registers. ============================================================================.

============================================================================

Constant:

DM6437_PCIADWRBITMASK

#define DM6437_PAGEWRBITMASK   0xFF800000u

Mask indicating writeable bits in PCI Base Address Mask Register5. ============================================================================.

============================================================================

Constant:

DM6437_PAGEWRBITMASK

---

Typedef Documentation

typedef struct DM6437_devRegs_tag DM6437_devRegs

typedef struct DM6437_pllRegs_tag DM6437_pllRegs

typedef struct DM6437_pscRegs_tag DM6437_pscRegs

typedef struct DM6437_paramEntry_tags DM6437_paramEntry

typedef struct DM6437_edmaRegs_tag DM6437_edmaRegs

typedef struct DM6437_pciRegs_tag DM6437_pciRegs