J722S Interrupt Management Device Descriptions¶
Introduction¶
This chapter provides information on the Interrupt Management devices in the J722S SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.
Interrupt Router Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J722S Device IDs these are the valid Interrupt Router device IDs.
| Interrupt Router Device Name | Interrupt Router Device ID |
|---|---|
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 |
MAIN_GPIOMUX_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 0 | J722S_DEV_GPIO0 | gpio | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 1 | J722S_DEV_GPIO0 | gpio | 1 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 2 | J722S_DEV_GPIO0 | gpio | 2 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 3 | J722S_DEV_GPIO0 | gpio | 3 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 4 | J722S_DEV_GPIO0 | gpio | 4 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 5 | J722S_DEV_GPIO0 | gpio | 5 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 6 | J722S_DEV_GPIO0 | gpio | 6 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 7 | J722S_DEV_GPIO0 | gpio | 7 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 8 | J722S_DEV_GPIO0 | gpio | 8 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 9 | J722S_DEV_GPIO0 | gpio | 9 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 10 | J722S_DEV_GPIO0 | gpio | 10 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 11 | J722S_DEV_GPIO0 | gpio | 11 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 12 | J722S_DEV_GPIO0 | gpio | 12 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 13 | J722S_DEV_GPIO0 | gpio | 13 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 14 | J722S_DEV_GPIO0 | gpio | 14 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 15 | J722S_DEV_GPIO0 | gpio | 15 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 16 | J722S_DEV_GPIO0 | gpio | 16 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 17 | J722S_DEV_GPIO0 | gpio | 17 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 18 | J722S_DEV_GPIO0 | gpio | 18 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 19 | J722S_DEV_GPIO0 | gpio | 19 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 20 | J722S_DEV_GPIO0 | gpio | 20 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 21 | J722S_DEV_GPIO0 | gpio | 21 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 22 | J722S_DEV_GPIO0 | gpio | 22 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 23 | J722S_DEV_GPIO0 | gpio | 23 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 24 | J722S_DEV_GPIO0 | gpio | 24 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 25 | J722S_DEV_GPIO0 | gpio | 25 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 26 | J722S_DEV_GPIO0 | gpio | 26 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 27 | J722S_DEV_GPIO0 | gpio | 27 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 28 | J722S_DEV_GPIO0 | gpio | 28 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 29 | J722S_DEV_GPIO0 | gpio | 29 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 30 | J722S_DEV_GPIO0 | gpio | 30 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 31 | J722S_DEV_GPIO0 | gpio | 31 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 32 | J722S_DEV_GPIO0 | gpio | 32 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 33 | J722S_DEV_GPIO0 | gpio | 33 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 34 | J722S_DEV_GPIO0 | gpio | 34 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 35 | J722S_DEV_GPIO0 | gpio | 35 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 36 | J722S_DEV_GPIO0 | gpio | 36 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 37 | J722S_DEV_GPIO0 | gpio | 37 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 38 | J722S_DEV_GPIO0 | gpio | 38 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 39 | J722S_DEV_GPIO0 | gpio | 39 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 40 | J722S_DEV_GPIO0 | gpio | 40 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 41 | J722S_DEV_GPIO0 | gpio | 41 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 42 | J722S_DEV_GPIO0 | gpio | 42 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 43 | J722S_DEV_GPIO0 | gpio | 43 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 44 | J722S_DEV_GPIO0 | gpio | 44 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 45 | J722S_DEV_GPIO0 | gpio | 45 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 46 | J722S_DEV_GPIO0 | gpio | 46 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 47 | J722S_DEV_GPIO0 | gpio | 47 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 48 | J722S_DEV_GPIO0 | gpio | 48 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 49 | J722S_DEV_GPIO0 | gpio | 49 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 50 | J722S_DEV_GPIO0 | gpio | 50 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 51 | J722S_DEV_GPIO0 | gpio | 51 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 52 | J722S_DEV_GPIO0 | gpio | 52 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 53 | J722S_DEV_GPIO0 | gpio | 53 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 54 | J722S_DEV_GPIO0 | gpio | 54 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 55 | J722S_DEV_GPIO0 | gpio | 55 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 56 | J722S_DEV_GPIO0 | gpio | 56 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 57 | J722S_DEV_GPIO0 | gpio | 57 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 58 | J722S_DEV_GPIO0 | gpio | 58 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 59 | J722S_DEV_GPIO0 | gpio | 59 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 60 | J722S_DEV_GPIO0 | gpio | 60 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 61 | J722S_DEV_GPIO0 | gpio | 61 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 62 | J722S_DEV_GPIO0 | gpio | 62 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 63 | J722S_DEV_GPIO0 | gpio | 63 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 64 | J722S_DEV_GPIO0 | gpio | 64 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 65 | J722S_DEV_GPIO0 | gpio | 65 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 66 | J722S_DEV_GPIO0 | gpio | 66 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 67 | J722S_DEV_GPIO0 | gpio | 67 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 68 | J722S_DEV_GPIO0 | gpio | 68 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 69 | J722S_DEV_GPIO0 | gpio | 69 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 70 | J722S_DEV_GPIO0 | gpio | 70 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 71 | J722S_DEV_GPIO0 | gpio | 71 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 72 | J722S_DEV_GPIO0 | gpio | 72 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 73 | J722S_DEV_GPIO0 | gpio | 73 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 74 | J722S_DEV_GPIO0 | gpio | 74 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 75 | J722S_DEV_GPIO0 | gpio | 75 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 76 | J722S_DEV_GPIO0 | gpio | 76 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 77 | J722S_DEV_GPIO0 | gpio | 77 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 78 | J722S_DEV_GPIO0 | gpio | 78 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 79 | J722S_DEV_GPIO0 | gpio | 79 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 80 | J722S_DEV_GPIO0 | gpio | 80 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 81 | J722S_DEV_GPIO0 | gpio | 81 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 82 | J722S_DEV_GPIO0 | gpio | 82 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 83 | J722S_DEV_GPIO0 | gpio | 83 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 84 | J722S_DEV_GPIO0 | gpio | 84 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 85 | J722S_DEV_GPIO0 | gpio | 85 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 86 | J722S_DEV_GPIO0 | gpio | 86 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 87 | J722S_DEV_GPIO0 | gpio | 87 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 88 | J722S_DEV_GPIO0 | gpio | 88 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 89 | J722S_DEV_GPIO0 | gpio | 89 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 90 | J722S_DEV_GPIO1 | gpio | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 91 | J722S_DEV_GPIO1 | gpio | 1 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 92 | J722S_DEV_GPIO1 | gpio | 2 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 93 | J722S_DEV_GPIO1 | gpio | 3 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 94 | J722S_DEV_GPIO1 | gpio | 4 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 95 | J722S_DEV_GPIO1 | gpio | 5 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 96 | J722S_DEV_GPIO1 | gpio | 6 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 97 | J722S_DEV_GPIO1 | gpio | 7 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 98 | J722S_DEV_GPIO1 | gpio | 8 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 99 | J722S_DEV_GPIO1 | gpio | 9 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 100 | J722S_DEV_GPIO1 | gpio | 10 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 101 | J722S_DEV_GPIO1 | gpio | 11 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 102 | J722S_DEV_GPIO1 | gpio | 12 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 103 | J722S_DEV_GPIO1 | gpio | 13 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 104 | J722S_DEV_GPIO1 | gpio | 14 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 105 | J722S_DEV_GPIO1 | gpio | 15 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 106 | J722S_DEV_GPIO1 | gpio | 16 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 107 | J722S_DEV_GPIO1 | gpio | 17 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 108 | J722S_DEV_GPIO1 | gpio | 18 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 109 | J722S_DEV_GPIO1 | gpio | 19 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 110 | J722S_DEV_GPIO1 | gpio | 20 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 111 | J722S_DEV_GPIO1 | gpio | 21 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 112 | J722S_DEV_GPIO1 | gpio | 22 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 113 | J722S_DEV_GPIO1 | gpio | 23 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 114 | J722S_DEV_GPIO1 | gpio | 24 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 115 | J722S_DEV_GPIO1 | gpio | 25 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 116 | J722S_DEV_GPIO1 | gpio | 26 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 117 | J722S_DEV_GPIO1 | gpio | 27 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 118 | J722S_DEV_GPIO1 | gpio | 28 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 119 | J722S_DEV_GPIO1 | gpio | 29 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 120 | J722S_DEV_GPIO1 | gpio | 30 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 121 | J722S_DEV_GPIO1 | gpio | 31 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 122 | J722S_DEV_GPIO1 | gpio | 32 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 123 | J722S_DEV_GPIO1 | gpio | 33 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 124 | J722S_DEV_GPIO1 | gpio | 34 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 125 | J722S_DEV_GPIO1 | gpio | 35 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 126 | J722S_DEV_GPIO1 | gpio | 36 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 127 | J722S_DEV_GPIO1 | gpio | 37 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 128 | J722S_DEV_GPIO1 | gpio | 38 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 129 | J722S_DEV_GPIO1 | gpio | 39 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 130 | J722S_DEV_GPIO1 | gpio | 40 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 131 | J722S_DEV_GPIO1 | gpio | 41 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 132 | J722S_DEV_GPIO1 | gpio | 42 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 133 | J722S_DEV_GPIO1 | gpio | 43 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 134 | J722S_DEV_GPIO1 | gpio | 44 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 135 | J722S_DEV_GPIO1 | gpio | 45 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 136 | J722S_DEV_GPIO1 | gpio | 46 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 137 | J722S_DEV_GPIO1 | gpio | 47 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 138 | J722S_DEV_GPIO1 | gpio | 48 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 139 | J722S_DEV_GPIO1 | gpio | 49 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 140 | J722S_DEV_GPIO1 | gpio | 50 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 141 | J722S_DEV_GPIO1 | gpio | 51 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 142 | J722S_DEV_GPIO1 | gpio | 52 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 143 | J722S_DEV_GPIO1 | gpio | 53 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 144 | J722S_DEV_GPIO1 | gpio | 54 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 145 | J722S_DEV_GPIO1 | gpio | 55 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 146 | J722S_DEV_GPIO1 | gpio | 56 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 147 | J722S_DEV_GPIO1 | gpio | 57 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 148 | J722S_DEV_GPIO1 | gpio | 58 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 149 | J722S_DEV_GPIO1 | gpio | 59 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 150 | J722S_DEV_GPIO1 | gpio | 60 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 151 | J722S_DEV_GPIO1 | gpio | 61 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 152 | J722S_DEV_GPIO1 | gpio | 62 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 153 | J722S_DEV_GPIO1 | gpio | 63 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 154 | J722S_DEV_GPIO1 | gpio | 64 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 155 | J722S_DEV_GPIO1 | gpio | 65 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 156 | J722S_DEV_GPIO1 | gpio | 66 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 157 | J722S_DEV_GPIO1 | gpio | 67 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 158 | J722S_DEV_GPIO1 | gpio | 68 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 159 | J722S_DEV_GPIO1 | gpio | 69 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 160 | J722S_DEV_GPIO1 | gpio | 70 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 161 | J722S_DEV_GPIO1 | gpio | 71 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 162 | J722S_DEV_TIMER0 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 163 | J722S_DEV_TIMER1 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 164 | J722S_DEV_TIMER2 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 165 | J722S_DEV_TIMER3 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 166 | J722S_DEV_TIMER4 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 167 | J722S_DEV_TIMER5 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 168 | J722S_DEV_TIMER6 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 169 | J722S_DEV_TIMER7 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 170 | J722S_DEV_MCU_TIMER0 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 171 | J722S_DEV_MCU_TIMER1 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 172 | J722S_DEV_MCU_TIMER2 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 173 | J722S_DEV_MCU_TIMER3 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 174 | J722S_DEV_WKUP_TIMER0 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 175 | J722S_DEV_WKUP_TIMER1 | timer_pwm | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 176 | J722S_DEV_GPIO0 | gpio | 90 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 177 | J722S_DEV_GPIO0 | gpio | 91 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 178 | J722S_DEV_I2C4 | pointrpend | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 179 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 180 | J722S_DEV_GPIO1 | gpio_bank | 72 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 181 | J722S_DEV_GPIO1 | gpio_bank | 73 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 182 | J722S_DEV_GPIO1 | gpio_bank | 74 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 183 | J722S_DEV_GPIO1 | gpio_bank | 75 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 184 | J722S_DEV_GPIO1 | gpio_bank | 76 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 185 | J722S_DEV_GPIO1 | gpio_bank | 77 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 186 | J722S_DEV_MCASP3 | rec_intr_pend | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 187 | J722S_DEV_MCASP3 | xmit_intr_pend | 1 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 188 | J722S_DEV_MCASP4 | rec_intr_pend | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 189 | J722S_DEV_MCASP4 | xmit_intr_pend | 1 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 190 | J722S_DEV_GPIO0 | gpio_bank | 92 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 191 | J722S_DEV_GPIO0 | gpio_bank | 93 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 192 | J722S_DEV_GPIO0 | gpio_bank | 94 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 193 | J722S_DEV_GPIO0 | gpio_bank | 95 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 194 | J722S_DEV_GPIO0 | gpio_bank | 96 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 195 | J722S_DEV_GPIO0 | gpio_bank | 97 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 196 | J722S_DEV_DMPAC0 | dmpac_level | 0 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 197 | J722S_DEV_DMPAC0 | dmpac_level | 1 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 198 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 199 | Use TRM - Not managed by TISCI |
MAIN_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 0 | J722S_DEV_GICSS0 | spi | 32 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 32 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 0 | J722S_DEV_C7X256V0_CLEC | gic_spi | 32 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 32 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 0 | J722S_DEV_HSM0 | nvic | 208 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 1 | J722S_DEV_GICSS0 | spi | 33 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 33 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 1 | J722S_DEV_C7X256V0_CLEC | gic_spi | 33 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 33 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 1 | J722S_DEV_HSM0 | nvic | 209 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 2 | J722S_DEV_GICSS0 | spi | 34 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 34 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 2 | J722S_DEV_C7X256V0_CLEC | gic_spi | 34 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 34 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 2 | J722S_DEV_HSM0 | nvic | 210 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 3 | J722S_DEV_GICSS0 | spi | 35 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 35 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 3 | J722S_DEV_C7X256V0_CLEC | gic_spi | 35 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 35 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 3 | J722S_DEV_HSM0 | nvic | 211 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 4 | J722S_DEV_GICSS0 | spi | 36 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 36 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 4 | J722S_DEV_C7X256V0_CLEC | gic_spi | 36 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 36 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 4 | J722S_DEV_HSM0 | nvic | 212 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 5 | J722S_DEV_GICSS0 | spi | 37 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 37 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 5 | J722S_DEV_C7X256V0_CLEC | gic_spi | 37 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 37 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 5 | J722S_DEV_HSM0 | nvic | 213 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 6 | J722S_DEV_GICSS0 | spi | 38 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 38 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 6 | J722S_DEV_C7X256V0_CLEC | gic_spi | 38 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 38 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 6 | J722S_DEV_HSM0 | nvic | 214 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 7 | J722S_DEV_GICSS0 | spi | 39 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 39 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 7 | J722S_DEV_C7X256V0_CLEC | gic_spi | 39 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 39 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 7 | J722S_DEV_HSM0 | nvic | 215 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 8 | J722S_DEV_GICSS0 | spi | 40 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 40 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 8 | J722S_DEV_C7X256V0_CLEC | gic_spi | 40 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 40 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 9 | J722S_DEV_GICSS0 | spi | 41 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 41 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 9 | J722S_DEV_C7X256V0_CLEC | gic_spi | 41 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 41 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 10 | J722S_DEV_GICSS0 | spi | 42 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 42 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 10 | J722S_DEV_C7X256V0_CLEC | gic_spi | 42 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 42 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 11 | J722S_DEV_GICSS0 | spi | 43 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 43 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 11 | J722S_DEV_C7X256V0_CLEC | gic_spi | 43 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 43 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 12 | J722S_DEV_GICSS0 | spi | 44 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 44 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 12 | J722S_DEV_C7X256V0_CLEC | gic_spi | 44 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 44 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 13 | J722S_DEV_GICSS0 | spi | 45 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 45 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 13 | J722S_DEV_C7X256V0_CLEC | gic_spi | 45 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 45 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 14 | J722S_DEV_GICSS0 | spi | 46 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 46 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 14 | J722S_DEV_C7X256V0_CLEC | gic_spi | 46 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 46 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 15 | J722S_DEV_GICSS0 | spi | 47 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 47 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 15 | J722S_DEV_C7X256V0_CLEC | gic_spi | 47 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 47 | |||
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 16 | J722S_DEV_R5FSS0_CORE0 | intr | 104 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 17 | J722S_DEV_R5FSS0_CORE0 | intr | 105 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 18 | J722S_DEV_R5FSS0_CORE0 | intr | 106 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 19 | J722S_DEV_R5FSS0_CORE0 | intr | 107 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 20 | J722S_DEV_R5FSS0_CORE0 | intr | 56 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 21 | J722S_DEV_R5FSS0_CORE0 | intr | 57 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 22 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 24 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 23 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 25 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 24 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 16 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 25 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 17 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 26 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 18 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 27 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 19 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 28 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 20 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 29 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 21 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 30 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 22 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 31 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 23 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 32 | J722S_DEV_R5FSS0_CORE0 | intr | 58 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 33 | J722S_DEV_R5FSS0_CORE0 | intr | 59 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 34 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 32 |
| J722S_DEV_MAIN_GPIOMUX_INTROUTER0 | 3 | 35 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 33 |
WKUP_MCU_GPIOMUX_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 0 | J722S_DEV_MCU_GPIO0 | gpio | 0 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 1 | J722S_DEV_MCU_GPIO0 | gpio | 1 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 2 | J722S_DEV_MCU_GPIO0 | gpio | 2 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 3 | J722S_DEV_MCU_GPIO0 | gpio | 3 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 4 | J722S_DEV_MCU_GPIO0 | gpio | 4 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 5 | J722S_DEV_MCU_GPIO0 | gpio | 5 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 6 | J722S_DEV_MCU_GPIO0 | gpio | 6 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 7 | J722S_DEV_MCU_GPIO0 | gpio | 7 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 8 | J722S_DEV_MCU_GPIO0 | gpio | 8 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 9 | J722S_DEV_MCU_GPIO0 | gpio | 9 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 10 | J722S_DEV_MCU_GPIO0 | gpio | 10 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 11 | J722S_DEV_MCU_GPIO0 | gpio | 11 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 12 | J722S_DEV_MCU_GPIO0 | gpio | 12 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 13 | J722S_DEV_MCU_GPIO0 | gpio | 13 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 14 | J722S_DEV_MCU_GPIO0 | gpio | 14 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 15 | J722S_DEV_MCU_GPIO0 | gpio | 15 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 16 | J722S_DEV_MCU_GPIO0 | gpio | 16 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 17 | J722S_DEV_MCU_GPIO0 | gpio | 17 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 18 | J722S_DEV_MCU_GPIO0 | gpio | 18 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 19 | J722S_DEV_MCU_GPIO0 | gpio | 19 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 20 | J722S_DEV_MCU_GPIO0 | gpio | 20 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 21 | J722S_DEV_MCU_GPIO0 | gpio | 21 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 22 | J722S_DEV_MCU_GPIO0 | gpio | 22 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 23 | J722S_DEV_MCU_GPIO0 | gpio | 23 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 24 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 25 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 26 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 27 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 28 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 29 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 30 | J722S_DEV_MCU_GPIO0 | gpio_bank | 24 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 31 | J722S_DEV_MCU_GPIO0 | gpio_bank | 25 |
WKUP_MCU_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 0 | J722S_DEV_GICSS0 | spi | 104 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 104 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 0 | J722S_DEV_C7X256V0_CLEC | gic_spi | 104 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 104 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 1 | J722S_DEV_GICSS0 | spi | 105 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 105 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 1 | J722S_DEV_C7X256V0_CLEC | gic_spi | 105 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 105 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 2 | J722S_DEV_GICSS0 | spi | 106 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 106 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 2 | J722S_DEV_C7X256V0_CLEC | gic_spi | 106 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 106 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 3 | J722S_DEV_GICSS0 | spi | 107 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 107 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 3 | J722S_DEV_C7X256V0_CLEC | gic_spi | 107 |
| J722S_DEV_C7X256V1_CLEC | gic_spi | 107 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 4 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 104 |
| J722S_DEV_HSM0 | nvic | 78 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 5 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 105 |
| J722S_DEV_HSM0 | nvic | 79 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 6 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 106 |
| J722S_DEV_HSM0 | nvic | 80 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 7 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 107 |
| J722S_DEV_HSM0 | nvic | 81 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 8 | J722S_DEV_WKUP_ESM0 | esm_pls_event0 | 88 |
| J722S_DEV_WKUP_ESM0 | esm_pls_event1 | 92 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 8 | J722S_DEV_WKUP_ESM0 | esm_pls_event2 | 96 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 9 | J722S_DEV_WKUP_ESM0 | esm_pls_event0 | 89 |
| J722S_DEV_WKUP_ESM0 | esm_pls_event1 | 93 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 9 | J722S_DEV_WKUP_ESM0 | esm_pls_event2 | 97 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 10 | J722S_DEV_WKUP_ESM0 | esm_pls_event0 | 90 |
| J722S_DEV_WKUP_ESM0 | esm_pls_event1 | 94 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 10 | J722S_DEV_WKUP_ESM0 | esm_pls_event2 | 98 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 11 | J722S_DEV_WKUP_ESM0 | esm_pls_event0 | 91 |
| J722S_DEV_WKUP_ESM0 | esm_pls_event1 | 95 | |||
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 11 | J722S_DEV_WKUP_ESM0 | esm_pls_event2 | 99 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 12 | J722S_DEV_R5FSS0_CORE0 | intr | 32 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 13 | J722S_DEV_R5FSS0_CORE0 | intr | 33 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 14 | J722S_DEV_R5FSS0_CORE0 | intr | 60 |
| J722S_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 | 5 | 15 | J722S_DEV_R5FSS0_CORE0 | intr | 61 |
TIMESYNC_EVENT_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 0 | J722S_DEV_TIMER0 | timer_pwm | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 1 | J722S_DEV_TIMER1 | timer_pwm | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 2 | J722S_DEV_TIMER2 | timer_pwm | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 3 | J722S_DEV_TIMER3 | timer_pwm | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 4 | J722S_DEV_PCIE0 | pcie_cpts_genf0 | 1 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 5 | J722S_DEV_PCIE0 | pcie_cpts_hw1_push | 2 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 6 | J722S_DEV_PCIE0 | pcie_cpts_sync | 3 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 7 | J722S_DEV_PCIE0 | pcie_ptm_valid_pulse | 4 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 8 | J722S_DEV_EPWM0 | epwm_synco_o | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 9 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 10 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 11 | J722S_DEV_WKUP_GTC0 | gtc_push_event | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 12 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 13 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 14 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 15 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 16 | J722S_DEV_CPSW0 | cpts_genf0 | 1 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 17 | J722S_DEV_CPSW0 | cpts_genf1 | 2 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 18 | J722S_DEV_CPSW0 | cpts_sync | 3 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 19 | Use TRM - Not managed by TISCI |
TIMESYNC_EVENT_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 0 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 8 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 1 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 9 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 2 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 10 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 3 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 11 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 4 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 12 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 5 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 13 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 6 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 14 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 7 | J722S_DEV_DMASS0_INTAGGR_0 | intaggr_levi_pend | 15 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 8 | J722S_DEV_PCIE0 | pcie_cpts_hw2_push | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 9 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 10 | J722S_DEV_CPSW0 | cpts_hw1_push | 0 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 11 | J722S_DEV_CPSW0 | cpts_hw2_push | 1 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 12 | J722S_DEV_CPSW0 | cpts_hw3_push | 2 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 13 | J722S_DEV_CPSW0 | cpts_hw4_push | 3 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 14 | J722S_DEV_CPSW0 | cpts_hw5_push | 4 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 15 | J722S_DEV_CPSW0 | cpts_hw6_push | 5 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 16 | J722S_DEV_CPSW0 | cpts_hw7_push | 6 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 17 | J722S_DEV_CPSW0 | cpts_hw8_push | 7 |
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 18 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 19 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 20 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 21 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 22 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 23 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 24 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_TIMESYNC_EVENT_INTROUTER0 | 6 | 25 | Use TRM - Not managed by TISCI |
Interrupt Aggregator Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J722S Device IDs these are the valid Interrupt Aggregator device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| J722S_DEV_DMASS0_INTAGGR_0 | 28 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 |
Interrupt Aggregator Virtual Interrupts¶
This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| J722S_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 6 |
| J722S_DEV_DMASS0_INTAGGR_0 | 7 to 39 |
| J722S_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 40 to 43 |
| J722S_DEV_DMASS0_INTAGGR_0 | 44 to 135 |
| J722S_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 136 to 139 |
| J722S_DEV_DMASS0_INTAGGR_0 | 140 to 151 |
| J722S_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 152 to 153 |
| J722S_DEV_DMASS0_INTAGGR_0 | 154 to 183 |
| J722S_DEV_DMASS1_INTAGGR_0 | 0 to 39 |
DMASS0_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IA Name | IA Device ID | IA VINT Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 0 | J722S_DEV_GICSS0 | spi | 64 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 64 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 0 | J722S_DEV_C7X256V1_CLEC | gic_spi | 64 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 1 | J722S_DEV_GICSS0 | spi | 65 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 65 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 1 | J722S_DEV_C7X256V1_CLEC | gic_spi | 65 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 2 | J722S_DEV_GICSS0 | spi | 66 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 66 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 2 | J722S_DEV_C7X256V1_CLEC | gic_spi | 66 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 3 | J722S_DEV_GICSS0 | spi | 67 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 67 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 3 | J722S_DEV_C7X256V1_CLEC | gic_spi | 67 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 4 | J722S_DEV_GICSS0 | spi | 68 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 68 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 4 | J722S_DEV_C7X256V1_CLEC | gic_spi | 68 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 5 | J722S_DEV_GICSS0 | spi | 69 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 69 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 5 | J722S_DEV_C7X256V1_CLEC | gic_spi | 69 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 6 | J722S_DEV_GICSS0 | spi | 70 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 70 | |||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 6 | J722S_DEV_C7X256V1_CLEC | gic_spi | 70 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 7 | J722S_DEV_GICSS0 | spi | 71 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 71 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 7 | J722S_DEV_C7X256V1_CLEC | gic_spi | 71 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 8 | J722S_DEV_GICSS0 | spi | 72 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 72 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 8 | J722S_DEV_C7X256V1_CLEC | gic_spi | 72 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 9 | J722S_DEV_GICSS0 | spi | 73 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 73 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 9 | J722S_DEV_C7X256V1_CLEC | gic_spi | 73 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 10 | J722S_DEV_GICSS0 | spi | 74 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 74 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 10 | J722S_DEV_C7X256V1_CLEC | gic_spi | 74 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 11 | J722S_DEV_GICSS0 | spi | 75 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 75 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 11 | J722S_DEV_C7X256V1_CLEC | gic_spi | 75 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 12 | J722S_DEV_GICSS0 | spi | 76 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 76 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 12 | J722S_DEV_C7X256V1_CLEC | gic_spi | 76 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 13 | J722S_DEV_GICSS0 | spi | 77 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 77 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 13 | J722S_DEV_C7X256V1_CLEC | gic_spi | 77 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 14 | J722S_DEV_GICSS0 | spi | 78 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 78 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 14 | J722S_DEV_C7X256V1_CLEC | gic_spi | 78 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 15 | J722S_DEV_GICSS0 | spi | 79 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 79 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 15 | J722S_DEV_C7X256V1_CLEC | gic_spi | 79 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 16 | J722S_DEV_GICSS0 | spi | 80 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 80 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 16 | J722S_DEV_C7X256V1_CLEC | gic_spi | 80 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 17 | J722S_DEV_GICSS0 | spi | 81 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 81 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 17 | J722S_DEV_C7X256V1_CLEC | gic_spi | 81 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 18 | J722S_DEV_GICSS0 | spi | 82 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 82 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 18 | J722S_DEV_C7X256V1_CLEC | gic_spi | 82 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 19 | J722S_DEV_GICSS0 | spi | 83 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 83 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 19 | J722S_DEV_C7X256V1_CLEC | gic_spi | 83 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 20 | J722S_DEV_GICSS0 | spi | 84 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 84 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 20 | J722S_DEV_C7X256V1_CLEC | gic_spi | 84 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 21 | J722S_DEV_GICSS0 | spi | 85 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 85 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 21 | J722S_DEV_C7X256V1_CLEC | gic_spi | 85 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 22 | J722S_DEV_GICSS0 | spi | 86 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 86 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 22 | J722S_DEV_C7X256V1_CLEC | gic_spi | 86 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 23 | J722S_DEV_GICSS0 | spi | 87 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 87 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 23 | J722S_DEV_C7X256V1_CLEC | gic_spi | 87 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 24 | J722S_DEV_GICSS0 | spi | 88 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 88 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 24 | J722S_DEV_C7X256V1_CLEC | gic_spi | 88 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 25 | J722S_DEV_GICSS0 | spi | 89 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 89 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 25 | J722S_DEV_C7X256V1_CLEC | gic_spi | 89 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 26 | J722S_DEV_GICSS0 | spi | 90 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 90 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 26 | J722S_DEV_C7X256V1_CLEC | gic_spi | 90 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 27 | J722S_DEV_GICSS0 | spi | 91 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 91 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 27 | J722S_DEV_C7X256V1_CLEC | gic_spi | 91 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 28 | J722S_DEV_GICSS0 | spi | 92 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 92 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 28 | J722S_DEV_C7X256V1_CLEC | gic_spi | 92 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 29 | J722S_DEV_GICSS0 | spi | 93 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 93 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 29 | J722S_DEV_C7X256V1_CLEC | gic_spi | 93 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 30 | J722S_DEV_GICSS0 | spi | 94 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 94 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 30 | J722S_DEV_C7X256V1_CLEC | gic_spi | 94 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 31 | J722S_DEV_GICSS0 | spi | 95 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 95 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 31 | J722S_DEV_C7X256V1_CLEC | gic_spi | 95 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 32 | J722S_DEV_GICSS0 | spi | 96 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 96 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 32 | J722S_DEV_C7X256V1_CLEC | gic_spi | 96 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 33 | J722S_DEV_GICSS0 | spi | 97 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 97 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 33 | J722S_DEV_C7X256V1_CLEC | gic_spi | 97 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 34 | J722S_DEV_GICSS0 | spi | 98 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 98 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 34 | J722S_DEV_C7X256V1_CLEC | gic_spi | 98 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 35 | J722S_DEV_GICSS0 | spi | 99 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 99 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 35 | J722S_DEV_C7X256V1_CLEC | gic_spi | 99 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 36 | J722S_DEV_GICSS0 | spi | 100 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 100 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 36 | J722S_DEV_C7X256V1_CLEC | gic_spi | 100 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 37 | J722S_DEV_GICSS0 | spi | 101 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 101 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 37 | J722S_DEV_C7X256V1_CLEC | gic_spi | 101 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 38 | J722S_DEV_GICSS0 | spi | 102 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 102 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 38 | J722S_DEV_C7X256V1_CLEC | gic_spi | 102 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 39 | J722S_DEV_GICSS0 | spi | 103 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 103 | |||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 39 | J722S_DEV_C7X256V1_CLEC | gic_spi | 103 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 40 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 64 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 41 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 65 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 42 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 66 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 43 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 67 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 44 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 68 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 45 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 69 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 46 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 70 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 47 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 71 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 48 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 72 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 49 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 73 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 50 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 74 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 51 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 75 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 52 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 76 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 53 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 77 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 54 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 78 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 55 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 79 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 56 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 80 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 57 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 81 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 58 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 82 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 59 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 83 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 60 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 84 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 61 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 85 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 62 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 86 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 63 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 87 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 64 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 88 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 65 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 89 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 66 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 90 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 67 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 91 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 68 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 92 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 69 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 93 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 70 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 94 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 71 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 95 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 72 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 8 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 73 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 9 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 74 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 10 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 75 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 11 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 76 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 12 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 77 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 13 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 78 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 14 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 79 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 15 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 80 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 81 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 82 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 83 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 84 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 16 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 85 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 17 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 86 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 18 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 87 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 19 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 88 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 20 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 89 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 21 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 90 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 22 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 91 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 23 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 92 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 24 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 93 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 25 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 94 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 26 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 95 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 27 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 96 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 28 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 97 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 29 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 98 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 30 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 99 | J722S_DEV_C7X256V0_CLEC | soc_events_in | 31 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 100 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 16 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 101 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 17 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 102 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 18 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 103 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 19 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 104 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 20 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 105 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 21 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 106 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 22 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 107 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 23 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 108 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 24 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 109 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 25 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 110 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 26 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 111 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 27 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 112 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 28 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 113 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 29 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 114 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 30 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 115 | J722S_DEV_C7X256V1_CLEC | soc_events_in | 31 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 116 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 117 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 118 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 119 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 120 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 121 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 122 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 123 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 124 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 125 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 126 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 127 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 128 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 129 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 130 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 131 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 132 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 133 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 134 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 135 | Use TRM - Not managed by TISCI | ||
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 136 | J722S_DEV_HSM0 | nvic | 176 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 137 | J722S_DEV_HSM0 | nvic | 177 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 138 | J722S_DEV_HSM0 | nvic | 178 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 139 | J722S_DEV_HSM0 | nvic | 179 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 140 | J722S_DEV_HSM0 | nvic | 180 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 141 | J722S_DEV_HSM0 | nvic | 181 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 142 | J722S_DEV_HSM0 | nvic | 182 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 143 | J722S_DEV_HSM0 | nvic | 183 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 144 | J722S_DEV_HSM0 | nvic | 184 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 145 | J722S_DEV_HSM0 | nvic | 185 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 146 | J722S_DEV_HSM0 | nvic | 186 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 147 | J722S_DEV_HSM0 | nvic | 187 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 148 | J722S_DEV_HSM0 | nvic | 188 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 149 | J722S_DEV_HSM0 | nvic | 189 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 150 | J722S_DEV_HSM0 | nvic | 190 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 151 | J722S_DEV_HSM0 | nvic | 191 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 152 | J722S_DEV_R5FSS0_CORE0 | intr | 64 |
| J722S_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) | 28 | 153 | J722S_DEV_R5FSS0_CORE0 | intr | 65 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 154 | J722S_DEV_R5FSS0_CORE0 | intr | 66 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 155 | J722S_DEV_R5FSS0_CORE0 | intr | 67 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 156 | J722S_DEV_R5FSS0_CORE0 | intr | 68 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 157 | J722S_DEV_R5FSS0_CORE0 | intr | 69 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 158 | J722S_DEV_R5FSS0_CORE0 | intr | 70 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 159 | J722S_DEV_R5FSS0_CORE0 | intr | 71 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 160 | J722S_DEV_R5FSS0_CORE0 | intr | 72 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 161 | J722S_DEV_R5FSS0_CORE0 | intr | 73 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 162 | J722S_DEV_R5FSS0_CORE0 | intr | 74 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 163 | J722S_DEV_R5FSS0_CORE0 | intr | 75 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 164 | J722S_DEV_R5FSS0_CORE0 | intr | 76 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 165 | J722S_DEV_R5FSS0_CORE0 | intr | 77 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 166 | J722S_DEV_R5FSS0_CORE0 | intr | 78 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 167 | J722S_DEV_R5FSS0_CORE0 | intr | 79 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 168 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 64 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 169 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 65 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 170 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 66 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 171 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 67 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 172 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 68 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 173 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 69 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 174 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 70 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 175 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 71 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 176 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 72 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 177 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 73 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 178 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 74 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 179 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 75 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 180 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 76 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 181 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 77 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 182 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 78 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | 183 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 79 |
DMASS1_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IA Name | IA Device ID | IA VINT Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 0 | J722S_DEV_GICSS0 | spi | 237 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 237 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 0 | J722S_DEV_C7X256V1_CLEC | gic_spi | 237 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 1 | J722S_DEV_GICSS0 | spi | 238 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 238 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 1 | J722S_DEV_C7X256V1_CLEC | gic_spi | 238 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 2 | J722S_DEV_GICSS0 | spi | 239 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 239 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 2 | J722S_DEV_C7X256V1_CLEC | gic_spi | 239 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 3 | J722S_DEV_GICSS0 | spi | 240 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 240 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 3 | J722S_DEV_C7X256V1_CLEC | gic_spi | 240 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 4 | J722S_DEV_GICSS0 | spi | 241 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 241 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 4 | J722S_DEV_C7X256V1_CLEC | gic_spi | 241 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 5 | J722S_DEV_GICSS0 | spi | 242 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 242 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 5 | J722S_DEV_C7X256V1_CLEC | gic_spi | 242 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 6 | J722S_DEV_GICSS0 | spi | 243 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 243 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 6 | J722S_DEV_C7X256V1_CLEC | gic_spi | 243 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 7 | J722S_DEV_GICSS0 | spi | 244 |
| J722S_DEV_C7X256V0_CLEC | gic_spi | 244 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 7 | J722S_DEV_C7X256V1_CLEC | gic_spi | 244 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 8 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 129 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 9 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 130 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 10 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 131 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 11 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 132 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 12 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 150 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 13 | J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 158 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 14 | J722S_DEV_R5FSS0_CORE0 | intr | 158 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 159 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 15 | J722S_DEV_R5FSS0_CORE0 | intr | 159 |
| J722S_DEV_WKUP_R5FSS0_CORE0 | intr | 160 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 16 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 129 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 17 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 130 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 18 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 131 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 19 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 132 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 20 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 150 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 21 | J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 158 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 22 | J722S_DEV_R5FSS0_CORE0 | intr | 160 |
| J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 159 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 23 | J722S_DEV_R5FSS0_CORE0 | intr | 150 |
| J722S_DEV_MCU_R5FSS0_CORE0 | cpu0_intr | 160 | |||
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 24 | J722S_DEV_R5FSS0_CORE0 | intr | 129 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 25 | J722S_DEV_R5FSS0_CORE0 | intr | 130 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 26 | J722S_DEV_R5FSS0_CORE0 | intr | 131 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 27 | J722S_DEV_R5FSS0_CORE0 | intr | 132 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 28 | J722S_DEV_R5FSS0_CORE0 | intr | 138 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 29 | J722S_DEV_R5FSS0_CORE0 | intr | 139 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 30 | J722S_DEV_R5FSS0_CORE0 | intr | 143 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 31 | J722S_DEV_R5FSS0_CORE0 | intr | 144 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 32 | J722S_DEV_R5FSS0_CORE0 | intr | 8 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 33 | J722S_DEV_R5FSS0_CORE0 | intr | 9 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 34 | J722S_DEV_R5FSS0_CORE0 | intr | 10 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 35 | J722S_DEV_R5FSS0_CORE0 | intr | 11 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 36 | J722S_DEV_R5FSS0_CORE0 | intr | 12 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 37 | J722S_DEV_R5FSS0_CORE0 | intr | 13 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 38 | J722S_DEV_R5FSS0_CORE0 | intr | 14 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | 39 | J722S_DEV_R5FSS0_CORE0 | intr | 15 |
Global Events¶
This section describes J722S global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| DMASS0_INTAGGR_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 16 |
| DMASS0_INTAGGR_0 SEVT | 17 to 1535 |
| DMASS0_INTAGGR_0 MEVT | 8192 to 8319 |
| DMASS0_INTAGGR_0 GEVT | 10240 to 10495 |
| DMASS1_INTAGGR_0 SEVT | 12288 to 12503 |
| DMASS1_INTAGGR_0 MEVT | 13312 to 13343 |
| DMASS1_INTAGGR_0 GEVT | 13824 to 13855 |
| DMASS0_INTAGGR_0 LEVT | 32768 to 32799 |
| DMASS0_BCDMA_0 TRIGGER | 50176 to 50339 |
| DMASS1_BCDMA_0 TRIGGER | 51200 to 51279 |
Event-Based Interrupt Source IDs¶
| Device Name | Device ID | Interrupt Source Name | Interrupt Source Index |
|---|---|---|---|
| J722S_DEV_DMASS0_RINGACC_0 | 33 | Ring events | N/A to N/A |
| J722S_DEV_DMASS0_RINGACC_0 | 33 | Ring global error event | N/A |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped pktdma_tx_chan_error events | 4096 to 4124 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped pktdma_tx_flow_completion events | 4608 to 4706 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped pktdma_rx_chan_error events | 5120 to 5143 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped pktdma_rx_flow_completion events | 5632 to 5682 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped pktdma_rx_flow_starvation events | 6144 to 6194 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_chan_error events | 8192 to 8223 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_chan_data_completion events | 8704 to 8735 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_chan_ring_completion events | 9216 to 9247 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_tx_chan_error events | 9728 to 9752 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_tx_chan_data_completion events | 10240 to 10264 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_tx_chan_ring_completion events | 10752 to 10776 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_rx_chan_error events | 11264 to 11288 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_rx_chan_data_completion events | 11776 to 11800 |
| J722S_DEV_DMASS0_INTAGGR_0 | 28 | DMASS0_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events | 12288 to 12312 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_tx_chan_error events | 1536 to 1543 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_tx_chan_data_completion events | 2048 to 2055 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_tx_chan_ring_completion events | 2560 to 2567 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_rx_chan_error events | 3072 to 3103 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_rx_chan_data_completion events | 3584 to 3615 |
| J722S_DEV_DMASS1_INTAGGR_0 | 200 | DMASS1_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events | 4096 to 4127 |