J721S2 Board Configuration Resource Assignment Type Descriptions¶
Introduction¶
This chapter provides information of Board Configuration resource assignment type IDs that are permitted in the J721S2 SoC. The resource type IDs represent J721S2 resources ranges assignable to SoC processing entities (or PEs).
WARNING: System Firmware RM currently supports a maximum of 980 RM board configuration resource assignment ranges on the J721S2 SoC. Sending more entries than the maximum will result in the RM board configuration being NACK’d
Device Name | Device ID (10-bits) | Subtype Name | Subtype ID (6-bits) | Unique Type ID (16-bits) | Resource Range Start | Resource Range Number |
---|---|---|---|---|---|---|
J721S2_DEV_MAIN2MCU_LVL_INTRTR0 | 0x079 | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x1E40 | 0 | 64 |
J721S2_DEV_MAIN2MCU_PLS_INTRTR0 | 0x07A | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x1E80 | 0 | 48 |
J721S2_DEV_TIMESYNC_INTRTR0 | 0x07C | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x1F00 | 0 | 48 |
J721S2_DEV_WKUP_GPIOMUX_INTRTR0 | 0x07D | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x1F40 | 0 | 32 |
J721S2_DEV_GPIOMUX_INTRTR0 | 0x094 | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x2500 | 0 | 64 |
J721S2_DEV_CMPEVENT_INTRTR0 | 0x096 | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x2580 | 0 | 16 |
J721S2_DEV_NAVSS0_BCDMA_0 | 0x0E1 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER | 0x02 | 0x3842 | 50176 | 96 |
RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x3843 | 0 | 1 | ||
RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN | 0x0E | 0x384E | 16 | 32 | ||
RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN | 0x0F | 0x384F | 0 | 16 | ||
RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN | 0x21 | 0x3861 | 0 | 32 | ||
RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN | 0x22 | 0x3862 | 0 | 16 | ||
J721S2_DEV_NAVSS0_INTR_0 | 0x0E3 | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x38C0 | 10 | 174 |
196 | 28 | |||||
228 | 28 | |||||
260 | 28 | |||||
292 | 220 | |||||
J721S2_DEV_NAVSS0_MODSS_INTA_0 | 0x0FE | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x3F8A | 0 | 64 |
RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x3F8D | 20480 | 1024 | ||
J721S2_DEV_NAVSS0_MODSS_INTA_1 | 0x0FF | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x3FCA | 0 | 64 |
RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x3FCD | 22528 | 1024 | ||
J721S2_DEV_NAVSS0_PROXY_0 | 0x100 | RESASG_SUBTYPE_PROXY_PROXIES | 0x00 | 0x4000 | 0 | 64 |
J721S2_DEV_NAVSS0_RINGACC_0 | 0x103 | RESASG_SUBTYPE_RA_ERROR_OES | 0x00 | 0x40C0 | 0 | 1 |
RESASG_SUBTYPE_RA_GP | 0x01 | 0x40C1 | 423 | 551 | ||
RESASG_SUBTYPE_RA_UDMAP_RX | 0x02 | 0x40C2 | 347 | 76 | ||
RESASG_SUBTYPE_RA_UDMAP_TX | 0x03 | 0x40C3 | 6 | 79 | ||
RESASG_SUBTYPE_RA_UDMAP_TX_EXT | 0x04 | 0x40C4 | 85 | 256 | ||
RESASG_SUBTYPE_RA_UDMAP_RX_H | 0x05 | 0x40C5 | 343 | 4 | ||
RESASG_SUBTYPE_RA_UDMAP_RX_UH | 0x06 | 0x40C6 | 341 | 2 | ||
RESASG_SUBTYPE_RA_UDMAP_TX_H | 0x07 | 0x40C7 | 2 | 4 | ||
RESASG_SUBTYPE_RA_UDMAP_TX_UH | 0x08 | 0x40C8 | 0 | 2 | ||
RESASG_SUBTYPE_RA_VIRTID | 0x0A | 0x40CA | 0 | 4096 | ||
RESASG_SUBTYPE_RA_MONITORS | 0x0B | 0x40CB | 0 | 32 | ||
J721S2_DEV_NAVSS0_UDMAP_0 | 0x107 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON | 0x00 | 0x41C0 | 82 | 142 |
RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES | 0x01 | 0x41C1 | 0 | 1 | ||
RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER | 0x02 | 0x41C2 | 49152 | 1024 | ||
RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x41C3 | 0 | 1 | ||
RESASG_SUBTYPE_UDMAP_RX_CHAN | 0x0A | 0x41CA | 6 | 76 | ||
RESASG_SUBTYPE_UDMAP_RX_HCHAN | 0x0B | 0x41CB | 2 | 4 | ||
RESASG_SUBTYPE_UDMAP_RX_UHCHAN | 0x0C | 0x41CC | 0 | 2 | ||
RESASG_SUBTYPE_UDMAP_TX_CHAN | 0x0D | 0x41CD | 6 | 79 | ||
RESASG_SUBTYPE_UDMAP_TX_ECHAN | 0x0E | 0x41CE | 85 | 256 | ||
RESASG_SUBTYPE_UDMAP_TX_HCHAN | 0x0F | 0x41CF | 2 | 4 | ||
RESASG_SUBTYPE_UDMAP_TX_UHCHAN | 0x10 | 0x41D0 | 0 | 2 | ||
J721S2_DEV_NAVSS0_UDMASS_INTA_0 | 0x109 | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x424A | 34 | 222 |
RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x424D | 34 | 4574 | ||
RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES | 0x0F | 0x424F | 1536 | 16 | ||
RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES | 0x10 | 0x4250 | 2048 | 16 | ||
RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES | 0x11 | 0x4251 | 2560 | 16 | ||
RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES | 0x12 | 0x4252 | 3072 | 32 | ||
RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES | 0x13 | 0x4253 | 3584 | 32 | ||
RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES | 0x14 | 0x4254 | 4096 | 32 | ||
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 | 0x10C | RESASG_SUBTYPE_IR_OUTPUT | 0x00 | 0x4300 | 12 | 12 |
36 | 28 | |||||
J721S2_DEV_MCU_NAVSS0_PROXY0 | 0x10F | RESASG_SUBTYPE_PROXY_PROXIES | 0x00 | 0x43C0 | 1 | 63 |
J721S2_DEV_MCU_NAVSS0_RINGACC0 | 0x110 | RESASG_SUBTYPE_RA_ERROR_OES | 0x00 | 0x4400 | 0 | 1 |
RESASG_SUBTYPE_RA_GP | 0x01 | 0x4401 | 96 | 156 | ||
RESASG_SUBTYPE_RA_UDMAP_RX | 0x02 | 0x4402 | 50 | 43 | ||
RESASG_SUBTYPE_RA_UDMAP_TX | 0x03 | 0x4403 | 2 | 44 | ||
RESASG_SUBTYPE_RA_UDMAP_RX_H | 0x05 | 0x4405 | 48 | 2 | ||
RESASG_SUBTYPE_RA_UDMAP_TX_H | 0x07 | 0x4407 | 0 | 2 | ||
RESASG_SUBTYPE_RA_VIRTID | 0x0A | 0x440A | 0 | 4096 | ||
RESASG_SUBTYPE_RA_MONITORS | 0x0B | 0x440B | 0 | 32 | ||
J721S2_DEV_MCU_NAVSS0_UDMAP_0 | 0x111 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON | 0x00 | 0x4440 | 48 | 48 |
RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES | 0x01 | 0x4441 | 0 | 1 | ||
RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER | 0x02 | 0x4442 | 56320 | 256 | ||
RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x4443 | 0 | 1 | ||
RESASG_SUBTYPE_UDMAP_RX_CHAN | 0x0A | 0x444A | 2 | 43 | ||
RESASG_SUBTYPE_UDMAP_RX_HCHAN | 0x0B | 0x444B | 0 | 2 | ||
RESASG_SUBTYPE_UDMAP_TX_CHAN | 0x0D | 0x444D | 2 | 44 | ||
RESASG_SUBTYPE_UDMAP_TX_HCHAN | 0x0F | 0x444F | 0 | 2 | ||
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 0x113 | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x44CA | 22 | 234 |
RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x44CD | 16406 | 1514 | ||
J721S2_DEV_MCU_SA3_SS0_INTAGGR_0 | 0x12C | RESASG_SUBTYPE_IA_VINT | 0x0A | 0x4B0A | 8 | 0 |
RESASG_SUBTYPE_GLOBAL_EVENT_SEVT | 0x0D | 0x4B0D | 100 | 0 | ||
RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES | 0x15 | 0x4B15 | 0 | 1024 | ||
RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES | 0x16 | 0x4B16 | 4096 | 2 | ||
RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES | 0x17 | 0x4B17 | 4608 | 16 | ||
RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES | 0x18 | 0x4B18 | 5120 | 4 | ||
RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES | 0x19 | 0x4B19 | 5632 | 16 | ||
RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES | 0x1A | 0x4B1A | 6144 | 16 | ||
RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES | 0x1B | 0x4B1B | 6656 | 16 | ||
J721S2_DEV_MCU_SA3_SS0_PKTDMA_0 | 0x12D | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG | 0x03 | 0x4B43 | 0 | 1 |
RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN | 0x12 | 0x4B52 | 8 | 0 | ||
RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN | 0x13 | 0x4B53 | 8 | 8 | ||
RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN | 0x18 | 0x4B58 | 16 | 8 | ||
RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN | 0x19 | 0x4B59 | 24 | 0 | ||
RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN | 0x1A | 0x4B5A | 24 | 8 | ||
RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN | 0x1B | 0x4B5B | 24 | 8 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN | 0x25 | 0x4B65 | 1 | 0 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN | 0x26 | 0x4B66 | 1 | 1 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN | 0x2D | 0x4B6D | 1 | 0 | ||
RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN | 0x2E | 0x4B6E | 0 | 8 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN | 0x2F | 0x4B6F | 2 | 0 | ||
RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN | 0x30 | 0x4B70 | 0 | 8 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN | 0x31 | 0x4B71 | 2 | 1 | ||
RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN | 0x32 | 0x4B72 | 8 | 8 | ||
RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN | 0x33 | 0x4B73 | 3 | 1 | ||
RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN | 0x34 | 0x4B74 | 8 | 8 | ||
J721S2_DEV_MCU_SA3_SS0_RINGACC_0 | 0x12E | RESASG_SUBTYPE_RA_ERROR_OES | 0x00 | 0x4B80 | 0 | 1 |
RESASG_SUBTYPE_RA_VIRTID | 0x0A | 0x4B8A | 0 | 4096 |