J7200 Devices Descriptions¶
Introduction¶
This chapter provides information on Device IDs that are permitted in the j7200 SoC. The device IDs represent SoC subsystems that can be modified via DMSC TISCI message APIs. Some Secure, Power, and Resource Management DMSC subsystem TISCI message APIs define a device ID as a parameter allowing a user to specify management of a particular SoC subsystem.
Enumeration of Device IDs¶
| Device ID | Device Name |
|---|---|
| 0 | J7200_DEV_MCU_ADC0 |
| 1 | J7200_DEV_MCU_ADC1 |
| 2 | J7200_DEV_ATL0 |
| 3 | J7200_DEV_COMPUTE_CLUSTER0 |
| 4 | J7200_DEV_A72SS0_CORE0 |
| 5 | J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP |
| 6 | J7200_DEV_COMPUTE_CLUSTER0_CLEC |
| 7 | J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE |
| 8 | J7200_DEV_DDR0 |
| 9 | J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP |
| 10 | J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 |
| 11 | J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 |
| 12 | J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP |
| 13 | J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN |
| 14 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS |
| 17 | J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP |
| 18 | J7200_DEV_MCU_CPSW0 |
| 19 | J7200_DEV_CPSW0 |
| 20 | J7200_DEV_CPT2_AGGR0 |
| 21 | J7200_DEV_CPT2_AGGR1 |
| 22 | J7200_DEV_WKUP_DMSC0 |
| 23 | J7200_DEV_CPT2_AGGR2 |
| 24 | J7200_DEV_MCU_CPT2_AGGR0 |
| 25 | J7200_DEV_CPT2_AGGR3 |
| 26 | J7200_DEV_CPSW_TX_RGMII0 |
| 29 | J7200_DEV_STM0 |
| 30 | J7200_DEV_DCC0 |
| 31 | J7200_DEV_DCC1 |
| 32 | J7200_DEV_DCC2 |
| 33 | J7200_DEV_DCC3 |
| 34 | J7200_DEV_DCC4 |
| 35 | J7200_DEV_MCU_TIMER0 |
| 36 | J7200_DEV_DCC5 |
| 37 | J7200_DEV_DCC6 |
| 39 | J7200_DEV_MAIN0 |
| 40 | J7200_DEV_WKUP_WAKEUP0 |
| 44 | J7200_DEV_MCU_DCC0 |
| 45 | J7200_DEV_MCU_DCC1 |
| 46 | J7200_DEV_MCU_DCC2 |
| 49 | J7200_DEV_TIMER0 |
| 50 | J7200_DEV_TIMER1 |
| 51 | J7200_DEV_TIMER2 |
| 52 | J7200_DEV_TIMER3 |
| 53 | J7200_DEV_TIMER4 |
| 54 | J7200_DEV_TIMER5 |
| 55 | J7200_DEV_TIMER6 |
| 57 | J7200_DEV_TIMER7 |
| 58 | J7200_DEV_TIMER8 |
| 59 | J7200_DEV_TIMER9 |
| 60 | J7200_DEV_TIMER10 |
| 61 | J7200_DEV_GTC0 |
| 62 | J7200_DEV_TIMER11 |
| 63 | J7200_DEV_TIMER12 |
| 64 | J7200_DEV_TIMER13 |
| 65 | J7200_DEV_TIMER14 |
| 66 | J7200_DEV_TIMER15 |
| 67 | J7200_DEV_TIMER16 |
| 68 | J7200_DEV_TIMER17 |
| 69 | J7200_DEV_TIMER18 |
| 70 | J7200_DEV_TIMER19 |
| 71 | J7200_DEV_MCU_TIMER1 |
| 72 | J7200_DEV_MCU_TIMER2 |
| 73 | J7200_DEV_MCU_TIMER3 |
| 74 | J7200_DEV_MCU_TIMER4 |
| 75 | J7200_DEV_MCU_TIMER5 |
| 76 | J7200_DEV_MCU_TIMER6 |
| 77 | J7200_DEV_MCU_TIMER7 |
| 78 | J7200_DEV_MCU_TIMER8 |
| 79 | J7200_DEV_MCU_TIMER9 |
| 80 | J7200_DEV_ECAP0 |
| 81 | J7200_DEV_ECAP1 |
| 82 | J7200_DEV_ECAP2 |
| 83 | J7200_DEV_EHRPWM0 |
| 84 | J7200_DEV_EHRPWM1 |
| 85 | J7200_DEV_EHRPWM2 |
| 86 | J7200_DEV_EHRPWM3 |
| 87 | J7200_DEV_EHRPWM4 |
| 88 | J7200_DEV_EHRPWM5 |
| 89 | J7200_DEV_ELM0 |
| 90 | J7200_DEV_EMIF_DATA_0_VD |
| 91 | J7200_DEV_MMCSD0 |
| 92 | J7200_DEV_MMCSD1 |
| 94 | J7200_DEV_EQEP0 |
| 95 | J7200_DEV_EQEP1 |
| 96 | J7200_DEV_EQEP2 |
| 97 | J7200_DEV_ESM0 |
| 98 | J7200_DEV_MCU_ESM0 |
| 99 | J7200_DEV_WKUP_ESM0 |
| 100 | J7200_DEV_MCU_FSS0 |
| 101 | J7200_DEV_MCU_FSS0_FSAS_0 |
| 102 | J7200_DEV_MCU_FSS0_HYPERBUS1P0_0 |
| 103 | J7200_DEV_MCU_FSS0_OSPI_0 |
| 104 | J7200_DEV_MCU_FSS0_OSPI_1 |
| 105 | J7200_DEV_GPIO0 |
| 107 | J7200_DEV_GPIO2 |
| 109 | J7200_DEV_GPIO4 |
| 111 | J7200_DEV_GPIO6 |
| 113 | J7200_DEV_WKUP_GPIO0 |
| 114 | J7200_DEV_WKUP_GPIO1 |
| 115 | J7200_DEV_GPMC0 |
| 116 | J7200_DEV_I3C0 |
| 117 | J7200_DEV_MCU_I3C0 |
| 118 | J7200_DEV_MCU_I3C1 |
| 123 | J7200_DEV_CMPEVENT_INTRTR0 |
| 127 | J7200_DEV_LED0 |
| 128 | J7200_DEV_MAIN2MCU_LVL_INTRTR0 |
| 130 | J7200_DEV_MAIN2MCU_PLS_INTRTR0 |
| 131 | J7200_DEV_GPIOMUX_INTRTR0 |
| 132 | J7200_DEV_WKUP_PORZ_SYNC0 |
| 133 | J7200_DEV_PSC0 |
| 136 | J7200_DEV_TIMESYNC_INTRTR0 |
| 137 | J7200_DEV_WKUP_GPIOMUX_INTRTR0 |
| 138 | J7200_DEV_WKUP_PSC0 |
| 139 | J7200_DEV_PBIST0 |
| 140 | J7200_DEV_PBIST1 |
| 141 | J7200_DEV_PBIST2 |
| 142 | J7200_DEV_MCU_PBIST0 |
| 143 | J7200_DEV_MCU_PBIST1 |
| 144 | J7200_DEV_MCU_PBIST2 |
| 145 | J7200_DEV_WKUP_DDPA0 |
| 146 | J7200_DEV_UART0 |
| 149 | J7200_DEV_MCU_UART0 |
| 150 | J7200_DEV_MCAN14 |
| 151 | J7200_DEV_MCAN15 |
| 152 | J7200_DEV_MCAN16 |
| 153 | J7200_DEV_MCAN17 |
| 154 | J7200_DEV_WKUP_VTM0 |
| 155 | J7200_DEV_MAIN2WKUPMCU_VD |
| 156 | J7200_DEV_MCAN0 |
| 157 | J7200_DEV_BOARD0 |
| 158 | J7200_DEV_MCAN1 |
| 160 | J7200_DEV_MCAN2 |
| 161 | J7200_DEV_MCAN3 |
| 162 | J7200_DEV_MCAN4 |
| 163 | J7200_DEV_MCAN5 |
| 164 | J7200_DEV_MCAN6 |
| 165 | J7200_DEV_MCAN7 |
| 166 | J7200_DEV_MCAN8 |
| 167 | J7200_DEV_MCAN9 |
| 168 | J7200_DEV_MCAN10 |
| 169 | J7200_DEV_MCAN11 |
| 170 | J7200_DEV_MCAN12 |
| 171 | J7200_DEV_MCAN13 |
| 172 | J7200_DEV_MCU_MCAN0 |
| 173 | J7200_DEV_MCU_MCAN1 |
| 174 | J7200_DEV_MCASP0 |
| 175 | J7200_DEV_MCASP1 |
| 176 | J7200_DEV_MCASP2 |
| 187 | J7200_DEV_I2C0 |
| 188 | J7200_DEV_I2C1 |
| 189 | J7200_DEV_I2C2 |
| 190 | J7200_DEV_I2C3 |
| 191 | J7200_DEV_I2C4 |
| 192 | J7200_DEV_I2C5 |
| 193 | J7200_DEV_I2C6 |
| 194 | J7200_DEV_MCU_I2C0 |
| 195 | J7200_DEV_MCU_I2C1 |
| 197 | J7200_DEV_WKUP_I2C0 |
| 199 | J7200_DEV_NAVSS0 |
| 201 | J7200_DEV_NAVSS0_CPTS_0 |
| 202 | J7200_DEV_A72SS0_CORE0_0 |
| 203 | J7200_DEV_A72SS0_CORE0_1 |
| 206 | J7200_DEV_NAVSS0_DTI_0 |
| 207 | J7200_DEV_NAVSS0_MODSS_INTA_0 |
| 208 | J7200_DEV_NAVSS0_MODSS_INTA_1 |
| 209 | J7200_DEV_NAVSS0_UDMASS_INTA_0 |
| 210 | J7200_DEV_NAVSS0_PROXY_0 |
| 211 | J7200_DEV_NAVSS0_RINGACC_0 |
| 212 | J7200_DEV_NAVSS0_UDMAP_0 |
| 213 | J7200_DEV_NAVSS0_INTR_ROUTER_0 |
| 214 | J7200_DEV_NAVSS0_MAILBOX_0 |
| 215 | J7200_DEV_NAVSS0_MAILBOX_1 |
| 216 | J7200_DEV_NAVSS0_MAILBOX_2 |
| 217 | J7200_DEV_NAVSS0_MAILBOX_3 |
| 218 | J7200_DEV_NAVSS0_MAILBOX_4 |
| 219 | J7200_DEV_NAVSS0_MAILBOX_5 |
| 220 | J7200_DEV_NAVSS0_MAILBOX_6 |
| 221 | J7200_DEV_NAVSS0_MAILBOX_7 |
| 222 | J7200_DEV_NAVSS0_MAILBOX_8 |
| 223 | J7200_DEV_NAVSS0_MAILBOX_9 |
| 224 | J7200_DEV_NAVSS0_MAILBOX_10 |
| 225 | J7200_DEV_NAVSS0_MAILBOX_11 |
| 226 | J7200_DEV_NAVSS0_SPINLOCK_0 |
| 227 | J7200_DEV_NAVSS0_MCRC_0 |
| 228 | J7200_DEV_NAVSS0_TBU_0 |
| 230 | J7200_DEV_NAVSS0_TIMERMGR_0 |
| 231 | J7200_DEV_NAVSS0_TIMERMGR_1 |
| 232 | J7200_DEV_MCU_NAVSS0 |
| 233 | J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 |
| 234 | J7200_DEV_MCU_NAVSS0_PROXY0 |
| 235 | J7200_DEV_MCU_NAVSS0_RINGACC0 |
| 236 | J7200_DEV_MCU_NAVSS0_UDMAP_0 |
| 237 | J7200_DEV_MCU_NAVSS0_INTR_0 |
| 238 | J7200_DEV_MCU_NAVSS0_MCRC_0 |
| 240 | J7200_DEV_PCIE1 |
| 243 | J7200_DEV_R5FSS0 |
| 245 | J7200_DEV_R5FSS0_CORE0 |
| 246 | J7200_DEV_R5FSS0_CORE1 |
| 249 | J7200_DEV_MCU_R5FSS0 |
| 250 | J7200_DEV_MCU_R5FSS0_CORE0 |
| 251 | J7200_DEV_MCU_R5FSS0_CORE1 |
| 252 | J7200_DEV_RTI0 |
| 253 | J7200_DEV_RTI1 |
| 258 | J7200_DEV_RTI28 |
| 259 | J7200_DEV_RTI29 |
| 262 | J7200_DEV_MCU_RTI0 |
| 263 | J7200_DEV_MCU_RTI1 |
| 265 | J7200_DEV_MCU_SA2_UL0 |
| 266 | J7200_DEV_MCSPI0 |
| 267 | J7200_DEV_MCSPI1 |
| 268 | J7200_DEV_MCSPI2 |
| 269 | J7200_DEV_MCSPI3 |
| 270 | J7200_DEV_MCSPI4 |
| 271 | J7200_DEV_MCSPI5 |
| 272 | J7200_DEV_MCSPI6 |
| 273 | J7200_DEV_MCSPI7 |
| 274 | J7200_DEV_MCU_MCSPI0 |
| 275 | J7200_DEV_MCU_MCSPI1 |
| 276 | J7200_DEV_MCU_MCSPI2 |
| 278 | J7200_DEV_UART1 |
| 279 | J7200_DEV_UART2 |
| 280 | J7200_DEV_UART3 |
| 281 | J7200_DEV_UART4 |
| 282 | J7200_DEV_UART5 |
| 283 | J7200_DEV_UART6 |
| 284 | J7200_DEV_UART7 |
| 285 | J7200_DEV_UART8 |
| 286 | J7200_DEV_UART9 |
| 287 | J7200_DEV_WKUP_UART0 |
| 288 | J7200_DEV_USB0 |
| 292 | J7200_DEV_SERDES_10G1 |
| 298 | J7200_DEV_WKUPMCU2MAIN_VD |
| 299 | J7200_DEV_NAVSS0_MODSS |
| 300 | J7200_DEV_NAVSS0_UDMASS |
| 301 | J7200_DEV_NAVSS0_VIRTSS |
| 302 | J7200_DEV_MCU_NAVSS0_MODSS |
| 303 | J7200_DEV_MCU_NAVSS0_UDMASS |
| 304 | J7200_DEV_DEBUGSS_WRAP0 |
| 305 | J7200_DEV_FFI_MAIN_INFRA_CBASS_VD |
| 306 | J7200_DEV_FFI_MAIN_IP_CBASS_VD |
| 307 | J7200_DEV_FFI_MAIN_RC_CBASS_VD |