J7200 Secure Proxy Descriptions

Introduction

This chapter provides information of Secure Proxies and communication paths that are permitted in the J7200 SoC. These host IDs represent processing entities (or PEs) which is mandatory identification of a Host in a processor. See PE/Host documentation for further information

Enumeration of Secure Proxies

Sproxy ID	Sproxy Name
0	NAVSS0_SEC_PROXY_0
1	MCU_NAVSS0_SEC_PROXY0

Thread Allocation per Secure Proxy

Secure Proxy thread allocation for NAVSS0_SEC_PROXY_0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
148	read	9	DM	nonsec_high_priority_rx	MCU_R5FSS0_CORE0/INTR_69, MCU_R5FSS0_CORE0/INTR_70	MCU_R5FSS0_CORE0/INTR_69, MCU_R5FSS0_CORE0/INTR_70
147	read	36	DM	nonsec_low_priority_rx	MCU_R5FSS0_CORE0/INTR_71, MCU_R5FSS0_CORE0/INTR_72	MCU_R5FSS0_CORE0/INTR_71, MCU_R5FSS0_CORE0/INTR_72
146	read	9	DM	nonsec_notify_resp_rx	MCU_R5FSS0_CORE0/INTR_73, MCU_R5FSS0_CORE0/INTR_74	MCU_R5FSS0_CORE0/INTR_73, MCU_R5FSS0_CORE0/INTR_74
145	write	2	DM	nonsec_A72_2_notify_tx	N/A	N/A
144	write	22	DM	nonsec_A72_2_response_tx	N/A	N/A
143	write	2	DM	nonsec_A72_3_notify_tx	N/A	N/A
142	write	7	DM	nonsec_A72_3_response_tx	N/A	N/A
141	write	2	DM	nonsec_A72_4_notify_tx	N/A	N/A
140	write	7	DM	nonsec_A72_4_response_tx	N/A	N/A
139	write	2	DM	nonsec_MAIN_0_R5_0_notify_tx	N/A	N/A
138	write	7	DM	nonsec_MAIN_0_R5_0_response_tx	N/A	N/A
137	write	1	DM	nonsec_MAIN_0_R5_2_notify_tx	N/A	N/A
136	write	2	DM	nonsec_MAIN_0_R5_2_response_tx	N/A	N/A
0	read	2	A72_0	notify	COMPUTE_CLUSTER0_GIC500SS/SPI_64, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_64, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_64	COMPUTE_CLUSTER0_GIC500SS/SPI_64, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_64, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_64
1	read	30	A72_0	response	COMPUTE_CLUSTER0_GIC500SS/SPI_65, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_65, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_65	COMPUTE_CLUSTER0_GIC500SS/SPI_65, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_65, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_65
2	write	10	A72_0	high_priority	N/A	N/A
3	write	20	A72_0	low_priority	N/A	N/A
4	write	2	A72_0	notify_resp	N/A	N/A
5	read	2	A72_1	notify	COMPUTE_CLUSTER0_GIC500SS/SPI_66, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_66, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_66	COMPUTE_CLUSTER0_GIC500SS/SPI_66, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_66, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_66
6	read	30	A72_1	response	COMPUTE_CLUSTER0_GIC500SS/SPI_67, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_67, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_67	COMPUTE_CLUSTER0_GIC500SS/SPI_67, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_67, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_67
7	write	10	A72_1	high_priority	N/A	N/A
8	write	20	A72_1	low_priority	N/A	N/A
9	write	2	A72_1	notify_resp	N/A	N/A
10	read	2	A72_2	notify	COMPUTE_CLUSTER0_GIC500SS/SPI_68, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_68, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_68	COMPUTE_CLUSTER0_GIC500SS/SPI_68, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_68, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_68
11	read	22	A72_2	response	COMPUTE_CLUSTER0_GIC500SS/SPI_69, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_69, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_69	COMPUTE_CLUSTER0_GIC500SS/SPI_69, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_69, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_69
12	write	2	A72_2	high_priority	N/A	N/A
13	write	20	A72_2	low_priority	N/A	N/A
14	write	2	A72_2	notify_resp	N/A	N/A
15	read	2	A72_3	notify	COMPUTE_CLUSTER0_GIC500SS/SPI_70, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_70, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_70	COMPUTE_CLUSTER0_GIC500SS/SPI_70, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_70, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_70
16	read	7	A72_3	response	COMPUTE_CLUSTER0_GIC500SS/SPI_71, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_71, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_71	COMPUTE_CLUSTER0_GIC500SS/SPI_71, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_71, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_71
17	write	2	A72_3	high_priority	N/A	N/A
18	write	5	A72_3	low_priority	N/A	N/A
19	write	2	A72_3	notify_resp	N/A	N/A
20	read	2	A72_4	notify	COMPUTE_CLUSTER0_GIC500SS/SPI_72, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_72, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_72	COMPUTE_CLUSTER0_GIC500SS/SPI_72, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_72, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_72
21	read	7	A72_4	response	COMPUTE_CLUSTER0_GIC500SS/SPI_73, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_73, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_73	COMPUTE_CLUSTER0_GIC500SS/SPI_73, COMPUTE_CLUSTER0_MSMC_1MB/GIC_SPI_73, COMPUTE_CLUSTER0_MSMC_EN/GIC_SPI_73
22	write	2	A72_4	high_priority	N/A	N/A
23	write	5	A72_4	low_priority	N/A	N/A
24	write	2	A72_4	notify_resp	N/A	N/A
25	read	2	MAIN_0_R5_0	notify	R5FSS0_CORE0/INTR_224	R5FSS0_CORE0/INTR_224
26	read	7	MAIN_0_R5_0	response	R5FSS0_CORE0/INTR_225	R5FSS0_CORE0/INTR_225
27	write	2	MAIN_0_R5_0	high_priority	N/A	N/A
28	write	5	MAIN_0_R5_0	low_priority	N/A	N/A
29	write	2	MAIN_0_R5_0	notify_resp	N/A	N/A
30	read	2	MAIN_0_R5_1	notify	R5FSS0_CORE0/INTR_226	R5FSS0_CORE0/INTR_226
31	read	7	MAIN_0_R5_1	response	R5FSS0_CORE0/INTR_227	R5FSS0_CORE0/INTR_227
32	write	2	MAIN_0_R5_1	high_priority	N/A	N/A
33	write	5	MAIN_0_R5_1	low_priority	N/A	N/A
34	write	2	MAIN_0_R5_1	notify_resp	N/A	N/A
35	read	1	MAIN_0_R5_2	notify	R5FSS0_CORE1/INTR_224	R5FSS0_CORE1/INTR_224
36	read	2	MAIN_0_R5_2	response	R5FSS0_CORE1/INTR_225	R5FSS0_CORE1/INTR_225
37	write	1	MAIN_0_R5_2	high_priority	N/A	N/A
38	write	1	MAIN_0_R5_2	low_priority	N/A	N/A
39	write	1	MAIN_0_R5_2	notify_resp	N/A	N/A
40	read	1	MAIN_0_R5_3	notify	R5FSS0_CORE1/INTR_226	R5FSS0_CORE1/INTR_226
41	read	2	MAIN_0_R5_3	response	R5FSS0_CORE1/INTR_227	R5FSS0_CORE1/INTR_227
42	write	1	MAIN_0_R5_3	high_priority	N/A	N/A
43	write	1	MAIN_0_R5_3	low_priority	N/A	N/A
44	write	1	MAIN_0_R5_3	notify_resp	N/A	N/A

Secure Proxy thread allocation for MCU_NAVSS0_SEC_PROXY0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
80	read	13	DM	nonsec_high_priority_rx	MCU_R5FSS0_CORE0/INTR_69, MCU_R5FSS0_CORE0/INTR_70	MCU_R5FSS0_CORE0/INTR_69, MCU_R5FSS0_CORE0/INTR_70
79	read	13	DM	nonsec_low_priority_rx	MCU_R5FSS0_CORE0/INTR_71, MCU_R5FSS0_CORE0/INTR_72	MCU_R5FSS0_CORE0/INTR_71, MCU_R5FSS0_CORE0/INTR_72
78	read	5	DM	nonsec_notify_resp_rx	MCU_R5FSS0_CORE0/INTR_73, MCU_R5FSS0_CORE0/INTR_74	MCU_R5FSS0_CORE0/INTR_73, MCU_R5FSS0_CORE0/INTR_74
77	write	2	DM	nonsec_MCU_0_R5_0_notify_tx	N/A	N/A
76	write	20	DM	nonsec_MCU_0_R5_0_response_tx	N/A	N/A
75	write	1	DM	nonsec_MCU_0_R5_2_notify_tx	N/A	N/A
74	write	2	DM	nonsec_MCU_0_R5_2_response_tx	N/A	N/A
73	write	2	DM	nonsec_DMSC2DM_notify_tx	N/A	N/A
72	write	4	DM	nonsec_DMSC2DM_response_tx	N/A	N/A
0	read	2	MCU_0_R5_0	notify	MCU_R5FSS0_CORE0/INTR_64	MCU_R5FSS0_CORE0/INTR_64
1	read	20	MCU_0_R5_0	response	MCU_R5FSS0_CORE0/INTR_65	MCU_R5FSS0_CORE0/INTR_65
2	write	10	MCU_0_R5_0	high_priority	N/A	N/A
3	write	10	MCU_0_R5_0	low_priority	N/A	N/A
4	write	2	MCU_0_R5_0	notify_resp	N/A	N/A
5	read	2	MCU_0_R5_1	notify	MCU_R5FSS0_CORE0/INTR_66	MCU_R5FSS0_CORE0/INTR_66
6	read	20	MCU_0_R5_1	response	MCU_R5FSS0_CORE0/INTR_67	MCU_R5FSS0_CORE0/INTR_67
7	write	10	MCU_0_R5_1	high_priority	N/A	N/A
8	write	10	MCU_0_R5_1	low_priority	N/A	N/A
9	write	2	MCU_0_R5_1	notify_resp	N/A	N/A
10	read	1	MCU_0_R5_2	notify	MCU_R5FSS0_CORE1/INTR_64	MCU_R5FSS0_CORE1/INTR_64
11	read	2	MCU_0_R5_2	response	MCU_R5FSS0_CORE1/INTR_65	MCU_R5FSS0_CORE1/INTR_65
12	write	1	MCU_0_R5_2	high_priority	N/A	N/A
13	write	1	MCU_0_R5_2	low_priority	N/A	N/A
14	write	1	MCU_0_R5_2	notify_resp	N/A	N/A
15	read	1	MCU_0_R5_3	notify	MCU_R5FSS0_CORE1/INTR_66	MCU_R5FSS0_CORE1/INTR_66
16	read	2	MCU_0_R5_3	response	MCU_R5FSS0_CORE1/INTR_67	MCU_R5FSS0_CORE1/INTR_67
17	write	1	MCU_0_R5_3	high_priority	N/A	N/A
18	write	1	MCU_0_R5_3	low_priority	N/A	N/A
19	write	1	MCU_0_R5_3	notify_resp	N/A	N/A
20	read	2	DM2DMSC	notify	N/A	N/A
21	read	4	DM2DMSC	response	N/A	N/A
22	write	2	DM2DMSC	high_priority	N/A	N/A
23	write	2	DM2DMSC	low_priority	N/A	N/A
24	write	2	DM2DMSC	notify_resp	N/A	N/A
25	read	2	DMSC2DM	notify	N/A	N/A
26	read	4	DMSC2DM	response	N/A	N/A
27	write	2	DMSC2DM	high_priority	N/A	N/A
28	write	2	DMSC2DM	low_priority	N/A	N/A
29	write	2	DMSC2DM	notify_resp	N/A	N/A