AM6 Secure Proxy Descriptions

Introduction

This chapter provides information of Secure Proxies and communication paths that are permitted in the am6 SoC. These host IDs represent processing entities (or PEs) which is mandatory identification of a Host in a processor. See PE/Host documentation for further information

Enumeration of Secure Proxies

Sproxy ID	Sproxy Name
0	main_sec_proxy0
1	mcu_sec_proxy0

Thread Allocation per Secure Proxy

Secure Proxy thread allocation for main_sec_proxy0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ threshold	IRQ error
0	read	2	A53_0	notify	gic500ss_main_0/bus_spi_64	gic500ss_main_0/bus_spi_64
1	read	30	A53_0	response	gic500ss_main_0/bus_spi_65	gic500ss_main_0/bus_spi_65
2	write	10	A53_0	high_priority	N/A	N/A
3	write	20	A53_0	low_priority	N/A	N/A
4	write	2	A53_0	notify_resp	N/A	N/A
5	read	2	A53_1	notify	gic500ss_main_0/bus_spi_66	gic500ss_main_0/bus_spi_66
6	read	30	A53_1	response	gic500ss_main_0/bus_spi_67	gic500ss_main_0/bus_spi_67
7	write	10	A53_1	high_priority	N/A	N/A
8	write	20	A53_1	low_priority	N/A	N/A
9	write	2	A53_1	notify_resp	N/A	N/A
10	read	2	A53_2	notify	gic500ss_main_0/bus_spi_68	gic500ss_main_0/bus_spi_68
11	read	22	A53_2	response	gic500ss_main_0/bus_spi_69	gic500ss_main_0/bus_spi_69
12	write	2	A53_2	high_priority	N/A	N/A
13	write	20	A53_2	low_priority	N/A	N/A
14	write	2	A53_2	notify_resp	N/A	N/A
15	read	2	A53_3	notify	gic500ss_main_0/bus_spi_70	gic500ss_main_0/bus_spi_70
16	read	7	A53_3	response	gic500ss_main_0/bus_spi_71	gic500ss_main_0/bus_spi_71
17	write	2	A53_3	high_priority	N/A	N/A
18	write	5	A53_3	low_priority	N/A	N/A
19	write	2	A53_3	notify_resp	N/A	N/A
20	read	2	A53_4	notify	gic500ss_main_0/bus_spi_72	gic500ss_main_0/bus_spi_72
21	read	5	A53_4	response	gic500ss_main_0/bus_spi_73	gic500ss_main_0/bus_spi_73
22	write	2	A53_4	high_priority	N/A	N/A
23	write	5	A53_4	low_priority	N/A	N/A
24	write	2	A53_4	notify_resp	N/A	N/A
25	read	2	A53_5	notify	gic500ss_main_0/bus_spi_74	gic500ss_main_0/bus_spi_74
26	read	5	A53_5	response	gic500ss_main_0/bus_spi_75	gic500ss_main_0/bus_spi_75
27	write	2	A53_5	high_priority	N/A	N/A
28	write	5	A53_5	low_priority	N/A	N/A
29	write	2	A53_5	notify_resp	N/A	N/A
30	read	2	A53_6	notify	gic500ss_main_0/bus_spi_76	gic500ss_main_0/bus_spi_76
31	read	5	A53_6	response	gic500ss_main_0/bus_spi_77	gic500ss_main_0/bus_spi_77
32	write	2	A53_6	high_priority	N/A	N/A
33	write	5	A53_6	low_priority	N/A	N/A
34	write	2	A53_6	notify_resp	N/A	N/A
35	read	2	A53_7	notify	gic500ss_main_0/bus_spi_78	gic500ss_main_0/bus_spi_78
36	read	5	A53_7	response	gic500ss_main_0/bus_spi_79	gic500ss_main_0/bus_spi_79
37	write	2	A53_7	high_priority	N/A	N/A
38	write	5	A53_7	low_priority	N/A	N/A
39	write	2	A53_7	notify_resp	N/A	N/A
40	read	2	ICSSG_0	notify	N/A	N/A
41	read	7	ICSSG_0	response	N/A	N/A
42	write	2	ICSSG_0	high_priority	N/A	N/A
43	write	5	ICSSG_0	low_priority	N/A	N/A
44	write	2	ICSSG_0	notify_resp	N/A	N/A
45	read	2	ICSSG_1	notify	N/A	N/A
46	read	4	ICSSG_1	response	N/A	N/A
47	write	2	ICSSG_1	high_priority	N/A	N/A
48	write	2	ICSSG_1	low_priority	N/A	N/A
49	write	2	ICSSG_1	notify_resp	N/A	N/A
50	read	2	ICSSG_2	notify	N/A	N/A
51	read	4	ICSSG_2	response	N/A	N/A
52	write	2	ICSSG_2	high_priority	N/A	N/A
53	write	2	ICSSG_2	low_priority	N/A	N/A
54	write	2	ICSSG_2	notify_resp	N/A	N/A
55	read	2	GPU_0	notify	N/A	N/A
56	read	7	GPU_0	response	N/A	N/A
57	write	2	GPU_0	high_priority	N/A	N/A
58	write	5	GPU_0	low_priority	N/A	N/A
59	write	2	GPU_0	notify_resp	N/A	N/A
60	read	2	GPU_1	notify	N/A	N/A
61	read	5	GPU_1	response	N/A	N/A
62	write	2	GPU_1	high_priority	N/A	N/A
63	write	3	GPU_1	low_priority	N/A	N/A
64	write	2	GPU_1	notify_resp	N/A	N/A

Secure Proxy thread allocation for mcu_sec_proxy0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ threshold	IRQ error
0	read	2	R5_0	notify	mcu_armss0_cpu0/bus_intr_64	mcu_armss0_cpu0/bus_intr_64
1	read	7	R5_0	response	mcu_armss0_cpu0/bus_intr_65	mcu_armss0_cpu0/bus_intr_65
2	write	2	R5_0	high_priority	N/A	N/A
3	write	5	R5_0	low_priority	N/A	N/A
4	write	2	R5_0	notify_resp	N/A	N/A
5	read	2	R5_1	notify	mcu_armss0_cpu0/bus_intr_66	mcu_armss0_cpu0/bus_intr_66
6	read	7	R5_1	response	mcu_armss0_cpu0/bus_intr_67	mcu_armss0_cpu0/bus_intr_67
7	write	2	R5_1	high_priority	N/A	N/A
8	write	5	R5_1	low_priority	N/A	N/A
9	write	2	R5_1	notify_resp	N/A	N/A
10	read	1	R5_2	notify	mcu_armss0_cpu1/bus_intr_64	mcu_armss0_cpu1/bus_intr_64
11	read	2	R5_2	response	mcu_armss0_cpu1/bus_intr_65	mcu_armss0_cpu1/bus_intr_65
12	write	1	R5_2	high_priority	N/A	N/A
13	write	1	R5_2	low_priority	N/A	N/A
14	write	1	R5_2	notify_resp	N/A	N/A
15	read	1	R5_3	notify	mcu_armss0_cpu1/bus_intr_66	mcu_armss0_cpu1/bus_intr_66
16	read	2	R5_3	response	mcu_armss0_cpu1/bus_intr_67	mcu_armss0_cpu1/bus_intr_67
17	write	1	R5_3	high_priority	N/A	N/A
18	write	1	R5_3	low_priority	N/A	N/A
19	write	1	R5_3	notify_resp	N/A	N/A