J784S4 Secure Proxy Descriptions

Introduction

This chapter provides information of Secure Proxies and communication paths that are permitted in the J784S4 SoC. These host IDs represent processing entities (or PEs) which is mandatory identification of a Host in a processor. See PE/Host documentation for further information

Enumeration of Secure Proxies

Sproxy ID	Sproxy Name
0	NAVSS0_SEC_PROXY_0
1	MCU_NAVSS0_SEC_PROXY0
2	MCU_SA3_SS0_SEC_PROXY_0

Thread Allocation per Secure Proxy

Secure Proxy thread allocation for NAVSS0_SEC_PROXY_0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
342	read	31	DM	nonsec_high_priority_rx	MCU_R5FSS0_CORE0/INTR_70, MCU_R5FSS0_CORE0/INTR_71	MCU_R5FSS0_CORE0/INTR_70, MCU_R5FSS0_CORE0/INTR_71
341	read	103	DM	nonsec_low_priority_rx	MCU_R5FSS0_CORE0/INTR_72, MCU_R5FSS0_CORE0/INTR_73	MCU_R5FSS0_CORE0/INTR_72, MCU_R5FSS0_CORE0/INTR_73
340	read	31	DM	nonsec_notify_resp_rx	MCU_R5FSS0_CORE0/INTR_74, MCU_R5FSS0_CORE0/INTR_75	MCU_R5FSS0_CORE0/INTR_74, MCU_R5FSS0_CORE0/INTR_75
339	write	2	DM	nonsec_A72_2_notify_tx	N/A	N/A
338	write	22	DM	nonsec_A72_2_response_tx	N/A	N/A
337	write	2	DM	nonsec_A72_3_notify_tx	N/A	N/A
336	write	7	DM	nonsec_A72_3_response_tx	N/A	N/A
335	write	2	DM	nonsec_A72_4_notify_tx	N/A	N/A
334	write	7	DM	nonsec_A72_4_response_tx	N/A	N/A
333	write	2	DM	nonsec_A72_5_notify_tx	N/A	N/A
332	write	22	DM	nonsec_A72_5_response_tx	N/A	N/A
331	write	2	DM	nonsec_A72_6_notify_tx	N/A	N/A
330	write	7	DM	nonsec_A72_6_response_tx	N/A	N/A
329	write	2	DM	nonsec_A72_7_notify_tx	N/A	N/A
328	write	7	DM	nonsec_A72_7_response_tx	N/A	N/A
327	write	2	DM	nonsec_C7X_0_1_notify_tx	N/A	N/A
326	write	7	DM	nonsec_C7X_0_1_response_tx	N/A	N/A
325	write	2	DM	nonsec_C7X_1_1_notify_tx	N/A	N/A
324	write	7	DM	nonsec_C7X_1_1_response_tx	N/A	N/A
323	write	2	DM	nonsec_C7X_2_1_notify_tx	N/A	N/A
322	write	7	DM	nonsec_C7X_2_1_response_tx	N/A	N/A
321	write	2	DM	nonsec_C7X_3_1_notify_tx	N/A	N/A
320	write	7	DM	nonsec_C7X_3_1_response_tx	N/A	N/A
319	write	2	DM	nonsec_GPU_0_notify_tx	N/A	N/A
318	write	7	DM	nonsec_GPU_0_response_tx	N/A	N/A
317	write	2	DM	nonsec_MAIN_0_R5_0_notify_tx	N/A	N/A
316	write	7	DM	nonsec_MAIN_0_R5_0_response_tx	N/A	N/A
315	write	1	DM	nonsec_MAIN_0_R5_2_notify_tx	N/A	N/A
314	write	2	DM	nonsec_MAIN_0_R5_2_response_tx	N/A	N/A
313	write	2	DM	nonsec_MAIN_1_R5_0_notify_tx	N/A	N/A
312	write	7	DM	nonsec_MAIN_1_R5_0_response_tx	N/A	N/A
311	write	1	DM	nonsec_MAIN_1_R5_2_notify_tx	N/A	N/A
310	write	2	DM	nonsec_MAIN_1_R5_2_response_tx	N/A	N/A
309	write	2	DM	nonsec_MAIN_2_R5_0_notify_tx	N/A	N/A
308	write	7	DM	nonsec_MAIN_2_R5_0_response_tx	N/A	N/A
307	write	1	DM	nonsec_MAIN_2_R5_2_notify_tx	N/A	N/A
306	write	2	DM	nonsec_MAIN_2_R5_2_response_tx	N/A	N/A
0	read	2	A72_0	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_64, COMPUTE_CLUSTER0_GIC500SS/SPI_64	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_64, COMPUTE_CLUSTER0_GIC500SS/SPI_64
1	read	30	A72_0	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_65, COMPUTE_CLUSTER0_GIC500SS/SPI_65	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_65, COMPUTE_CLUSTER0_GIC500SS/SPI_65
2	write	10	A72_0	high_priority	N/A	N/A
3	write	20	A72_0	low_priority	N/A	N/A
4	write	2	A72_0	notify_resp	N/A	N/A
5	read	2	A72_1	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_66, COMPUTE_CLUSTER0_GIC500SS/SPI_66	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_66, COMPUTE_CLUSTER0_GIC500SS/SPI_66
6	read	30	A72_1	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_67, COMPUTE_CLUSTER0_GIC500SS/SPI_67	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_67, COMPUTE_CLUSTER0_GIC500SS/SPI_67
7	write	10	A72_1	high_priority	N/A	N/A
8	write	20	A72_1	low_priority	N/A	N/A
9	write	2	A72_1	notify_resp	N/A	N/A
10	read	2	A72_2	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_68, COMPUTE_CLUSTER0_GIC500SS/SPI_68	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_68, COMPUTE_CLUSTER0_GIC500SS/SPI_68
11	read	22	A72_2	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_69, COMPUTE_CLUSTER0_GIC500SS/SPI_69	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_69, COMPUTE_CLUSTER0_GIC500SS/SPI_69
12	write	2	A72_2	high_priority	N/A	N/A
13	write	20	A72_2	low_priority	N/A	N/A
14	write	2	A72_2	notify_resp	N/A	N/A
15	read	2	A72_3	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_70, COMPUTE_CLUSTER0_GIC500SS/SPI_70	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_70, COMPUTE_CLUSTER0_GIC500SS/SPI_70
16	read	7	A72_3	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_71, COMPUTE_CLUSTER0_GIC500SS/SPI_71	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_71, COMPUTE_CLUSTER0_GIC500SS/SPI_71
17	write	2	A72_3	high_priority	N/A	N/A
18	write	5	A72_3	low_priority	N/A	N/A
19	write	2	A72_3	notify_resp	N/A	N/A
20	read	2	A72_4	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_72, COMPUTE_CLUSTER0_GIC500SS/SPI_72	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_72, COMPUTE_CLUSTER0_GIC500SS/SPI_72
21	read	7	A72_4	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_73, COMPUTE_CLUSTER0_GIC500SS/SPI_73	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_73, COMPUTE_CLUSTER0_GIC500SS/SPI_73
22	write	2	A72_4	high_priority	N/A	N/A
23	write	5	A72_4	low_priority	N/A	N/A
24	write	2	A72_4	notify_resp	N/A	N/A
25	read	2	A72_5	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_74, COMPUTE_CLUSTER0_GIC500SS/SPI_74	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_74, COMPUTE_CLUSTER0_GIC500SS/SPI_74
26	read	22	A72_5	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_75, COMPUTE_CLUSTER0_GIC500SS/SPI_75	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_75, COMPUTE_CLUSTER0_GIC500SS/SPI_75
27	write	2	A72_5	high_priority	N/A	N/A
28	write	20	A72_5	low_priority	N/A	N/A
29	write	2	A72_5	notify_resp	N/A	N/A
30	read	2	A72_6	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_76, COMPUTE_CLUSTER0_GIC500SS/SPI_76	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_76, COMPUTE_CLUSTER0_GIC500SS/SPI_76
31	read	7	A72_6	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_77, COMPUTE_CLUSTER0_GIC500SS/SPI_77	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_77, COMPUTE_CLUSTER0_GIC500SS/SPI_77
32	write	2	A72_6	high_priority	N/A	N/A
33	write	5	A72_6	low_priority	N/A	N/A
34	write	2	A72_6	notify_resp	N/A	N/A
35	read	2	A72_7	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_78, COMPUTE_CLUSTER0_GIC500SS/SPI_78	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_78, COMPUTE_CLUSTER0_GIC500SS/SPI_78
36	read	7	A72_7	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_79, COMPUTE_CLUSTER0_GIC500SS/SPI_79	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_79, COMPUTE_CLUSTER0_GIC500SS/SPI_79
37	write	2	A72_7	high_priority	N/A	N/A
38	write	5	A72_7	low_priority	N/A	N/A
39	write	2	A72_7	notify_resp	N/A	N/A
40	read	2	C7X_0_0	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_720, COMPUTE_CLUSTER0_GIC500SS/SPI_720	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_720, COMPUTE_CLUSTER0_GIC500SS/SPI_720
41	read	7	C7X_0_0	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_721, COMPUTE_CLUSTER0_GIC500SS/SPI_721	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_721, COMPUTE_CLUSTER0_GIC500SS/SPI_721
42	write	2	C7X_0_0	high_priority	N/A	N/A
43	write	5	C7X_0_0	low_priority	N/A	N/A
44	write	2	C7X_0_0	notify_resp	N/A	N/A
45	read	2	C7X_0_1	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_722, COMPUTE_CLUSTER0_GIC500SS/SPI_722	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_722, COMPUTE_CLUSTER0_GIC500SS/SPI_722
46	read	7	C7X_0_1	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_723, COMPUTE_CLUSTER0_GIC500SS/SPI_723	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_723, COMPUTE_CLUSTER0_GIC500SS/SPI_723
47	write	2	C7X_0_1	high_priority	N/A	N/A
48	write	5	C7X_0_1	low_priority	N/A	N/A
49	write	2	C7X_0_1	notify_resp	N/A	N/A
50	read	2	C7X_1_0	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_724, COMPUTE_CLUSTER0_GIC500SS/SPI_724	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_724, COMPUTE_CLUSTER0_GIC500SS/SPI_724
51	read	7	C7X_1_0	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_725, COMPUTE_CLUSTER0_GIC500SS/SPI_725	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_725, COMPUTE_CLUSTER0_GIC500SS/SPI_725
52	write	2	C7X_1_0	high_priority	N/A	N/A
53	write	5	C7X_1_0	low_priority	N/A	N/A
54	write	2	C7X_1_0	notify_resp	N/A	N/A
55	read	2	C7X_1_1	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_726, COMPUTE_CLUSTER0_GIC500SS/SPI_726	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_726, COMPUTE_CLUSTER0_GIC500SS/SPI_726
56	read	7	C7X_1_1	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_727, COMPUTE_CLUSTER0_GIC500SS/SPI_727	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_727, COMPUTE_CLUSTER0_GIC500SS/SPI_727
57	write	2	C7X_1_1	high_priority	N/A	N/A
58	write	5	C7X_1_1	low_priority	N/A	N/A
59	write	2	C7X_1_1	notify_resp	N/A	N/A
60	read	2	C7X_2_0	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_728, COMPUTE_CLUSTER0_GIC500SS/SPI_728	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_728, COMPUTE_CLUSTER0_GIC500SS/SPI_728
61	read	7	C7X_2_0	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_729, COMPUTE_CLUSTER0_GIC500SS/SPI_729	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_729, COMPUTE_CLUSTER0_GIC500SS/SPI_729
62	write	2	C7X_2_0	high_priority	N/A	N/A
63	write	5	C7X_2_0	low_priority	N/A	N/A
64	write	2	C7X_2_0	notify_resp	N/A	N/A
65	read	2	C7X_2_1	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_730, COMPUTE_CLUSTER0_GIC500SS/SPI_730	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_730, COMPUTE_CLUSTER0_GIC500SS/SPI_730
66	read	7	C7X_2_1	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_731, COMPUTE_CLUSTER0_GIC500SS/SPI_731	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_731, COMPUTE_CLUSTER0_GIC500SS/SPI_731
67	write	2	C7X_2_1	high_priority	N/A	N/A
68	write	5	C7X_2_1	low_priority	N/A	N/A
69	write	2	C7X_2_1	notify_resp	N/A	N/A
70	read	2	C7X_3_0	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_732, COMPUTE_CLUSTER0_GIC500SS/SPI_732	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_732, COMPUTE_CLUSTER0_GIC500SS/SPI_732
71	read	7	C7X_3_0	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_733, COMPUTE_CLUSTER0_GIC500SS/SPI_733	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_733, COMPUTE_CLUSTER0_GIC500SS/SPI_733
72	write	2	C7X_3_0	high_priority	N/A	N/A
73	write	5	C7X_3_0	low_priority	N/A	N/A
74	write	2	C7X_3_0	notify_resp	N/A	N/A
75	read	2	C7X_3_1	notify	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_734, COMPUTE_CLUSTER0_GIC500SS/SPI_734	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_734, COMPUTE_CLUSTER0_GIC500SS/SPI_734
76	read	7	C7X_3_1	response	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_735, COMPUTE_CLUSTER0_GIC500SS/SPI_735	COMPUTE_CLUSTER0_CLEC/SOC_EVENTS_IN_735, COMPUTE_CLUSTER0_GIC500SS/SPI_735
77	write	2	C7X_3_1	high_priority	N/A	N/A
78	write	5	C7X_3_1	low_priority	N/A	N/A
79	write	2	C7X_3_1	notify_resp	N/A	N/A
80	read	2	GPU_0	notify	N/A	N/A
81	read	7	GPU_0	response	N/A	N/A
82	write	2	GPU_0	high_priority	N/A	N/A
83	write	5	GPU_0	low_priority	N/A	N/A
84	write	2	GPU_0	notify_resp	N/A	N/A
85	read	2	MAIN_0_R5_0	notify	R5FSS0_CORE0/INTR_224	R5FSS0_CORE0/INTR_224
86	read	7	MAIN_0_R5_0	response	R5FSS0_CORE0/INTR_225	R5FSS0_CORE0/INTR_225
87	write	2	MAIN_0_R5_0	high_priority	N/A	N/A
88	write	5	MAIN_0_R5_0	low_priority	N/A	N/A
89	write	2	MAIN_0_R5_0	notify_resp	N/A	N/A
90	read	2	MAIN_0_R5_1	notify	R5FSS0_CORE0/INTR_226	R5FSS0_CORE0/INTR_226
91	read	7	MAIN_0_R5_1	response	R5FSS0_CORE0/INTR_227	R5FSS0_CORE0/INTR_227
92	write	2	MAIN_0_R5_1	high_priority	N/A	N/A
93	write	5	MAIN_0_R5_1	low_priority	N/A	N/A
94	write	2	MAIN_0_R5_1	notify_resp	N/A	N/A
95	read	1	MAIN_0_R5_2	notify	R5FSS0_CORE1/INTR_224	R5FSS0_CORE1/INTR_224
96	read	2	MAIN_0_R5_2	response	R5FSS0_CORE1/INTR_225	R5FSS0_CORE1/INTR_225
97	write	1	MAIN_0_R5_2	high_priority	N/A	N/A
98	write	1	MAIN_0_R5_2	low_priority	N/A	N/A
99	write	1	MAIN_0_R5_2	notify_resp	N/A	N/A
100	read	1	MAIN_0_R5_3	notify	R5FSS0_CORE1/INTR_226	R5FSS0_CORE1/INTR_226
101	read	2	MAIN_0_R5_3	response	R5FSS0_CORE1/INTR_227	R5FSS0_CORE1/INTR_227
102	write	1	MAIN_0_R5_3	high_priority	N/A	N/A
103	write	1	MAIN_0_R5_3	low_priority	N/A	N/A
104	write	1	MAIN_0_R5_3	notify_resp	N/A	N/A
105	read	2	MAIN_1_R5_0	notify	R5FSS1_CORE0/INTR_224	R5FSS1_CORE0/INTR_224
106	read	7	MAIN_1_R5_0	response	R5FSS1_CORE0/INTR_225	R5FSS1_CORE0/INTR_225
107	write	2	MAIN_1_R5_0	high_priority	N/A	N/A
108	write	5	MAIN_1_R5_0	low_priority	N/A	N/A
109	write	2	MAIN_1_R5_0	notify_resp	N/A	N/A
110	read	2	MAIN_1_R5_1	notify	R5FSS1_CORE0/INTR_226	R5FSS1_CORE0/INTR_226
111	read	7	MAIN_1_R5_1	response	R5FSS1_CORE0/INTR_227	R5FSS1_CORE0/INTR_227
112	write	2	MAIN_1_R5_1	high_priority	N/A	N/A
113	write	5	MAIN_1_R5_1	low_priority	N/A	N/A
114	write	2	MAIN_1_R5_1	notify_resp	N/A	N/A
115	read	1	MAIN_1_R5_2	notify	R5FSS1_CORE1/INTR_224	R5FSS1_CORE1/INTR_224
116	read	2	MAIN_1_R5_2	response	R5FSS1_CORE1/INTR_225	R5FSS1_CORE1/INTR_225
117	write	1	MAIN_1_R5_2	high_priority	N/A	N/A
118	write	1	MAIN_1_R5_2	low_priority	N/A	N/A
119	write	1	MAIN_1_R5_2	notify_resp	N/A	N/A
120	read	1	MAIN_1_R5_3	notify	R5FSS1_CORE1/INTR_226	R5FSS1_CORE1/INTR_226
121	read	2	MAIN_1_R5_3	response	R5FSS1_CORE1/INTR_227	R5FSS1_CORE1/INTR_227
122	write	1	MAIN_1_R5_3	high_priority	N/A	N/A
123	write	1	MAIN_1_R5_3	low_priority	N/A	N/A
124	write	1	MAIN_1_R5_3	notify_resp	N/A	N/A
125	read	2	MAIN_2_R5_0	notify	R5FSS2_CORE0/INTR_224	R5FSS2_CORE0/INTR_224
126	read	7	MAIN_2_R5_0	response	R5FSS2_CORE0/INTR_225	R5FSS2_CORE0/INTR_225
127	write	2	MAIN_2_R5_0	high_priority	N/A	N/A
128	write	5	MAIN_2_R5_0	low_priority	N/A	N/A
129	write	2	MAIN_2_R5_0	notify_resp	N/A	N/A
130	read	2	MAIN_2_R5_1	notify	R5FSS2_CORE0/INTR_226	R5FSS2_CORE0/INTR_226
131	read	7	MAIN_2_R5_1	response	R5FSS2_CORE0/INTR_227	R5FSS2_CORE0/INTR_227
132	write	2	MAIN_2_R5_1	high_priority	N/A	N/A
133	write	5	MAIN_2_R5_1	low_priority	N/A	N/A
134	write	2	MAIN_2_R5_1	notify_resp	N/A	N/A
135	read	1	MAIN_2_R5_2	notify	R5FSS2_CORE1/INTR_224	R5FSS2_CORE1/INTR_224
136	read	2	MAIN_2_R5_2	response	R5FSS2_CORE1/INTR_225	R5FSS2_CORE1/INTR_225
137	write	1	MAIN_2_R5_2	high_priority	N/A	N/A
138	write	1	MAIN_2_R5_2	low_priority	N/A	N/A
139	write	1	MAIN_2_R5_2	notify_resp	N/A	N/A
140	read	1	MAIN_2_R5_3	notify	R5FSS2_CORE1/INTR_226	R5FSS2_CORE1/INTR_226
141	read	2	MAIN_2_R5_3	response	R5FSS2_CORE1/INTR_227	R5FSS2_CORE1/INTR_227
142	write	1	MAIN_2_R5_3	high_priority	N/A	N/A
143	write	1	MAIN_2_R5_3	low_priority	N/A	N/A
144	write	1	MAIN_2_R5_3	notify_resp	N/A	N/A

Secure Proxy thread allocation for MCU_NAVSS0_SEC_PROXY0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
80	read	13	DM	nonsec_high_priority_rx	MCU_R5FSS0_CORE0/INTR_70, MCU_R5FSS0_CORE0/INTR_71	MCU_R5FSS0_CORE0/INTR_70, MCU_R5FSS0_CORE0/INTR_71
79	read	13	DM	nonsec_low_priority_rx	MCU_R5FSS0_CORE0/INTR_72, MCU_R5FSS0_CORE0/INTR_73	MCU_R5FSS0_CORE0/INTR_72, MCU_R5FSS0_CORE0/INTR_73
78	read	5	DM	nonsec_notify_resp_rx	MCU_R5FSS0_CORE0/INTR_74, MCU_R5FSS0_CORE0/INTR_75	MCU_R5FSS0_CORE0/INTR_74, MCU_R5FSS0_CORE0/INTR_75
77	write	2	DM	nonsec_MCU_0_R5_0_notify_tx	N/A	N/A
76	write	20	DM	nonsec_MCU_0_R5_0_response_tx	N/A	N/A
75	write	1	DM	nonsec_MCU_0_R5_2_notify_tx	N/A	N/A
74	write	2	DM	nonsec_MCU_0_R5_2_response_tx	N/A	N/A
73	write	2	DM	nonsec_TIFS2DM_notify_tx	N/A	N/A
72	write	4	DM	nonsec_TIFS2DM_response_tx	N/A	N/A
0	read	2	MCU_0_R5_0	notify	MCU_R5FSS0_CORE0/INTR_64	MCU_R5FSS0_CORE0/INTR_64
1	read	20	MCU_0_R5_0	response	MCU_R5FSS0_CORE0/INTR_65	MCU_R5FSS0_CORE0/INTR_65
2	write	10	MCU_0_R5_0	high_priority	N/A	N/A
3	write	10	MCU_0_R5_0	low_priority	N/A	N/A
4	write	2	MCU_0_R5_0	notify_resp	N/A	N/A
5	read	2	MCU_0_R5_1	notify	MCU_R5FSS0_CORE0/INTR_66	MCU_R5FSS0_CORE0/INTR_66
6	read	20	MCU_0_R5_1	response	MCU_R5FSS0_CORE0/INTR_67	MCU_R5FSS0_CORE0/INTR_67
7	write	10	MCU_0_R5_1	high_priority	N/A	N/A
8	write	10	MCU_0_R5_1	low_priority	N/A	N/A
9	write	2	MCU_0_R5_1	notify_resp	N/A	N/A
10	read	1	MCU_0_R5_2	notify	MCU_R5FSS0_CORE1/INTR_64	MCU_R5FSS0_CORE1/INTR_64
11	read	2	MCU_0_R5_2	response	MCU_R5FSS0_CORE1/INTR_65	MCU_R5FSS0_CORE1/INTR_65
12	write	1	MCU_0_R5_2	high_priority	N/A	N/A
13	write	1	MCU_0_R5_2	low_priority	N/A	N/A
14	write	1	MCU_0_R5_2	notify_resp	N/A	N/A
15	read	1	MCU_0_R5_3	notify	MCU_R5FSS0_CORE1/INTR_66	MCU_R5FSS0_CORE1/INTR_66
16	read	2	MCU_0_R5_3	response	MCU_R5FSS0_CORE1/INTR_67	MCU_R5FSS0_CORE1/INTR_67
17	write	1	MCU_0_R5_3	high_priority	N/A	N/A
18	write	1	MCU_0_R5_3	low_priority	N/A	N/A
19	write	1	MCU_0_R5_3	notify_resp	N/A	N/A
20	read	2	DM2TIFS	notify	N/A	N/A
21	read	4	DM2TIFS	response	N/A	N/A
22	write	2	DM2TIFS	high_priority	N/A	N/A
23	write	2	DM2TIFS	low_priority	N/A	N/A
24	write	2	DM2TIFS	notify_resp	N/A	N/A
25	read	2	TIFS2DM	notify	N/A	N/A
26	read	4	TIFS2DM	response	N/A	N/A
27	write	2	TIFS2DM	high_priority	N/A	N/A
28	write	2	TIFS2DM	low_priority	N/A	N/A
29	write	2	TIFS2DM	notify_resp	N/A	N/A

Secure Proxy thread allocation for MCU_SA3_SS0_SEC_PROXY_0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
15	read	8	TIFS_HSM	sec_low_priority_rx	WKUP_TIFS0/NVIC_81	WKUP_TIFS0/NVIC_81
14	write	8	TIFS_HSM	sec_HSM_response_tx	N/A	N/A
0	read	8	HSM	response	N/A	N/A
1	write	8	HSM	low_priority	N/A	N/A