J722S Secure Proxy Descriptions

Introduction

This chapter provides information of Secure Proxies and communication paths that are permitted in the J722S SoC. These host IDs represent processing entities (or PEs) which is mandatory identification of a Host in a processor. See PE/Host documentation for further information

Enumeration of Secure Proxies

Sproxy ID	Sproxy Name
0	DMASS0_SEC_PROXY_0
1	SA3_SS0_SEC_PROXY_0

Thread Allocation per Secure Proxy

Secure Proxy thread allocation for DMASS0_SEC_PROXY_0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
69	read	44	DM	nonsec_low_priority_rx	WKUP_R5FSS0_CORE0/INTR_67	WKUP_R5FSS0_CORE0/INTR_67
68	write	11	DM	nonsec_WKUP_0_R5_1_response_tx	N/A	N/A
67	write	6	DM	nonsec_MAIN_0_R5_1_response_tx	N/A	N/A
66	write	6	DM	nonsec_A53_2_response_tx	N/A	N/A
65	write	6	DM	nonsec_A53_3_response_tx	N/A	N/A
64	write	6	DM	nonsec_A53_4_response_tx	N/A	N/A
63	write	5	DM	nonsec_MCU_0_R5_0_response_tx	N/A	N/A
62	write	4	DM	nonsec_C7X_0_0_response_tx	N/A	N/A
61	write	4	DM	nonsec_C7X_1_0_response_tx	N/A	N/A
60	write	1	DM	nonsec_GPU_0_response_tx	N/A	N/A
59	write	1	DM	nonsec_GPU_1_response_tx	N/A	N/A
58	write	4	DM	nonsec_TIFS2DM_response_tx	N/A	N/A
0	read	11	WKUP_0_R5_0	response	WKUP_R5FSS0_CORE0/INTR_64	WKUP_R5FSS0_CORE0/INTR_64
1	write	10	WKUP_0_R5_0	low_priority	N/A	N/A
2	read	11	WKUP_0_R5_1	response	WKUP_R5FSS0_CORE0/INTR_65	WKUP_R5FSS0_CORE0/INTR_65
3	write	10	WKUP_0_R5_1	low_priority	N/A	N/A
4	read	6	MAIN_0_R5_0	response	R5FSS0_CORE0/INTR_64	R5FSS0_CORE0/INTR_64
5	write	5	MAIN_0_R5_0	low_priority	N/A	N/A
6	read	6	MAIN_0_R5_1	response	R5FSS0_CORE0/INTR_65	R5FSS0_CORE0/INTR_65
7	write	5	MAIN_0_R5_1	low_priority	N/A	N/A
8	read	11	A53_0	response	GICSS0/SPI_64	GICSS0/SPI_64
9	write	10	A53_0	low_priority	N/A	N/A
10	read	11	A53_1	response	GICSS0/SPI_65	GICSS0/SPI_65
11	write	10	A53_1	low_priority	N/A	N/A
12	read	6	A53_2	response	GICSS0/SPI_66	GICSS0/SPI_66
13	write	5	A53_2	low_priority	N/A	N/A
14	read	6	A53_3	response	GICSS0/SPI_67	GICSS0/SPI_67
15	write	5	A53_3	low_priority	N/A	N/A
16	read	6	A53_4	response	GICSS0/SPI_68	GICSS0/SPI_68
17	write	5	A53_4	low_priority	N/A	N/A
18	read	5	MCU_0_R5_0	response	N/A	N/A
19	write	4	MCU_0_R5_0	low_priority	N/A	N/A
20	read	4	C7X_0_0	response	C7X256V0_CLEC/GIC_SPI_69	C7X256V0_CLEC/GIC_SPI_69
21	write	3	C7X_0_0	low_priority	N/A	N/A
22	read	4	C7X_1_0	response	C7X256V1_CLEC/GIC_SPI_70	C7X256V1_CLEC/GIC_SPI_70
23	write	3	C7X_1_0	low_priority	N/A	N/A
24	read	1	GPU_0	response	N/A	N/A
25	write	1	GPU_0	low_priority	N/A	N/A
26	read	1	GPU_1	response	N/A	N/A
27	write	1	GPU_1	low_priority	N/A	N/A
28	read	4	DM2TIFS	response	N/A	N/A
29	write	2	DM2TIFS	low_priority	N/A	N/A
30	read	4	TIFS2DM	response	N/A	N/A
31	write	2	TIFS2DM	low_priority	N/A	N/A

Secure Proxy thread allocation for SA3_SS0_SEC_PROXY_0

Secure Proxy Thread ID	Direction (write or read)	Number of Messages	Host	Host Function	IRQ (threshold)	IRQ (error)
15	read	8	TIFS_HSM	sec_low_priority_rx	TIFS0/NVIC_217	TIFS0/NVIC_217
14	write	8	TIFS_HSM	sec_HSM_response_tx	N/A	N/A
0	read	8	HSM	response	N/A	N/A
1	write	8	HSM	low_priority	N/A	N/A