J721S2 Interrupt Management Device Descriptions

Introduction

This chapter provides information on the Interrupt Management devices in the J721S2 SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.

Interrupt Router Device IDs

Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J721S2 Device IDs these are the valid Interrupt Router device IDs.

Interrupt Router Device Name	Interrupt Router Device ID
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122
J721S2_DEV_TIMESYNC_INTRTR0	124
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125
J721S2_DEV_GPIOMUX_INTRTR0	148
J721S2_DEV_CMPEVENT_INTRTR0	150
J721S2_DEV_NAVSS0_INTR_0	227
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268

MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	0	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	1	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	2	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	3	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	4	J721S2_DEV_SA2_UL0	sa_ul_trng	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	5	J721S2_DEV_SA2_UL0	sa_ul_pka	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	6	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	7	J721S2_DEV_ELM0	elm_porocpsinterrupt_lvl	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	8	J721S2_DEV_GPMC0	gpmc_sinterrupt	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	9	J721S2_DEV_DDR0	ddrss_pll_freq_change_req	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	10	J721S2_DEV_DDR0	ddrss_controller	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	11	J721S2_DEV_DDR0	ddrss_v2a_other_err_lvl	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	12	J721S2_DEV_DDR0	ddrss_hs_phy_global_error	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	13	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	14	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	15	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	16	J721S2_DEV_MCAN0	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	17	J721S2_DEV_MCAN0	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	18	J721S2_DEV_MCAN0	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	19	J721S2_DEV_MCAN1	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	20	J721S2_DEV_MCAN1	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	21	J721S2_DEV_MCAN1	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	22	J721S2_DEV_MCAN2	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	23	J721S2_DEV_MCAN2	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	24	J721S2_DEV_MCAN2	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	25	J721S2_DEV_MCAN3	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	26	J721S2_DEV_MCAN3	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	27	J721S2_DEV_MCAN3	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	28	J721S2_DEV_MMCSD0	emmcss_intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	29	J721S2_DEV_MMCSD1	emmcsdss_intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	30	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	31	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	32	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	33	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	34	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	35	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	36	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	37	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	38	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	39	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	40	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	41	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	42	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	43	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	44	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	45	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	46	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	47	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	48	J721S2_DEV_MCSPI0	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	49	J721S2_DEV_MCSPI1	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	50	J721S2_DEV_MCSPI2	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	51	J721S2_DEV_MCSPI3	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	52	J721S2_DEV_MCSPI4	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	53	J721S2_DEV_MCSPI5	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	54	J721S2_DEV_MCSPI6	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	55	J721S2_DEV_MCSPI7	intr_spi	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	56	J721S2_DEV_I2C0	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	57	J721S2_DEV_I2C1	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	58	J721S2_DEV_I2C2	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	59	J721S2_DEV_I2C3	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	60	J721S2_DEV_I2C4	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	61	J721S2_DEV_I2C5	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	62	J721S2_DEV_I2C6	pointrpend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	63	J721S2_DEV_DDR1	ddrss_pll_freq_change_req	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	64	J721S2_DEV_DDR1	ddrss_controller	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	65	J721S2_DEV_DDR1	ddrss_v2a_other_err_lvl	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	66	J721S2_DEV_DDR1	ddrss_hs_phy_global_error	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	67	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	68	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	69	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	70	J721S2_DEV_CPSW1	stat_pend	6
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	71	J721S2_DEV_CPSW1	mdio_pend	5
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	72	J721S2_DEV_CPSW1	evnt_pend	4
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	73	J721S2_DEV_PCIE1	pcie_phy_level	13
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	74	J721S2_DEV_PCIE1	pcie_local_level	12
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	75	J721S2_DEV_PCIE1	pcie_cpts_pend	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	76	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	77	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	78	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	79	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	80	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	81	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	82	J721S2_DEV_VUSR_DUAL0	v0_vusr_intlvl	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	83	J721S2_DEV_VUSR_DUAL0	v0_mcp_lo_intlvl	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	84	J721S2_DEV_VUSR_DUAL0	v0_mcp_hi_intlvl	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	85	J721S2_DEV_VUSR_DUAL0	v1_vusr_intlvl	5
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	86	J721S2_DEV_VUSR_DUAL0	v1_mcp_lo_intlvl	4
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	87	J721S2_DEV_VUSR_DUAL0	v1_mcp_hi_intlvl	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	88	J721S2_DEV_DCC0	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	89	J721S2_DEV_DCC1	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	90	J721S2_DEV_DCC2	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	91	J721S2_DEV_DCC3	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	92	J721S2_DEV_DCC4	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	93	J721S2_DEV_DCC5	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	94	J721S2_DEV_DCC6	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	95	J721S2_DEV_DCC7	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	96	J721S2_DEV_UART0	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	97	J721S2_DEV_UART1	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	98	J721S2_DEV_UART2	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	99	J721S2_DEV_UART3	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	100	J721S2_DEV_UART4	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	101	J721S2_DEV_UART5	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	102	J721S2_DEV_UART6	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	103	J721S2_DEV_UART7	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	104	J721S2_DEV_UART8	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	105	J721S2_DEV_UART9	usart_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	106	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	107	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	108	J721S2_DEV_TIMER0	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	109	J721S2_DEV_TIMER1	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	110	J721S2_DEV_TIMER2	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	111	J721S2_DEV_TIMER3	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	112	J721S2_DEV_TIMER4	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	113	J721S2_DEV_TIMER5	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	114	J721S2_DEV_TIMER6	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	115	J721S2_DEV_TIMER7	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	116	J721S2_DEV_TIMER8	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	117	J721S2_DEV_TIMER9	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	118	J721S2_DEV_TIMER10	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	119	J721S2_DEV_TIMER11	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	120	J721S2_DEV_TIMER12	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	121	J721S2_DEV_TIMER13	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	122	J721S2_DEV_TIMER14	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	123	J721S2_DEV_TIMER15	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	124	J721S2_DEV_TIMER16	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	125	J721S2_DEV_TIMER17	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	126	J721S2_DEV_TIMER18	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	127	J721S2_DEV_TIMER19	intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	128	J721S2_DEV_USB0	irq	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	129	J721S2_DEV_USB0	irq	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	130	J721S2_DEV_USB0	irq	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	131	J721S2_DEV_USB0	irq	4
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	132	J721S2_DEV_USB0	irq	5
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	133	J721S2_DEV_USB0	irq	6
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	134	J721S2_DEV_USB0	irq	7
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	135	J721S2_DEV_USB0	irq	8
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	136	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	137	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	138	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	139	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	140	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	141	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	142	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	143	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	144	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	145	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	146	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	147	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	148	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	149	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	150	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	151	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	152	J721S2_DEV_USB0	otgirq	9
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	153	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	154	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	155	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	156	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	157	J721S2_DEV_USB0	host_system_error	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	158	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	159	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	160	J721S2_DEV_MCAN14	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	161	J721S2_DEV_MCAN14	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	162	J721S2_DEV_MCAN14	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	163	J721S2_DEV_MCAN15	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	164	J721S2_DEV_MCAN15	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	165	J721S2_DEV_MCAN15	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	166	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	167	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	168	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	169	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	170	J721S2_DEV_MCAN16	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	171	J721S2_DEV_MCAN16	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	172	J721S2_DEV_MCAN16	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	173	J721S2_DEV_MCAN17	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	174	J721S2_DEV_MCAN17	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	175	J721S2_DEV_MCAN17	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	176	J721S2_DEV_MCASP0	xmit_intr_pend	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	177	J721S2_DEV_MCASP0	rec_intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	178	J721S2_DEV_MCASP1	xmit_intr_pend	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	179	J721S2_DEV_MCASP1	rec_intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	180	J721S2_DEV_MCASP2	xmit_intr_pend	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	181	J721S2_DEV_MCASP2	rec_intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	182	J721S2_DEV_MCASP3	xmit_intr_pend	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	183	J721S2_DEV_MCASP3	rec_intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	184	J721S2_DEV_MCASP4	xmit_intr_pend	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	185	J721S2_DEV_MCASP4	rec_intr_pend	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	186	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	187	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	188	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	189	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	190	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	191	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	192	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	193	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	194	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	195	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	196	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	197	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	198	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	199	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	200	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	201	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	202	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	203	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	204	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	205	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	206	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	207	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	208	J721S2_DEV_DCC8	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	209	J721S2_DEV_DCC9	intr_done_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	210	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	211	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	212	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	213	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	214	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	215	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	216	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	217	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	218	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	219	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	220	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	221	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	222	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	223	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	224	J721S2_DEV_DSS_DSI0	dsi_0_func_intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	225	J721S2_DEV_DSS_DSI1	dsi_0_func_intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	226	J721S2_DEV_DSS0	dss_inst0_dispc_func_irq_proc0	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	227	J721S2_DEV_DSS0	dss_inst0_dispc_func_irq_proc1	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	228	J721S2_DEV_DSS0	dss_inst0_dispc_secure_irq_proc0	4
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	229	J721S2_DEV_DSS0	dss_inst0_dispc_secure_irq_proc1	5
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	230	J721S2_DEV_DSS0	dss_inst0_dispc_safety_error_irq_proc0	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	231	J721S2_DEV_DSS0	dss_inst0_dispc_safety_error_irq_proc1	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	232	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	233	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	234	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	235	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	236	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	237	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	238	J721S2_DEV_DSS_EDP0	intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	239	J721S2_DEV_DSS_EDP0	intr	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	240	J721S2_DEV_DSS_EDP0	intr	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	241	J721S2_DEV_DSS_EDP0	intr	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	242	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	243	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	244	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	245	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	246	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	247	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	248	J721S2_DEV_CSI_TX_IF_V2_1	csi_interrupt	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	249	J721S2_DEV_CSI_TX_IF_V2_1	csi_level	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	250	J721S2_DEV_CSI_TX_IF_V2_0	csi_interrupt	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	251	J721S2_DEV_CSI_TX_IF_V2_0	csi_level	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	252	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	253	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	254	J721S2_DEV_CSI_RX_IF0	csi_irq	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	255	J721S2_DEV_CSI_RX_IF0	csi_err_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	256	J721S2_DEV_CSI_RX_IF0	csi_level	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	257	J721S2_DEV_CSI_RX_IF1	csi_irq	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	258	J721S2_DEV_CSI_RX_IF1	csi_err_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	259	J721S2_DEV_CSI_RX_IF1	csi_level	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	260	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	261	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	262	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	263	J721S2_DEV_CODEC0	vpu_wave521cl_intr	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	264	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	265	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	266	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	267	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	268	J721S2_DEV_DMPAC0_INTD_0	system_intr_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	269	J721S2_DEV_DMPAC0_INTD_0	system_intr_level	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	270	J721S2_DEV_VPAC0	vpac_level	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	271	J721S2_DEV_VPAC0	vpac_level	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	272	J721S2_DEV_VPAC0	vpac_level	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	273	J721S2_DEV_VPAC0	vpac_level	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	274	J721S2_DEV_VPAC0	vpac_level	4
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	275	J721S2_DEV_VPAC0	vpac_level	5
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	276	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	277	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	278	J721S2_DEV_MCAN4	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	279	J721S2_DEV_MCAN4	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	280	J721S2_DEV_MCAN4	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	281	J721S2_DEV_MCAN5	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	282	J721S2_DEV_MCAN5	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	283	J721S2_DEV_MCAN5	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	284	J721S2_DEV_MCAN6	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	285	J721S2_DEV_MCAN6	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	286	J721S2_DEV_MCAN6	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	287	J721S2_DEV_MCAN7	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	288	J721S2_DEV_MCAN7	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	289	J721S2_DEV_MCAN7	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	290	J721S2_DEV_MCAN8	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	291	J721S2_DEV_MCAN8	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	292	J721S2_DEV_MCAN8	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	293	J721S2_DEV_MCAN9	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	294	J721S2_DEV_MCAN9	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	295	J721S2_DEV_MCAN9	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	296	J721S2_DEV_MCAN10	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	297	J721S2_DEV_MCAN10	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	298	J721S2_DEV_MCAN10	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	299	J721S2_DEV_MCAN11	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	300	J721S2_DEV_MCAN11	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	301	J721S2_DEV_MCAN11	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	302	J721S2_DEV_MCAN12	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	303	J721S2_DEV_MCAN12	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	304	J721S2_DEV_MCAN12	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	305	J721S2_DEV_MCAN13	mcanss_mcan_lvl_int	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	306	J721S2_DEV_MCAN13	mcanss_mcan_lvl_int	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	307	J721S2_DEV_MCAN13	mcanss_ext_ts_rollover_lvl_int	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	308	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	309	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	310	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	311	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	312	J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0	os_irq	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	313	J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0	os_irq	1
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	314	J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0	os_irq	2
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	315	J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0	os_irq	3
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	316	J721S2_DEV_J7AEP_GPU_BXS464_WRAP0	gpu_pwrctrl_req	0
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	317	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	318	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	319	Use TRM - Not managed by TISCI

MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	0	J721S2_DEV_MCU_R5FSS0_CORE0	intr	160
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	160
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	1	J721S2_DEV_MCU_R5FSS0_CORE0	intr	161
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	161
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	2	J721S2_DEV_MCU_R5FSS0_CORE0	intr	162
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	162
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	3	J721S2_DEV_MCU_R5FSS0_CORE0	intr	163
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	163
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	4	J721S2_DEV_MCU_R5FSS0_CORE0	intr	164
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	164
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	5	J721S2_DEV_MCU_R5FSS0_CORE0	intr	165
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	165
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	6	J721S2_DEV_MCU_R5FSS0_CORE0	intr	166
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	166
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	7	J721S2_DEV_MCU_R5FSS0_CORE0	intr	167
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	167
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	8	J721S2_DEV_MCU_R5FSS0_CORE0	intr	168
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	168
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	9	J721S2_DEV_MCU_R5FSS0_CORE0	intr	169
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	169
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	10	J721S2_DEV_MCU_R5FSS0_CORE0	intr	170
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	170
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	11	J721S2_DEV_MCU_R5FSS0_CORE0	intr	171
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	171
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	12	J721S2_DEV_MCU_R5FSS0_CORE0	intr	172
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	172
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	13	J721S2_DEV_MCU_R5FSS0_CORE0	intr	173
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	173
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	14	J721S2_DEV_MCU_R5FSS0_CORE0	intr	174
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	174
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	15	J721S2_DEV_MCU_R5FSS0_CORE0	intr	175
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	175
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	16	J721S2_DEV_MCU_R5FSS0_CORE0	intr	176
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	176
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	17	J721S2_DEV_MCU_R5FSS0_CORE0	intr	177
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	177
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	18	J721S2_DEV_MCU_R5FSS0_CORE0	intr	178
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	178
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	19	J721S2_DEV_MCU_R5FSS0_CORE0	intr	179
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	179
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	20	J721S2_DEV_MCU_R5FSS0_CORE0	intr	180
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	180
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	21	J721S2_DEV_MCU_R5FSS0_CORE0	intr	181
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	181
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	22	J721S2_DEV_MCU_R5FSS0_CORE0	intr	182
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	182
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	23	J721S2_DEV_MCU_R5FSS0_CORE0	intr	183
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	183
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	24	J721S2_DEV_MCU_R5FSS0_CORE0	intr	184
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	184
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	25	J721S2_DEV_MCU_R5FSS0_CORE0	intr	185
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	185
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	26	J721S2_DEV_MCU_R5FSS0_CORE0	intr	186
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	186
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	27	J721S2_DEV_MCU_R5FSS0_CORE0	intr	187
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	187
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	28	J721S2_DEV_MCU_R5FSS0_CORE0	intr	188
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	188
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	29	J721S2_DEV_MCU_R5FSS0_CORE0	intr	189
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	189
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	30	J721S2_DEV_MCU_R5FSS0_CORE0	intr	190
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	190
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	31	J721S2_DEV_MCU_R5FSS0_CORE0	intr	191
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	191
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	32	J721S2_DEV_MCU_R5FSS0_CORE0	intr	192
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	192
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	33	J721S2_DEV_MCU_R5FSS0_CORE0	intr	193
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	193
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	34	J721S2_DEV_MCU_R5FSS0_CORE0	intr	194
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	194
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	35	J721S2_DEV_MCU_R5FSS0_CORE0	intr	195
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	195
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	36	J721S2_DEV_MCU_R5FSS0_CORE0	intr	196
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	196
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	37	J721S2_DEV_MCU_R5FSS0_CORE0	intr	197
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	197
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	38	J721S2_DEV_MCU_R5FSS0_CORE0	intr	198
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	198
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	39	J721S2_DEV_MCU_R5FSS0_CORE0	intr	199
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	199
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	40	J721S2_DEV_MCU_R5FSS0_CORE0	intr	200
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	200
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	41	J721S2_DEV_MCU_R5FSS0_CORE0	intr	201
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	201
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	42	J721S2_DEV_MCU_R5FSS0_CORE0	intr	202
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	202
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	43	J721S2_DEV_MCU_R5FSS0_CORE0	intr	203
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	203
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	44	J721S2_DEV_MCU_R5FSS0_CORE0	intr	204
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	204
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	45	J721S2_DEV_MCU_R5FSS0_CORE0	intr	205
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	205
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	46	J721S2_DEV_MCU_R5FSS0_CORE0	intr	206
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	206
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	47	J721S2_DEV_MCU_R5FSS0_CORE0	intr	207
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	207
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	48	J721S2_DEV_MCU_R5FSS0_CORE0	intr	208
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	208
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	49	J721S2_DEV_MCU_R5FSS0_CORE0	intr	209
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	209
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	50	J721S2_DEV_MCU_R5FSS0_CORE0	intr	210
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	210
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	51	J721S2_DEV_MCU_R5FSS0_CORE0	intr	211
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	211
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	52	J721S2_DEV_MCU_R5FSS0_CORE0	intr	212
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	212
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	53	J721S2_DEV_MCU_R5FSS0_CORE0	intr	213
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	213
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	54	J721S2_DEV_MCU_R5FSS0_CORE0	intr	214
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	214
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	55	J721S2_DEV_MCU_R5FSS0_CORE0	intr	215
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	215
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	56	J721S2_DEV_MCU_R5FSS0_CORE0	intr	216
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	216
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	56	J721S2_DEV_WKUP_HSM0	nvic	64
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	57	J721S2_DEV_MCU_R5FSS0_CORE0	intr	217
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	217
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	57	J721S2_DEV_WKUP_HSM0	nvic	65
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	58	J721S2_DEV_MCU_R5FSS0_CORE0	intr	218
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	218
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	58	J721S2_DEV_WKUP_HSM0	nvic	66
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	59	J721S2_DEV_MCU_R5FSS0_CORE0	intr	219
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	219
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	59	J721S2_DEV_WKUP_HSM0	nvic	67
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	60	J721S2_DEV_MCU_R5FSS0_CORE0	intr	220
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	220
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	60	J721S2_DEV_WKUP_HSM0	nvic	68
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	61	J721S2_DEV_MCU_R5FSS0_CORE0	intr	221
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	221
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	61	J721S2_DEV_WKUP_HSM0	nvic	69
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	62	J721S2_DEV_MCU_R5FSS0_CORE0	intr	222
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	222
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	62	J721S2_DEV_WKUP_HSM0	nvic	70
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	63	J721S2_DEV_MCU_R5FSS0_CORE0	intr	223
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	223
J721S2_DEV_MAIN2MCU_LVL_INTRTR0	121	63	J721S2_DEV_WKUP_HSM0	nvic	71

MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	0	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	1	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	2	J721S2_DEV_EPWM0	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	3	J721S2_DEV_EPWM1	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	4	J721S2_DEV_EPWM2	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	5	J721S2_DEV_EPWM3	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	6	J721S2_DEV_EPWM4	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	7	J721S2_DEV_EPWM5	epwm_etint	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	8	J721S2_DEV_EPWM0	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	9	J721S2_DEV_EPWM1	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	10	J721S2_DEV_EPWM2	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	11	J721S2_DEV_EPWM3	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	12	J721S2_DEV_EPWM4	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	13	J721S2_DEV_EPWM5	epwm_tripzint	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	14	J721S2_DEV_EQEP0	eqep_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	15	J721S2_DEV_EQEP1	eqep_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	16	J721S2_DEV_EQEP2	eqep_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	17	J721S2_DEV_ECAP0	ecap_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	18	J721S2_DEV_ECAP1	ecap_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	19	J721S2_DEV_ECAP2	ecap_int	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	20	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	21	J721S2_DEV_PCIE1	pcie_dpa_pulse	6
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	22	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	23	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	24	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	25	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	26	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	27	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	28	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	29	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	30	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	31	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	32	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	33	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	34	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	35	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	36	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	37	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	38	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	39	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	40	J721S2_DEV_PCIE1	pcie_legacy_pulse	10
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	41	J721S2_DEV_PCIE1	pcie_downstream_pulse	5
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	42	J721S2_DEV_PCIE1	pcie_flr_pulse	8
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	43	J721S2_DEV_PCIE1	pcie_error_pulse	7
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	44	J721S2_DEV_PCIE1	pcie_link_state_pulse	11
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	45	J721S2_DEV_PCIE1	pcie_pwr_state_pulse	15
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	46	J721S2_DEV_PCIE1	pcie_ptm_valid_pulse	14
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	47	J721S2_DEV_PCIE1	pcie_hot_reset_pulse	9
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	48	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	49	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	50	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	51	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	52	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	53	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	54	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	55	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	56	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	57	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	58	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	59	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	60	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	61	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	62	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	63	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	64	J721S2_DEV_GPIOMUX_INTRTR0	outp	0
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	65	J721S2_DEV_GPIOMUX_INTRTR0	outp	1
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	66	J721S2_DEV_GPIOMUX_INTRTR0	outp	2
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	67	J721S2_DEV_GPIOMUX_INTRTR0	outp	3
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	68	J721S2_DEV_GPIOMUX_INTRTR0	outp	4
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	69	J721S2_DEV_GPIOMUX_INTRTR0	outp	5
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	70	J721S2_DEV_GPIOMUX_INTRTR0	outp	6
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	71	J721S2_DEV_GPIOMUX_INTRTR0	outp	7
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	72	J721S2_DEV_GPIOMUX_INTRTR0	outp	8
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	73	J721S2_DEV_GPIOMUX_INTRTR0	outp	9
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	74	J721S2_DEV_GPIOMUX_INTRTR0	outp	10
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	75	J721S2_DEV_GPIOMUX_INTRTR0	outp	11
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	76	J721S2_DEV_GPIOMUX_INTRTR0	outp	12
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	77	J721S2_DEV_GPIOMUX_INTRTR0	outp	13
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	78	J721S2_DEV_GPIOMUX_INTRTR0	outp	14
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	79	J721S2_DEV_GPIOMUX_INTRTR0	outp	15
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	80	J721S2_DEV_GPIOMUX_INTRTR0	outp	16
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	81	J721S2_DEV_GPIOMUX_INTRTR0	outp	17
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	82	J721S2_DEV_GPIOMUX_INTRTR0	outp	18
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	83	J721S2_DEV_GPIOMUX_INTRTR0	outp	19
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	84	J721S2_DEV_GPIOMUX_INTRTR0	outp	20
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	85	J721S2_DEV_GPIOMUX_INTRTR0	outp	21
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	86	J721S2_DEV_GPIOMUX_INTRTR0	outp	22
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	87	J721S2_DEV_GPIOMUX_INTRTR0	outp	23
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	88	J721S2_DEV_GPIOMUX_INTRTR0	outp	24
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	89	J721S2_DEV_GPIOMUX_INTRTR0	outp	25
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	90	J721S2_DEV_GPIOMUX_INTRTR0	outp	26
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	91	J721S2_DEV_GPIOMUX_INTRTR0	outp	27
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	92	J721S2_DEV_GPIOMUX_INTRTR0	outp	28
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	93	J721S2_DEV_GPIOMUX_INTRTR0	outp	29
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	94	J721S2_DEV_GPIOMUX_INTRTR0	outp	30
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	95	J721S2_DEV_GPIOMUX_INTRTR0	outp	31
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	96	J721S2_DEV_CMPEVENT_INTRTR0	outp	4
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	97	J721S2_DEV_CMPEVENT_INTRTR0	outp	5
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	98	J721S2_DEV_CMPEVENT_INTRTR0	outp	6
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	99	J721S2_DEV_CMPEVENT_INTRTR0	outp	7
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	100	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	101	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	102	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	103	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	104	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	105	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	106	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	107	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	108	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	109	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	110	Use TRM - Not managed by TISCI
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	111	Use TRM - Not managed by TISCI

MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	0	J721S2_DEV_MCU_R5FSS0_CORE0	intr	224
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	224
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	1	J721S2_DEV_MCU_R5FSS0_CORE0	intr	225
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	225
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	2	J721S2_DEV_MCU_R5FSS0_CORE0	intr	226
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	226
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	3	J721S2_DEV_MCU_R5FSS0_CORE0	intr	227
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	227
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	4	J721S2_DEV_MCU_R5FSS0_CORE0	intr	228
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	228
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	5	J721S2_DEV_MCU_R5FSS0_CORE0	intr	229
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	229
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	6	J721S2_DEV_MCU_R5FSS0_CORE0	intr	230
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	230
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	7	J721S2_DEV_MCU_R5FSS0_CORE0	intr	231
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	231
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	8	J721S2_DEV_MCU_R5FSS0_CORE0	intr	232
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	232
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	9	J721S2_DEV_MCU_R5FSS0_CORE0	intr	233
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	233
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	10	J721S2_DEV_MCU_R5FSS0_CORE0	intr	234
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	234
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	11	J721S2_DEV_MCU_R5FSS0_CORE0	intr	235
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	235
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	12	J721S2_DEV_MCU_R5FSS0_CORE0	intr	236
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	236
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	13	J721S2_DEV_MCU_R5FSS0_CORE0	intr	237
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	237
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	14	J721S2_DEV_MCU_R5FSS0_CORE0	intr	238
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	238
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	15	J721S2_DEV_MCU_R5FSS0_CORE0	intr	239
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	239
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	16	J721S2_DEV_MCU_R5FSS0_CORE0	intr	240
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	240
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	17	J721S2_DEV_MCU_R5FSS0_CORE0	intr	241
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	241
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	18	J721S2_DEV_MCU_R5FSS0_CORE0	intr	242
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	242
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	19	J721S2_DEV_MCU_R5FSS0_CORE0	intr	243
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	243
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	20	J721S2_DEV_MCU_R5FSS0_CORE0	intr	244
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	244
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	21	J721S2_DEV_MCU_R5FSS0_CORE0	intr	245
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	245
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	22	J721S2_DEV_MCU_R5FSS0_CORE0	intr	246
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	246
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	23	J721S2_DEV_MCU_R5FSS0_CORE0	intr	247
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	247
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	24	J721S2_DEV_MCU_R5FSS0_CORE0	intr	248
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	248
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	25	J721S2_DEV_MCU_R5FSS0_CORE0	intr	249
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	249
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	26	J721S2_DEV_MCU_R5FSS0_CORE0	intr	250
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	250
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	27	J721S2_DEV_MCU_R5FSS0_CORE0	intr	251
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	251
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	28	J721S2_DEV_MCU_R5FSS0_CORE0	intr	252
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	252
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	29	J721S2_DEV_MCU_R5FSS0_CORE0	intr	253
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	253
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	30	J721S2_DEV_MCU_R5FSS0_CORE0	intr	254
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	254
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	31	J721S2_DEV_MCU_R5FSS0_CORE0	intr	255
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	255
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	32	J721S2_DEV_MCU_R5FSS0_CORE0	intr	256
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	256
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	33	J721S2_DEV_MCU_R5FSS0_CORE0	intr	257
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	257
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	34	J721S2_DEV_MCU_R5FSS0_CORE0	intr	258
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	258
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	35	J721S2_DEV_MCU_R5FSS0_CORE0	intr	259
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	259
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	36	J721S2_DEV_MCU_R5FSS0_CORE0	intr	260
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	260
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	37	J721S2_DEV_MCU_R5FSS0_CORE0	intr	261
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	261
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	38	J721S2_DEV_MCU_R5FSS0_CORE0	intr	262
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	262
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	39	J721S2_DEV_MCU_R5FSS0_CORE0	intr	263
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	263
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	40	J721S2_DEV_MCU_R5FSS0_CORE0	intr	264
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	264
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	40	J721S2_DEV_WKUP_HSM0	nvic	72
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	41	J721S2_DEV_MCU_R5FSS0_CORE0	intr	265
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	265
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	41	J721S2_DEV_WKUP_HSM0	nvic	73
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	42	J721S2_DEV_MCU_R5FSS0_CORE0	intr	266
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	266
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	42	J721S2_DEV_WKUP_HSM0	nvic	74
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	43	J721S2_DEV_MCU_R5FSS0_CORE0	intr	267
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	267
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	43	J721S2_DEV_WKUP_HSM0	nvic	75
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	44	J721S2_DEV_MCU_R5FSS0_CORE0	intr	268
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	268
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	44	J721S2_DEV_WKUP_HSM0	nvic	76
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	45	J721S2_DEV_MCU_R5FSS0_CORE0	intr	269
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	269
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	45	J721S2_DEV_WKUP_HSM0	nvic	77
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	46	J721S2_DEV_MCU_R5FSS0_CORE0	intr	270
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	270
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	46	J721S2_DEV_WKUP_HSM0	nvic	78
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	47	J721S2_DEV_MCU_R5FSS0_CORE0	intr	271
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	271
J721S2_DEV_MAIN2MCU_PLS_INTRTR0	122	47	J721S2_DEV_WKUP_HSM0	nvic	79

TIMESYNC_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_TIMESYNC_INTRTR0	124	0	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	1	J721S2_DEV_GTC0	gtc_push_event	0
J721S2_DEV_TIMESYNC_INTRTR0	124	2	J721S2_DEV_TIMER14	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	3	J721S2_DEV_TIMER15	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	4	J721S2_DEV_NAVSS0	cpts0_genf0	1
J721S2_DEV_TIMESYNC_INTRTR0	124	5	J721S2_DEV_NAVSS0	cpts0_genf1	2
J721S2_DEV_TIMESYNC_INTRTR0	124	6	J721S2_DEV_NAVSS0	cpts0_genf2	3
J721S2_DEV_TIMESYNC_INTRTR0	124	7	J721S2_DEV_NAVSS0	cpts0_genf3	4
J721S2_DEV_TIMESYNC_INTRTR0	124	8	J721S2_DEV_NAVSS0	cpts0_genf4	5
J721S2_DEV_TIMESYNC_INTRTR0	124	9	J721S2_DEV_NAVSS0	cpts0_genf5	6
J721S2_DEV_TIMESYNC_INTRTR0	124	10	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	11	J721S2_DEV_PCIE1	pcie_cpts_genf0	1
J721S2_DEV_TIMESYNC_INTRTR0	124	12	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	13	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	14	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	15	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	16	J721S2_DEV_MCU_CPSW0	cpts_genf0	1
J721S2_DEV_TIMESYNC_INTRTR0	124	17	J721S2_DEV_MCU_CPSW0	cpts_genf1	2
J721S2_DEV_TIMESYNC_INTRTR0	124	18	J721S2_DEV_CPSW1	cpts_genf0	1
J721S2_DEV_TIMESYNC_INTRTR0	124	19	J721S2_DEV_CPSW1	cpts_genf1	2
J721S2_DEV_TIMESYNC_INTRTR0	124	20	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	21	J721S2_DEV_PCIE1	pcie_cpts_hw1_push	2
J721S2_DEV_TIMESYNC_INTRTR0	124	22	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	23	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	24	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	25	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	26	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	27	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	28	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	29	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	30	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	31	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	32	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	33	J721S2_DEV_PCIE1	pcie_cpts_sync	4
J721S2_DEV_TIMESYNC_INTRTR0	124	34	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	35	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	36	J721S2_DEV_NAVSS0	cpts0_sync	7
J721S2_DEV_TIMESYNC_INTRTR0	124	37	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	38	J721S2_DEV_MCU_CPSW0	cpts_sync	3
J721S2_DEV_TIMESYNC_INTRTR0	124	39	J721S2_DEV_CPSW1	cpts_sync	3
J721S2_DEV_TIMESYNC_INTRTR0	124	40	J721S2_DEV_TIMER16	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	41	J721S2_DEV_TIMER17	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	42	J721S2_DEV_TIMER18	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	43	J721S2_DEV_TIMER19	timer_pwm	1
J721S2_DEV_TIMESYNC_INTRTR0	124	44	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	45	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	46	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	47	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	48	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	49	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	50	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	51	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	52	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	53	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	54	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	55	Use TRM - Not managed by TISCI

TIMESYNC_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_TIMESYNC_INTRTR0	124	0	J721S2_DEV_NAVSS0	cpts0_hw1_push	0
J721S2_DEV_TIMESYNC_INTRTR0	124	1	J721S2_DEV_NAVSS0	cpts0_hw2_push	1
J721S2_DEV_TIMESYNC_INTRTR0	124	2	J721S2_DEV_NAVSS0	cpts0_hw3_push	2
J721S2_DEV_TIMESYNC_INTRTR0	124	3	J721S2_DEV_NAVSS0	cpts0_hw4_push	3
J721S2_DEV_TIMESYNC_INTRTR0	124	4	J721S2_DEV_NAVSS0	cpts0_hw5_push	4
J721S2_DEV_TIMESYNC_INTRTR0	124	5	J721S2_DEV_NAVSS0	cpts0_hw6_push	5
J721S2_DEV_TIMESYNC_INTRTR0	124	6	J721S2_DEV_NAVSS0	cpts0_hw7_push	6
J721S2_DEV_TIMESYNC_INTRTR0	124	7	J721S2_DEV_NAVSS0	cpts0_hw8_push	7
J721S2_DEV_TIMESYNC_INTRTR0	124	8	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	9	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	10	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	11	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	12	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	13	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	14	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	15	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	16	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	17	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	18	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	19	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	20	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	21	J721S2_DEV_PCIE1	pcie_cpts_hw2_push	0
J721S2_DEV_TIMESYNC_INTRTR0	124	22	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	23	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	24	J721S2_DEV_MCU_CPSW0	cpts_hw3_push	0
J721S2_DEV_TIMESYNC_INTRTR0	124	25	J721S2_DEV_MCU_CPSW0	cpts_hw4_push	1
J721S2_DEV_TIMESYNC_INTRTR0	124	26	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	27	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	28	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	29	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	30	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	31	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	32	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	33	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	34	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	35	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	36	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	37	Use TRM - Not managed by TISCI
J721S2_DEV_TIMESYNC_INTRTR0	124	38	J721S2_DEV_CPSW1	cpts_hw3_push	0
J721S2_DEV_TIMESYNC_INTRTR0	124	39	J721S2_DEV_CPSW1	cpts_hw4_push	1
J721S2_DEV_TIMESYNC_INTRTR0	124	40	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	100
J721S2_DEV_TIMESYNC_INTRTR0	124	41	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	101
J721S2_DEV_TIMESYNC_INTRTR0	124	42	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	102
J721S2_DEV_TIMESYNC_INTRTR0	124	43	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	103
J721S2_DEV_TIMESYNC_INTRTR0	124	44	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	104
J721S2_DEV_TIMESYNC_INTRTR0	124	45	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	105
J721S2_DEV_TIMESYNC_INTRTR0	124	46	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	106
J721S2_DEV_TIMESYNC_INTRTR0	124	47	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	107

WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	0	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	1	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	2	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	3	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	4	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	5	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	6	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	7	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	8	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	9	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	10	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	11	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	12	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	13	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	14	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	15	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	16	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	17	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	18	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	19	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	20	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	21	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	22	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	23	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	24	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	25	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	26	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	27	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	28	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	29	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	30	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	31	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	32	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	33	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	34	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	35	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	36	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	37	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	38	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	39	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	40	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	41	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	42	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	43	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	44	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	45	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	46	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	47	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	48	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	49	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	50	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	51	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	52	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	53	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	54	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	55	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	56	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	57	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	58	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	59	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	60	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	61	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	62	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	63	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	64	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	65	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	66	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	67	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	68	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	69	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	70	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	71	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	72	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	73	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	74	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	75	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	76	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	77	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	78	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	79	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	80	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	81	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	82	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	83	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	84	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	85	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	86	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	87	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	88	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	89	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	90	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	91	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	92	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	93	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	94	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	95	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	96	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	97	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	98	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	99	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	100	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	101	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	102	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	103	J721S2_DEV_WKUP_GPIO0	gpio_bank	0
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	104	J721S2_DEV_WKUP_GPIO0	gpio_bank	1
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	105	J721S2_DEV_WKUP_GPIO0	gpio_bank	2
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	106	J721S2_DEV_WKUP_GPIO0	gpio_bank	3
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	107	J721S2_DEV_WKUP_GPIO0	gpio_bank	4
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	108	J721S2_DEV_WKUP_GPIO0	gpio_bank	5
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	109	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	110	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	111	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	112	J721S2_DEV_WKUP_GPIO1	gpio_bank	0
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	113	J721S2_DEV_WKUP_GPIO1	gpio_bank	1
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	114	J721S2_DEV_WKUP_GPIO1	gpio_bank	2
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	115	J721S2_DEV_WKUP_GPIO1	gpio_bank	3
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	116	J721S2_DEV_WKUP_GPIO1	gpio_bank	4
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	117	J721S2_DEV_WKUP_GPIO1	gpio_bank	5
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	118	Use TRM - Not managed by TISCI
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	119	Use TRM - Not managed by TISCI

WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	0	J721S2_DEV_MCU_R5FSS0_CORE0	intr	124
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	124
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	0	J721S2_DEV_WKUP_HSM0	nvic	184
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	1	J721S2_DEV_MCU_R5FSS0_CORE0	intr	125
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	125
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	1	J721S2_DEV_WKUP_HSM0	nvic	185
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	2	J721S2_DEV_MCU_R5FSS0_CORE0	intr	126
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	126
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	2	J721S2_DEV_WKUP_HSM0	nvic	186
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	3	J721S2_DEV_MCU_R5FSS0_CORE0	intr	127
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	127
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	3	J721S2_DEV_WKUP_HSM0	nvic	187
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	4	J721S2_DEV_MCU_R5FSS0_CORE0	intr	128
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	128
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	4	J721S2_DEV_WKUP_HSM0	nvic	188
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	5	J721S2_DEV_MCU_R5FSS0_CORE0	intr	129
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	129
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	5	J721S2_DEV_WKUP_HSM0	nvic	189
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	6	J721S2_DEV_MCU_R5FSS0_CORE0	intr	130
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	130
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	6	J721S2_DEV_WKUP_HSM0	nvic	190
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	7	J721S2_DEV_MCU_R5FSS0_CORE0	intr	131
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	131
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	7	J721S2_DEV_WKUP_HSM0	nvic	191
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	8	J721S2_DEV_WKUP_ESM0	esm_pls_event0	120
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	128
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	8	J721S2_DEV_WKUP_ESM0	esm_pls_event2	136
			J721S2_DEV_MCU_R5FSS0_CORE0	intr	132
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	8	J721S2_DEV_MCU_R5FSS0_CORE1	intr	132
			J721S2_DEV_WKUP_HSM0	nvic	192
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	9	J721S2_DEV_WKUP_ESM0	esm_pls_event0	121
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	129
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	9	J721S2_DEV_WKUP_ESM0	esm_pls_event2	137
			J721S2_DEV_MCU_R5FSS0_CORE0	intr	133
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	9	J721S2_DEV_MCU_R5FSS0_CORE1	intr	133
			J721S2_DEV_WKUP_HSM0	nvic	193
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	10	J721S2_DEV_WKUP_ESM0	esm_pls_event0	122
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	130
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	10	J721S2_DEV_WKUP_ESM0	esm_pls_event2	138
			J721S2_DEV_MCU_R5FSS0_CORE0	intr	134
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	10	J721S2_DEV_MCU_R5FSS0_CORE1	intr	134
			J721S2_DEV_WKUP_HSM0	nvic	194
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	11	J721S2_DEV_WKUP_ESM0	esm_pls_event0	123
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	131
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	11	J721S2_DEV_WKUP_ESM0	esm_pls_event2	139
			J721S2_DEV_MCU_R5FSS0_CORE0	intr	135
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	11	J721S2_DEV_MCU_R5FSS0_CORE1	intr	135
			J721S2_DEV_WKUP_HSM0	nvic	195
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	12	J721S2_DEV_WKUP_ESM0	esm_pls_event0	124
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	132
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	12	J721S2_DEV_WKUP_ESM0	esm_pls_event2	140
			J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	4
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	12	J721S2_DEV_MCU_R5FSS0_CORE0	intr	136
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	136
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	13	J721S2_DEV_WKUP_ESM0	esm_pls_event0	125
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	133
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	13	J721S2_DEV_WKUP_ESM0	esm_pls_event2	141
			J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	5
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	13	J721S2_DEV_MCU_R5FSS0_CORE0	intr	137
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	137
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	14	J721S2_DEV_WKUP_ESM0	esm_pls_event0	126
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	134
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	14	J721S2_DEV_WKUP_ESM0	esm_pls_event2	142
			J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	6
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	14	J721S2_DEV_MCU_R5FSS0_CORE0	intr	138
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	138
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	15	J721S2_DEV_WKUP_ESM0	esm_pls_event0	127
			J721S2_DEV_WKUP_ESM0	esm_pls_event1	135
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	15	J721S2_DEV_WKUP_ESM0	esm_pls_event2	143
			J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	7
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	15	J721S2_DEV_MCU_R5FSS0_CORE0	intr	139
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	139
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	16	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	960
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	960
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	16	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	8
			J721S2_DEV_R5FSS0_CORE0	intr	488
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	16	J721S2_DEV_R5FSS0_CORE1	intr	488
			J721S2_DEV_R5FSS1_CORE0	intr	488
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	16	J721S2_DEV_R5FSS1_CORE1	intr	488
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	17	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	961
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	961
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	17	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	9
			J721S2_DEV_R5FSS0_CORE0	intr	489
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	17	J721S2_DEV_R5FSS0_CORE1	intr	489
			J721S2_DEV_R5FSS1_CORE0	intr	489
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	17	J721S2_DEV_R5FSS1_CORE1	intr	489
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	18	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	962
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	962
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	18	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	10
			J721S2_DEV_R5FSS0_CORE0	intr	490
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	18	J721S2_DEV_R5FSS0_CORE1	intr	490
			J721S2_DEV_R5FSS1_CORE0	intr	490
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	18	J721S2_DEV_R5FSS1_CORE1	intr	490
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	19	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	963
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	963
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	19	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	11
			J721S2_DEV_R5FSS0_CORE0	intr	491
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	19	J721S2_DEV_R5FSS0_CORE1	intr	491
			J721S2_DEV_R5FSS1_CORE0	intr	491
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	19	J721S2_DEV_R5FSS1_CORE1	intr	491
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	20	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	964
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	964
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	20	J721S2_DEV_R5FSS0_CORE0	intr	492
			J721S2_DEV_R5FSS0_CORE1	intr	492
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	20	J721S2_DEV_R5FSS1_CORE0	intr	492
			J721S2_DEV_R5FSS1_CORE1	intr	492
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	21	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	965
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	965
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	21	J721S2_DEV_R5FSS0_CORE0	intr	493
			J721S2_DEV_R5FSS0_CORE1	intr	493
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	21	J721S2_DEV_R5FSS1_CORE0	intr	493
			J721S2_DEV_R5FSS1_CORE1	intr	493
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	22	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	966
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	966
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	22	J721S2_DEV_R5FSS0_CORE0	intr	494
			J721S2_DEV_R5FSS0_CORE1	intr	494
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	22	J721S2_DEV_R5FSS1_CORE0	intr	494
			J721S2_DEV_R5FSS1_CORE1	intr	494
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	23	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	967
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	967
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	23	J721S2_DEV_R5FSS0_CORE0	intr	495
			J721S2_DEV_R5FSS0_CORE1	intr	495
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	23	J721S2_DEV_R5FSS1_CORE0	intr	495
			J721S2_DEV_R5FSS1_CORE1	intr	495
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	24	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	968
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	968
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	24	J721S2_DEV_R5FSS0_CORE0	intr	496
			J721S2_DEV_R5FSS0_CORE1	intr	496
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	24	J721S2_DEV_R5FSS1_CORE0	intr	496
			J721S2_DEV_R5FSS1_CORE1	intr	496
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	25	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	969
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	969
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	25	J721S2_DEV_R5FSS0_CORE0	intr	497
			J721S2_DEV_R5FSS0_CORE1	intr	497
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	25	J721S2_DEV_R5FSS1_CORE0	intr	497
			J721S2_DEV_R5FSS1_CORE1	intr	497
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	26	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	970
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	970
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	26	J721S2_DEV_R5FSS0_CORE0	intr	498
			J721S2_DEV_R5FSS0_CORE1	intr	498
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	26	J721S2_DEV_R5FSS1_CORE0	intr	498
			J721S2_DEV_R5FSS1_CORE1	intr	498
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	27	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	971
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	971
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	27	J721S2_DEV_R5FSS0_CORE0	intr	499
			J721S2_DEV_R5FSS0_CORE1	intr	499
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	27	J721S2_DEV_R5FSS1_CORE0	intr	499
			J721S2_DEV_R5FSS1_CORE1	intr	499
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	28	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	972
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	972
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	28	J721S2_DEV_R5FSS0_CORE0	intr	500
			J721S2_DEV_R5FSS0_CORE1	intr	500
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	28	J721S2_DEV_R5FSS1_CORE0	intr	500
			J721S2_DEV_R5FSS1_CORE1	intr	500
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	29	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	973
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	973
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	29	J721S2_DEV_R5FSS0_CORE0	intr	501
			J721S2_DEV_R5FSS0_CORE1	intr	501
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	29	J721S2_DEV_R5FSS1_CORE0	intr	501
			J721S2_DEV_R5FSS1_CORE1	intr	501
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	30	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	974
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	974
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	30	J721S2_DEV_R5FSS0_CORE0	intr	502
			J721S2_DEV_R5FSS0_CORE1	intr	502
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	30	J721S2_DEV_R5FSS1_CORE0	intr	502
			J721S2_DEV_R5FSS1_CORE1	intr	502
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	31	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	975
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	975
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	31	J721S2_DEV_R5FSS0_CORE0	intr	503
			J721S2_DEV_R5FSS0_CORE1	intr	503
J721S2_DEV_WKUP_GPIOMUX_INTRTR0	125	31	J721S2_DEV_R5FSS1_CORE0	intr	503
			J721S2_DEV_R5FSS1_CORE1	intr	503

GPIOMUX_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_GPIOMUX_INTRTR0	148	0	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	1	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	2	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	3	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	4	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	5	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	6	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	7	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	8	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	9	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	10	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	11	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	12	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	13	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	14	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	15	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	16	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	17	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	18	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	19	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	20	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	21	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	22	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	23	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	24	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	25	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	26	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	27	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	28	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	29	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	30	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	31	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	32	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	33	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	34	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	35	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	36	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	37	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	38	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	39	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	40	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	41	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	42	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	43	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	44	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	45	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	46	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	47	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	48	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	49	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	50	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	51	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	52	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	53	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	54	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	55	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	56	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	57	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	58	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	59	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	60	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	61	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	62	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	63	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	64	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	65	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	66	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	67	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	68	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	69	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	70	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	71	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	72	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	73	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	74	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	75	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	76	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	77	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	78	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	79	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	80	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	81	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	82	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	83	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	84	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	85	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	86	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	87	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	88	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	89	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	90	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	91	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	92	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	93	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	94	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	95	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	96	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	97	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	98	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	99	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	100	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	101	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	102	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	103	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	104	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	105	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	106	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	107	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	108	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	109	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	110	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	111	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	112	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	113	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	114	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	115	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	116	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	117	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	118	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	119	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	120	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	121	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	122	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	123	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	124	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	125	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	126	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	127	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	128	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	129	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	130	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	131	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	132	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	133	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	134	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	135	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	136	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	137	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	138	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	139	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	140	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	141	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	142	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	143	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	144	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	145	J721S2_DEV_GPIO0	gpio_bank	0
J721S2_DEV_GPIOMUX_INTRTR0	148	146	J721S2_DEV_GPIO0	gpio_bank	1
J721S2_DEV_GPIOMUX_INTRTR0	148	147	J721S2_DEV_GPIO0	gpio_bank	2
J721S2_DEV_GPIOMUX_INTRTR0	148	148	J721S2_DEV_GPIO0	gpio_bank	3
J721S2_DEV_GPIOMUX_INTRTR0	148	149	J721S2_DEV_GPIO0	gpio_bank	4
J721S2_DEV_GPIOMUX_INTRTR0	148	150	J721S2_DEV_GPIO0	gpio_bank	5
J721S2_DEV_GPIOMUX_INTRTR0	148	151	J721S2_DEV_GPIO0	gpio_bank	6
J721S2_DEV_GPIOMUX_INTRTR0	148	152	J721S2_DEV_GPIO0	gpio_bank	7
J721S2_DEV_GPIOMUX_INTRTR0	148	153	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	154	J721S2_DEV_GPIO2	gpio_bank	0
J721S2_DEV_GPIOMUX_INTRTR0	148	155	J721S2_DEV_GPIO2	gpio_bank	1
J721S2_DEV_GPIOMUX_INTRTR0	148	156	J721S2_DEV_GPIO2	gpio_bank	2
J721S2_DEV_GPIOMUX_INTRTR0	148	157	J721S2_DEV_GPIO2	gpio_bank	3
J721S2_DEV_GPIOMUX_INTRTR0	148	158	J721S2_DEV_GPIO2	gpio_bank	4
J721S2_DEV_GPIOMUX_INTRTR0	148	159	J721S2_DEV_GPIO2	gpio_bank	5
J721S2_DEV_GPIOMUX_INTRTR0	148	160	J721S2_DEV_GPIO2	gpio_bank	6
J721S2_DEV_GPIOMUX_INTRTR0	148	161	J721S2_DEV_GPIO2	gpio_bank	7
J721S2_DEV_GPIOMUX_INTRTR0	148	162	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	163	J721S2_DEV_GPIO4	gpio_bank	0
J721S2_DEV_GPIOMUX_INTRTR0	148	164	J721S2_DEV_GPIO4	gpio_bank	1
J721S2_DEV_GPIOMUX_INTRTR0	148	165	J721S2_DEV_GPIO4	gpio_bank	2
J721S2_DEV_GPIOMUX_INTRTR0	148	166	J721S2_DEV_GPIO4	gpio_bank	3
J721S2_DEV_GPIOMUX_INTRTR0	148	167	J721S2_DEV_GPIO4	gpio_bank	4
J721S2_DEV_GPIOMUX_INTRTR0	148	168	J721S2_DEV_GPIO4	gpio_bank	5
J721S2_DEV_GPIOMUX_INTRTR0	148	169	J721S2_DEV_GPIO4	gpio_bank	6
J721S2_DEV_GPIOMUX_INTRTR0	148	170	J721S2_DEV_GPIO4	gpio_bank	7
J721S2_DEV_GPIOMUX_INTRTR0	148	171	Use TRM - Not managed by TISCI
J721S2_DEV_GPIOMUX_INTRTR0	148	172	J721S2_DEV_GPIO6	gpio_bank	0
J721S2_DEV_GPIOMUX_INTRTR0	148	173	J721S2_DEV_GPIO6	gpio_bank	1
J721S2_DEV_GPIOMUX_INTRTR0	148	174	J721S2_DEV_GPIO6	gpio_bank	2
J721S2_DEV_GPIOMUX_INTRTR0	148	175	J721S2_DEV_GPIO6	gpio_bank	3
J721S2_DEV_GPIOMUX_INTRTR0	148	176	J721S2_DEV_GPIO6	gpio_bank	4
J721S2_DEV_GPIOMUX_INTRTR0	148	177	J721S2_DEV_GPIO6	gpio_bank	5
J721S2_DEV_GPIOMUX_INTRTR0	148	178	J721S2_DEV_GPIO6	gpio_bank	6
J721S2_DEV_GPIOMUX_INTRTR0	148	179	J721S2_DEV_GPIO6	gpio_bank	7

GPIOMUX_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_GPIOMUX_INTRTR0	148	0	J721S2_DEV_ESM0	esm_pls_event0	664
			J721S2_DEV_ESM0	esm_pls_event1	672
J721S2_DEV_GPIOMUX_INTRTR0	148	0	J721S2_DEV_ESM0	esm_pls_event2	680
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	64
J721S2_DEV_GPIOMUX_INTRTR0	148	0	J721S2_DEV_R5FSS0_CORE0	intr	396
			J721S2_DEV_R5FSS0_CORE1	intr	396
J721S2_DEV_GPIOMUX_INTRTR0	148	0	J721S2_DEV_R5FSS1_CORE0	intr	396
			J721S2_DEV_R5FSS1_CORE1	intr	396
J721S2_DEV_GPIOMUX_INTRTR0	148	1	J721S2_DEV_ESM0	esm_pls_event0	665
			J721S2_DEV_ESM0	esm_pls_event1	673
J721S2_DEV_GPIOMUX_INTRTR0	148	1	J721S2_DEV_ESM0	esm_pls_event2	681
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	65
J721S2_DEV_GPIOMUX_INTRTR0	148	1	J721S2_DEV_R5FSS0_CORE0	intr	397
			J721S2_DEV_R5FSS0_CORE1	intr	397
J721S2_DEV_GPIOMUX_INTRTR0	148	1	J721S2_DEV_R5FSS1_CORE0	intr	397
			J721S2_DEV_R5FSS1_CORE1	intr	397
J721S2_DEV_GPIOMUX_INTRTR0	148	2	J721S2_DEV_ESM0	esm_pls_event0	666
			J721S2_DEV_ESM0	esm_pls_event1	674
J721S2_DEV_GPIOMUX_INTRTR0	148	2	J721S2_DEV_ESM0	esm_pls_event2	682
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	66
J721S2_DEV_GPIOMUX_INTRTR0	148	2	J721S2_DEV_R5FSS0_CORE0	intr	398
			J721S2_DEV_R5FSS0_CORE1	intr	398
J721S2_DEV_GPIOMUX_INTRTR0	148	2	J721S2_DEV_R5FSS1_CORE0	intr	398
			J721S2_DEV_R5FSS1_CORE1	intr	398
J721S2_DEV_GPIOMUX_INTRTR0	148	3	J721S2_DEV_ESM0	esm_pls_event0	667
			J721S2_DEV_ESM0	esm_pls_event1	675
J721S2_DEV_GPIOMUX_INTRTR0	148	3	J721S2_DEV_ESM0	esm_pls_event2	683
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	67
J721S2_DEV_GPIOMUX_INTRTR0	148	3	J721S2_DEV_R5FSS0_CORE0	intr	399
			J721S2_DEV_R5FSS0_CORE1	intr	399
J721S2_DEV_GPIOMUX_INTRTR0	148	3	J721S2_DEV_R5FSS1_CORE0	intr	399
			J721S2_DEV_R5FSS1_CORE1	intr	399
J721S2_DEV_GPIOMUX_INTRTR0	148	4	J721S2_DEV_ESM0	esm_pls_event0	668
			J721S2_DEV_ESM0	esm_pls_event1	676
J721S2_DEV_GPIOMUX_INTRTR0	148	4	J721S2_DEV_ESM0	esm_pls_event2	684
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	68
J721S2_DEV_GPIOMUX_INTRTR0	148	4	J721S2_DEV_R5FSS0_CORE0	intr	400
			J721S2_DEV_R5FSS0_CORE1	intr	400
J721S2_DEV_GPIOMUX_INTRTR0	148	4	J721S2_DEV_R5FSS1_CORE0	intr	400
			J721S2_DEV_R5FSS1_CORE1	intr	400
J721S2_DEV_GPIOMUX_INTRTR0	148	5	J721S2_DEV_ESM0	esm_pls_event0	669
			J721S2_DEV_ESM0	esm_pls_event1	677
J721S2_DEV_GPIOMUX_INTRTR0	148	5	J721S2_DEV_ESM0	esm_pls_event2	685
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	69
J721S2_DEV_GPIOMUX_INTRTR0	148	5	J721S2_DEV_R5FSS0_CORE0	intr	401
			J721S2_DEV_R5FSS0_CORE1	intr	401
J721S2_DEV_GPIOMUX_INTRTR0	148	5	J721S2_DEV_R5FSS1_CORE0	intr	401
			J721S2_DEV_R5FSS1_CORE1	intr	401
J721S2_DEV_GPIOMUX_INTRTR0	148	6	J721S2_DEV_ESM0	esm_pls_event0	670
			J721S2_DEV_ESM0	esm_pls_event1	678
J721S2_DEV_GPIOMUX_INTRTR0	148	6	J721S2_DEV_ESM0	esm_pls_event2	686
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	70
J721S2_DEV_GPIOMUX_INTRTR0	148	6	J721S2_DEV_R5FSS0_CORE0	intr	402
			J721S2_DEV_R5FSS0_CORE1	intr	402
J721S2_DEV_GPIOMUX_INTRTR0	148	6	J721S2_DEV_R5FSS1_CORE0	intr	402
			J721S2_DEV_R5FSS1_CORE1	intr	402
J721S2_DEV_GPIOMUX_INTRTR0	148	7	J721S2_DEV_ESM0	esm_pls_event0	671
			J721S2_DEV_ESM0	esm_pls_event1	679
J721S2_DEV_GPIOMUX_INTRTR0	148	7	J721S2_DEV_ESM0	esm_pls_event2	687
			J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	71
J721S2_DEV_GPIOMUX_INTRTR0	148	7	J721S2_DEV_R5FSS0_CORE0	intr	403
			J721S2_DEV_R5FSS0_CORE1	intr	403
J721S2_DEV_GPIOMUX_INTRTR0	148	7	J721S2_DEV_R5FSS1_CORE0	intr	403
			J721S2_DEV_R5FSS1_CORE1	intr	403
J721S2_DEV_GPIOMUX_INTRTR0	148	8	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	392
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	392
J721S2_DEV_GPIOMUX_INTRTR0	148	8	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	72
			J721S2_DEV_R5FSS0_CORE0	intr	404
J721S2_DEV_GPIOMUX_INTRTR0	148	8	J721S2_DEV_R5FSS0_CORE1	intr	404
			J721S2_DEV_R5FSS1_CORE0	intr	404
J721S2_DEV_GPIOMUX_INTRTR0	148	8	J721S2_DEV_R5FSS1_CORE1	intr	404
J721S2_DEV_GPIOMUX_INTRTR0	148	9	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	393
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	393
J721S2_DEV_GPIOMUX_INTRTR0	148	9	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	73
			J721S2_DEV_R5FSS0_CORE0	intr	405
J721S2_DEV_GPIOMUX_INTRTR0	148	9	J721S2_DEV_R5FSS0_CORE1	intr	405
			J721S2_DEV_R5FSS1_CORE0	intr	405
J721S2_DEV_GPIOMUX_INTRTR0	148	9	J721S2_DEV_R5FSS1_CORE1	intr	405
J721S2_DEV_GPIOMUX_INTRTR0	148	10	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	394
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	394
J721S2_DEV_GPIOMUX_INTRTR0	148	10	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	74
			J721S2_DEV_R5FSS0_CORE0	intr	406
J721S2_DEV_GPIOMUX_INTRTR0	148	10	J721S2_DEV_R5FSS0_CORE1	intr	406
			J721S2_DEV_R5FSS1_CORE0	intr	406
J721S2_DEV_GPIOMUX_INTRTR0	148	10	J721S2_DEV_R5FSS1_CORE1	intr	406
J721S2_DEV_GPIOMUX_INTRTR0	148	11	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	395
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	395
J721S2_DEV_GPIOMUX_INTRTR0	148	11	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	75
			J721S2_DEV_R5FSS0_CORE0	intr	407
J721S2_DEV_GPIOMUX_INTRTR0	148	11	J721S2_DEV_R5FSS0_CORE1	intr	407
			J721S2_DEV_R5FSS1_CORE0	intr	407
J721S2_DEV_GPIOMUX_INTRTR0	148	11	J721S2_DEV_R5FSS1_CORE1	intr	407
J721S2_DEV_GPIOMUX_INTRTR0	148	12	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	396
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	396
J721S2_DEV_GPIOMUX_INTRTR0	148	12	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	76
			J721S2_DEV_R5FSS0_CORE0	intr	408
J721S2_DEV_GPIOMUX_INTRTR0	148	12	J721S2_DEV_R5FSS0_CORE1	intr	408
			J721S2_DEV_R5FSS1_CORE0	intr	408
J721S2_DEV_GPIOMUX_INTRTR0	148	12	J721S2_DEV_R5FSS1_CORE1	intr	408
J721S2_DEV_GPIOMUX_INTRTR0	148	13	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	397
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	397
J721S2_DEV_GPIOMUX_INTRTR0	148	13	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	77
			J721S2_DEV_R5FSS0_CORE0	intr	409
J721S2_DEV_GPIOMUX_INTRTR0	148	13	J721S2_DEV_R5FSS0_CORE1	intr	409
			J721S2_DEV_R5FSS1_CORE0	intr	409
J721S2_DEV_GPIOMUX_INTRTR0	148	13	J721S2_DEV_R5FSS1_CORE1	intr	409
J721S2_DEV_GPIOMUX_INTRTR0	148	14	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	398
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	398
J721S2_DEV_GPIOMUX_INTRTR0	148	14	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	78
			J721S2_DEV_R5FSS0_CORE0	intr	410
J721S2_DEV_GPIOMUX_INTRTR0	148	14	J721S2_DEV_R5FSS0_CORE1	intr	410
			J721S2_DEV_R5FSS1_CORE0	intr	410
J721S2_DEV_GPIOMUX_INTRTR0	148	14	J721S2_DEV_R5FSS1_CORE1	intr	410
J721S2_DEV_GPIOMUX_INTRTR0	148	15	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	399
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	399
J721S2_DEV_GPIOMUX_INTRTR0	148	15	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	79
			J721S2_DEV_R5FSS0_CORE0	intr	411
J721S2_DEV_GPIOMUX_INTRTR0	148	15	J721S2_DEV_R5FSS0_CORE1	intr	411
			J721S2_DEV_R5FSS1_CORE0	intr	411
J721S2_DEV_GPIOMUX_INTRTR0	148	15	J721S2_DEV_R5FSS1_CORE1	intr	411
J721S2_DEV_GPIOMUX_INTRTR0	148	16	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	400
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	400
J721S2_DEV_GPIOMUX_INTRTR0	148	16	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	80
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	116
J721S2_DEV_GPIOMUX_INTRTR0	148	16	J721S2_DEV_R5FSS0_CORE0	intr	176
			J721S2_DEV_R5FSS0_CORE1	intr	176
J721S2_DEV_GPIOMUX_INTRTR0	148	16	J721S2_DEV_R5FSS1_CORE0	intr	176
			J721S2_DEV_R5FSS1_CORE1	intr	176
J721S2_DEV_GPIOMUX_INTRTR0	148	17	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	401
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	401
J721S2_DEV_GPIOMUX_INTRTR0	148	17	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	81
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	117
J721S2_DEV_GPIOMUX_INTRTR0	148	17	J721S2_DEV_R5FSS0_CORE0	intr	177
			J721S2_DEV_R5FSS0_CORE1	intr	177
J721S2_DEV_GPIOMUX_INTRTR0	148	17	J721S2_DEV_R5FSS1_CORE0	intr	177
			J721S2_DEV_R5FSS1_CORE1	intr	177
J721S2_DEV_GPIOMUX_INTRTR0	148	18	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	402
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	402
J721S2_DEV_GPIOMUX_INTRTR0	148	18	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	82
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	118
J721S2_DEV_GPIOMUX_INTRTR0	148	18	J721S2_DEV_R5FSS0_CORE0	intr	178
			J721S2_DEV_R5FSS0_CORE1	intr	178
J721S2_DEV_GPIOMUX_INTRTR0	148	18	J721S2_DEV_R5FSS1_CORE0	intr	178
			J721S2_DEV_R5FSS1_CORE1	intr	178
J721S2_DEV_GPIOMUX_INTRTR0	148	19	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	403
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	403
J721S2_DEV_GPIOMUX_INTRTR0	148	19	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	83
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	119
J721S2_DEV_GPIOMUX_INTRTR0	148	19	J721S2_DEV_R5FSS0_CORE0	intr	179
			J721S2_DEV_R5FSS0_CORE1	intr	179
J721S2_DEV_GPIOMUX_INTRTR0	148	19	J721S2_DEV_R5FSS1_CORE0	intr	179
			J721S2_DEV_R5FSS1_CORE1	intr	179
J721S2_DEV_GPIOMUX_INTRTR0	148	20	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	404
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	404
J721S2_DEV_GPIOMUX_INTRTR0	148	20	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	84
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	120
J721S2_DEV_GPIOMUX_INTRTR0	148	20	J721S2_DEV_R5FSS0_CORE0	intr	180
			J721S2_DEV_R5FSS0_CORE1	intr	180
J721S2_DEV_GPIOMUX_INTRTR0	148	20	J721S2_DEV_R5FSS1_CORE0	intr	180
			J721S2_DEV_R5FSS1_CORE1	intr	180
J721S2_DEV_GPIOMUX_INTRTR0	148	21	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	405
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	405
J721S2_DEV_GPIOMUX_INTRTR0	148	21	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	85
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	121
J721S2_DEV_GPIOMUX_INTRTR0	148	21	J721S2_DEV_R5FSS0_CORE0	intr	181
			J721S2_DEV_R5FSS0_CORE1	intr	181
J721S2_DEV_GPIOMUX_INTRTR0	148	21	J721S2_DEV_R5FSS1_CORE0	intr	181
			J721S2_DEV_R5FSS1_CORE1	intr	181
J721S2_DEV_GPIOMUX_INTRTR0	148	22	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	406
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	406
J721S2_DEV_GPIOMUX_INTRTR0	148	22	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	86
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	122
J721S2_DEV_GPIOMUX_INTRTR0	148	22	J721S2_DEV_R5FSS0_CORE0	intr	182
			J721S2_DEV_R5FSS0_CORE1	intr	182
J721S2_DEV_GPIOMUX_INTRTR0	148	22	J721S2_DEV_R5FSS1_CORE0	intr	182
			J721S2_DEV_R5FSS1_CORE1	intr	182
J721S2_DEV_GPIOMUX_INTRTR0	148	23	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	407
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	407
J721S2_DEV_GPIOMUX_INTRTR0	148	23	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	87
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	123
J721S2_DEV_GPIOMUX_INTRTR0	148	23	J721S2_DEV_R5FSS0_CORE0	intr	183
			J721S2_DEV_R5FSS0_CORE1	intr	183
J721S2_DEV_GPIOMUX_INTRTR0	148	23	J721S2_DEV_R5FSS1_CORE0	intr	183
			J721S2_DEV_R5FSS1_CORE1	intr	183
J721S2_DEV_GPIOMUX_INTRTR0	148	24	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	408
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	408
J721S2_DEV_GPIOMUX_INTRTR0	148	24	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	88
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	124
J721S2_DEV_GPIOMUX_INTRTR0	148	24	J721S2_DEV_R5FSS0_CORE0	intr	184
			J721S2_DEV_R5FSS0_CORE1	intr	184
J721S2_DEV_GPIOMUX_INTRTR0	148	24	J721S2_DEV_R5FSS1_CORE0	intr	184
			J721S2_DEV_R5FSS1_CORE1	intr	184
J721S2_DEV_GPIOMUX_INTRTR0	148	25	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	409
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	409
J721S2_DEV_GPIOMUX_INTRTR0	148	25	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	89
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	125
J721S2_DEV_GPIOMUX_INTRTR0	148	25	J721S2_DEV_R5FSS0_CORE0	intr	185
			J721S2_DEV_R5FSS0_CORE1	intr	185
J721S2_DEV_GPIOMUX_INTRTR0	148	25	J721S2_DEV_R5FSS1_CORE0	intr	185
			J721S2_DEV_R5FSS1_CORE1	intr	185
J721S2_DEV_GPIOMUX_INTRTR0	148	26	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	410
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	410
J721S2_DEV_GPIOMUX_INTRTR0	148	26	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	90
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	126
J721S2_DEV_GPIOMUX_INTRTR0	148	26	J721S2_DEV_R5FSS0_CORE0	intr	186
			J721S2_DEV_R5FSS0_CORE1	intr	186
J721S2_DEV_GPIOMUX_INTRTR0	148	26	J721S2_DEV_R5FSS1_CORE0	intr	186
			J721S2_DEV_R5FSS1_CORE1	intr	186
J721S2_DEV_GPIOMUX_INTRTR0	148	27	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	411
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	411
J721S2_DEV_GPIOMUX_INTRTR0	148	27	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	91
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	127
J721S2_DEV_GPIOMUX_INTRTR0	148	27	J721S2_DEV_R5FSS0_CORE0	intr	187
			J721S2_DEV_R5FSS0_CORE1	intr	187
J721S2_DEV_GPIOMUX_INTRTR0	148	27	J721S2_DEV_R5FSS1_CORE0	intr	187
			J721S2_DEV_R5FSS1_CORE1	intr	187
J721S2_DEV_GPIOMUX_INTRTR0	148	28	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	412
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	412
J721S2_DEV_GPIOMUX_INTRTR0	148	28	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	92
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	128
J721S2_DEV_GPIOMUX_INTRTR0	148	28	J721S2_DEV_R5FSS0_CORE0	intr	188
			J721S2_DEV_R5FSS0_CORE1	intr	188
J721S2_DEV_GPIOMUX_INTRTR0	148	28	J721S2_DEV_R5FSS1_CORE0	intr	188
			J721S2_DEV_R5FSS1_CORE1	intr	188
J721S2_DEV_GPIOMUX_INTRTR0	148	29	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	413
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	413
J721S2_DEV_GPIOMUX_INTRTR0	148	29	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	93
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	129
J721S2_DEV_GPIOMUX_INTRTR0	148	29	J721S2_DEV_R5FSS0_CORE0	intr	189
			J721S2_DEV_R5FSS0_CORE1	intr	189
J721S2_DEV_GPIOMUX_INTRTR0	148	29	J721S2_DEV_R5FSS1_CORE0	intr	189
			J721S2_DEV_R5FSS1_CORE1	intr	189
J721S2_DEV_GPIOMUX_INTRTR0	148	30	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	414
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	414
J721S2_DEV_GPIOMUX_INTRTR0	148	30	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	94
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	130
J721S2_DEV_GPIOMUX_INTRTR0	148	30	J721S2_DEV_R5FSS0_CORE0	intr	190
			J721S2_DEV_R5FSS0_CORE1	intr	190
J721S2_DEV_GPIOMUX_INTRTR0	148	30	J721S2_DEV_R5FSS1_CORE0	intr	190
			J721S2_DEV_R5FSS1_CORE1	intr	190
J721S2_DEV_GPIOMUX_INTRTR0	148	31	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	415
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	415
J721S2_DEV_GPIOMUX_INTRTR0	148	31	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	95
			J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	131
J721S2_DEV_GPIOMUX_INTRTR0	148	31	J721S2_DEV_R5FSS0_CORE0	intr	191
			J721S2_DEV_R5FSS0_CORE1	intr	191
J721S2_DEV_GPIOMUX_INTRTR0	148	31	J721S2_DEV_R5FSS1_CORE0	intr	191
			J721S2_DEV_R5FSS1_CORE1	intr	191
J721S2_DEV_GPIOMUX_INTRTR0	148	32	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	416
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	416
J721S2_DEV_GPIOMUX_INTRTR0	148	33	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	417
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	417
J721S2_DEV_GPIOMUX_INTRTR0	148	34	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	418
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	418
J721S2_DEV_GPIOMUX_INTRTR0	148	35	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	419
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	419
J721S2_DEV_GPIOMUX_INTRTR0	148	36	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	420
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	420
J721S2_DEV_GPIOMUX_INTRTR0	148	37	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	421
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	421
J721S2_DEV_GPIOMUX_INTRTR0	148	38	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	422
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	422
J721S2_DEV_GPIOMUX_INTRTR0	148	39	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	423
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	423
J721S2_DEV_GPIOMUX_INTRTR0	148	40	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	424
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	424
J721S2_DEV_GPIOMUX_INTRTR0	148	41	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	425
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	425
J721S2_DEV_GPIOMUX_INTRTR0	148	42	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	426
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	426
J721S2_DEV_GPIOMUX_INTRTR0	148	43	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	427
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	427
J721S2_DEV_GPIOMUX_INTRTR0	148	44	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	428
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	428
J721S2_DEV_GPIOMUX_INTRTR0	148	45	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	429
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	429
J721S2_DEV_GPIOMUX_INTRTR0	148	46	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	430
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	430
J721S2_DEV_GPIOMUX_INTRTR0	148	47	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	431
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	431
J721S2_DEV_GPIOMUX_INTRTR0	148	48	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	432
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	432
J721S2_DEV_GPIOMUX_INTRTR0	148	49	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	433
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	433
J721S2_DEV_GPIOMUX_INTRTR0	148	50	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	434
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	434
J721S2_DEV_GPIOMUX_INTRTR0	148	51	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	435
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	435
J721S2_DEV_GPIOMUX_INTRTR0	148	52	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	436
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	436
J721S2_DEV_GPIOMUX_INTRTR0	148	53	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	437
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	437
J721S2_DEV_GPIOMUX_INTRTR0	148	54	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	438
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	438
J721S2_DEV_GPIOMUX_INTRTR0	148	55	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	439
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	439
J721S2_DEV_GPIOMUX_INTRTR0	148	56	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	440
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	440
J721S2_DEV_GPIOMUX_INTRTR0	148	57	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	441
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	441
J721S2_DEV_GPIOMUX_INTRTR0	148	58	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	442
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	442
J721S2_DEV_GPIOMUX_INTRTR0	148	59	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	443
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	443
J721S2_DEV_GPIOMUX_INTRTR0	148	60	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	444
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	444
J721S2_DEV_GPIOMUX_INTRTR0	148	61	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	445
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	445
J721S2_DEV_GPIOMUX_INTRTR0	148	62	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	446
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	446
J721S2_DEV_GPIOMUX_INTRTR0	148	63	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	447
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	447

CMPEVENT_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_CMPEVENT_INTRTR0	150	0	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	1	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	2	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	3	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	4	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	5	J721S2_DEV_PCIE1	pcie_cpts_comp	0
J721S2_DEV_CMPEVENT_INTRTR0	150	6	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	7	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	8	J721S2_DEV_NAVSS0	cpts0_comp	0
J721S2_DEV_CMPEVENT_INTRTR0	150	9	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	10	J721S2_DEV_MCU_CPSW0	cpts_comp	0
J721S2_DEV_CMPEVENT_INTRTR0	150	11	J721S2_DEV_CPSW1	cpts_comp	0
J721S2_DEV_CMPEVENT_INTRTR0	150	12	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	13	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	14	Use TRM - Not managed by TISCI
J721S2_DEV_CMPEVENT_INTRTR0	150	15	Use TRM - Not managed by TISCI

CMPEVENT_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_CMPEVENT_INTRTR0	150	0	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	544
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	544
J721S2_DEV_CMPEVENT_INTRTR0	150	1	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	545
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	545
J721S2_DEV_CMPEVENT_INTRTR0	150	2	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	546
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	546
J721S2_DEV_CMPEVENT_INTRTR0	150	3	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	547
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	547
J721S2_DEV_CMPEVENT_INTRTR0	150	4	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	96
J721S2_DEV_CMPEVENT_INTRTR0	150	5	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	97
J721S2_DEV_CMPEVENT_INTRTR0	150	6	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	98
J721S2_DEV_CMPEVENT_INTRTR0	150	7	J721S2_DEV_MAIN2MCU_PLS_INTRTR0	in	99
J721S2_DEV_CMPEVENT_INTRTR0	150	8	J721S2_DEV_R5FSS0_CORE0	intr	326
			J721S2_DEV_R5FSS0_CORE1	intr	326
J721S2_DEV_CMPEVENT_INTRTR0	150	8	J721S2_DEV_R5FSS1_CORE0	intr	326
			J721S2_DEV_R5FSS1_CORE1	intr	326
J721S2_DEV_CMPEVENT_INTRTR0	150	9	J721S2_DEV_R5FSS0_CORE0	intr	327
			J721S2_DEV_R5FSS0_CORE1	intr	327
J721S2_DEV_CMPEVENT_INTRTR0	150	9	J721S2_DEV_R5FSS1_CORE0	intr	327
			J721S2_DEV_R5FSS1_CORE1	intr	327
J721S2_DEV_CMPEVENT_INTRTR0	150	10	J721S2_DEV_R5FSS0_CORE0	intr	328
			J721S2_DEV_R5FSS0_CORE1	intr	328
J721S2_DEV_CMPEVENT_INTRTR0	150	10	J721S2_DEV_R5FSS1_CORE0	intr	328
			J721S2_DEV_R5FSS1_CORE1	intr	328
J721S2_DEV_CMPEVENT_INTRTR0	150	11	J721S2_DEV_R5FSS0_CORE0	intr	329
			J721S2_DEV_R5FSS0_CORE1	intr	329
J721S2_DEV_CMPEVENT_INTRTR0	150	11	J721S2_DEV_R5FSS1_CORE0	intr	329
			J721S2_DEV_R5FSS1_CORE1	intr	329
J721S2_DEV_CMPEVENT_INTRTR0	150	12	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	108
J721S2_DEV_CMPEVENT_INTRTR0	150	13	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	109
J721S2_DEV_CMPEVENT_INTRTR0	150	14	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	110
J721S2_DEV_CMPEVENT_INTRTR0	150	15	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_levi_pend	111

NAVSS0_INTR_0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	0	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	0
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	1	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	1
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	2	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	2
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	3	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	3
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	4	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	4
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	5	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	5
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	6	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	6
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	7	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	7
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	8	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	8
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	9	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	9
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	10	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	10
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	11	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	11
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	12	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	12
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	13	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	13
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	14	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	14
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	15	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	15
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	16	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	16
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	17	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	17
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	18	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	18
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	19	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	19
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	20	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	20
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	21	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	21
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	22	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	22
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	23	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	23
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	24	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	24
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	25	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	25
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	26	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	26
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	27	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	27
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	28	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	28
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	29	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	29
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	30	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	30
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	31	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	31
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	32	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	32
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	33	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	33
J721S2_DEV_NAVSS0_INTR_0	227	34	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	34
J721S2_DEV_NAVSS0_INTR_0	227	35	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	35
J721S2_DEV_NAVSS0_INTR_0	227	36	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	36
J721S2_DEV_NAVSS0_INTR_0	227	37	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	37
J721S2_DEV_NAVSS0_INTR_0	227	38	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	38
J721S2_DEV_NAVSS0_INTR_0	227	39	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	39
J721S2_DEV_NAVSS0_INTR_0	227	40	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	40
J721S2_DEV_NAVSS0_INTR_0	227	41	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	41
J721S2_DEV_NAVSS0_INTR_0	227	42	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	42
J721S2_DEV_NAVSS0_INTR_0	227	43	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	43
J721S2_DEV_NAVSS0_INTR_0	227	44	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	44
J721S2_DEV_NAVSS0_INTR_0	227	45	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	45
J721S2_DEV_NAVSS0_INTR_0	227	46	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	46
J721S2_DEV_NAVSS0_INTR_0	227	47	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	47
J721S2_DEV_NAVSS0_INTR_0	227	48	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	48
J721S2_DEV_NAVSS0_INTR_0	227	49	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	49
J721S2_DEV_NAVSS0_INTR_0	227	50	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	50
J721S2_DEV_NAVSS0_INTR_0	227	51	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	51
J721S2_DEV_NAVSS0_INTR_0	227	52	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	52
J721S2_DEV_NAVSS0_INTR_0	227	53	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	53
J721S2_DEV_NAVSS0_INTR_0	227	54	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	54
J721S2_DEV_NAVSS0_INTR_0	227	55	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	55
J721S2_DEV_NAVSS0_INTR_0	227	56	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	56
J721S2_DEV_NAVSS0_INTR_0	227	57	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	57
J721S2_DEV_NAVSS0_INTR_0	227	58	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	58
J721S2_DEV_NAVSS0_INTR_0	227	59	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	59
J721S2_DEV_NAVSS0_INTR_0	227	60	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	60
J721S2_DEV_NAVSS0_INTR_0	227	61	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	61
J721S2_DEV_NAVSS0_INTR_0	227	62	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	62
J721S2_DEV_NAVSS0_INTR_0	227	63	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	63
J721S2_DEV_NAVSS0_INTR_0	227	64	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	64
J721S2_DEV_NAVSS0_INTR_0	227	65	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	65
J721S2_DEV_NAVSS0_INTR_0	227	66	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	66
J721S2_DEV_NAVSS0_INTR_0	227	67	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	67
J721S2_DEV_NAVSS0_INTR_0	227	68	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	68
J721S2_DEV_NAVSS0_INTR_0	227	69	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	69
J721S2_DEV_NAVSS0_INTR_0	227	70	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	70
J721S2_DEV_NAVSS0_INTR_0	227	71	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	71
J721S2_DEV_NAVSS0_INTR_0	227	72	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	72
J721S2_DEV_NAVSS0_INTR_0	227	73	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	73
J721S2_DEV_NAVSS0_INTR_0	227	74	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	74
J721S2_DEV_NAVSS0_INTR_0	227	75	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	75
J721S2_DEV_NAVSS0_INTR_0	227	76	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	76
J721S2_DEV_NAVSS0_INTR_0	227	77	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	77
J721S2_DEV_NAVSS0_INTR_0	227	78	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	78
J721S2_DEV_NAVSS0_INTR_0	227	79	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	79
J721S2_DEV_NAVSS0_INTR_0	227	80	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	80
J721S2_DEV_NAVSS0_INTR_0	227	81	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	81
J721S2_DEV_NAVSS0_INTR_0	227	82	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	82
J721S2_DEV_NAVSS0_INTR_0	227	83	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	83
J721S2_DEV_NAVSS0_INTR_0	227	84	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	84
J721S2_DEV_NAVSS0_INTR_0	227	85	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	85
J721S2_DEV_NAVSS0_INTR_0	227	86	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	86
J721S2_DEV_NAVSS0_INTR_0	227	87	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	87
J721S2_DEV_NAVSS0_INTR_0	227	88	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	88
J721S2_DEV_NAVSS0_INTR_0	227	89	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	89
J721S2_DEV_NAVSS0_INTR_0	227	90	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	90
J721S2_DEV_NAVSS0_INTR_0	227	91	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	91
J721S2_DEV_NAVSS0_INTR_0	227	92	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	92
J721S2_DEV_NAVSS0_INTR_0	227	93	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	93
J721S2_DEV_NAVSS0_INTR_0	227	94	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	94
J721S2_DEV_NAVSS0_INTR_0	227	95	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	95
J721S2_DEV_NAVSS0_INTR_0	227	96	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	96
J721S2_DEV_NAVSS0_INTR_0	227	97	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	97
J721S2_DEV_NAVSS0_INTR_0	227	98	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	98
J721S2_DEV_NAVSS0_INTR_0	227	99	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	99
J721S2_DEV_NAVSS0_INTR_0	227	100	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	100
J721S2_DEV_NAVSS0_INTR_0	227	101	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	101
J721S2_DEV_NAVSS0_INTR_0	227	102	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	102
J721S2_DEV_NAVSS0_INTR_0	227	103	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	103
J721S2_DEV_NAVSS0_INTR_0	227	104	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	104
J721S2_DEV_NAVSS0_INTR_0	227	105	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	105
J721S2_DEV_NAVSS0_INTR_0	227	106	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	106
J721S2_DEV_NAVSS0_INTR_0	227	107	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	107
J721S2_DEV_NAVSS0_INTR_0	227	108	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	108
J721S2_DEV_NAVSS0_INTR_0	227	109	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	109
J721S2_DEV_NAVSS0_INTR_0	227	110	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	110
J721S2_DEV_NAVSS0_INTR_0	227	111	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	111
J721S2_DEV_NAVSS0_INTR_0	227	112	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	112
J721S2_DEV_NAVSS0_INTR_0	227	113	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	113
J721S2_DEV_NAVSS0_INTR_0	227	114	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	114
J721S2_DEV_NAVSS0_INTR_0	227	115	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	115
J721S2_DEV_NAVSS0_INTR_0	227	116	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	116
J721S2_DEV_NAVSS0_INTR_0	227	117	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	117
J721S2_DEV_NAVSS0_INTR_0	227	118	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	118
J721S2_DEV_NAVSS0_INTR_0	227	119	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	119
J721S2_DEV_NAVSS0_INTR_0	227	120	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	120
J721S2_DEV_NAVSS0_INTR_0	227	121	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	121
J721S2_DEV_NAVSS0_INTR_0	227	122	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	122
J721S2_DEV_NAVSS0_INTR_0	227	123	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	123
J721S2_DEV_NAVSS0_INTR_0	227	124	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	124
J721S2_DEV_NAVSS0_INTR_0	227	125	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	125
J721S2_DEV_NAVSS0_INTR_0	227	126	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	126
J721S2_DEV_NAVSS0_INTR_0	227	127	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	127
J721S2_DEV_NAVSS0_INTR_0	227	128	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	128
J721S2_DEV_NAVSS0_INTR_0	227	129	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	129
J721S2_DEV_NAVSS0_INTR_0	227	130	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	130
J721S2_DEV_NAVSS0_INTR_0	227	131	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	131
J721S2_DEV_NAVSS0_INTR_0	227	132	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	132
J721S2_DEV_NAVSS0_INTR_0	227	133	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	133
J721S2_DEV_NAVSS0_INTR_0	227	134	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	134
J721S2_DEV_NAVSS0_INTR_0	227	135	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	135
J721S2_DEV_NAVSS0_INTR_0	227	136	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	136
J721S2_DEV_NAVSS0_INTR_0	227	137	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	137
J721S2_DEV_NAVSS0_INTR_0	227	138	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	138
J721S2_DEV_NAVSS0_INTR_0	227	139	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	139
J721S2_DEV_NAVSS0_INTR_0	227	140	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	140
J721S2_DEV_NAVSS0_INTR_0	227	141	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	141
J721S2_DEV_NAVSS0_INTR_0	227	142	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	142
J721S2_DEV_NAVSS0_INTR_0	227	143	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	143
J721S2_DEV_NAVSS0_INTR_0	227	144	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	144
J721S2_DEV_NAVSS0_INTR_0	227	145	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	145
J721S2_DEV_NAVSS0_INTR_0	227	146	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	146
J721S2_DEV_NAVSS0_INTR_0	227	147	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	147
J721S2_DEV_NAVSS0_INTR_0	227	148	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	148
J721S2_DEV_NAVSS0_INTR_0	227	149	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	149
J721S2_DEV_NAVSS0_INTR_0	227	150	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	150
J721S2_DEV_NAVSS0_INTR_0	227	151	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	151
J721S2_DEV_NAVSS0_INTR_0	227	152	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	152
J721S2_DEV_NAVSS0_INTR_0	227	153	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	153
J721S2_DEV_NAVSS0_INTR_0	227	154	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	154
J721S2_DEV_NAVSS0_INTR_0	227	155	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	155
J721S2_DEV_NAVSS0_INTR_0	227	156	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	156
J721S2_DEV_NAVSS0_INTR_0	227	157	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	157
J721S2_DEV_NAVSS0_INTR_0	227	158	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	158
J721S2_DEV_NAVSS0_INTR_0	227	159	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	159
J721S2_DEV_NAVSS0_INTR_0	227	160	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	160
J721S2_DEV_NAVSS0_INTR_0	227	161	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	161
J721S2_DEV_NAVSS0_INTR_0	227	162	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	162
J721S2_DEV_NAVSS0_INTR_0	227	163	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	163
J721S2_DEV_NAVSS0_INTR_0	227	164	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	164
J721S2_DEV_NAVSS0_INTR_0	227	165	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	165
J721S2_DEV_NAVSS0_INTR_0	227	166	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	166
J721S2_DEV_NAVSS0_INTR_0	227	167	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	167
J721S2_DEV_NAVSS0_INTR_0	227	168	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	168
J721S2_DEV_NAVSS0_INTR_0	227	169	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	169
J721S2_DEV_NAVSS0_INTR_0	227	170	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	170
J721S2_DEV_NAVSS0_INTR_0	227	171	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	171
J721S2_DEV_NAVSS0_INTR_0	227	172	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	172
J721S2_DEV_NAVSS0_INTR_0	227	173	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	173
J721S2_DEV_NAVSS0_INTR_0	227	174	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	174
J721S2_DEV_NAVSS0_INTR_0	227	175	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	175
J721S2_DEV_NAVSS0_INTR_0	227	176	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	176
J721S2_DEV_NAVSS0_INTR_0	227	177	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	177
J721S2_DEV_NAVSS0_INTR_0	227	178	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	178
J721S2_DEV_NAVSS0_INTR_0	227	179	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	179
J721S2_DEV_NAVSS0_INTR_0	227	180	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	180
J721S2_DEV_NAVSS0_INTR_0	227	181	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	181
J721S2_DEV_NAVSS0_INTR_0	227	182	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	182
J721S2_DEV_NAVSS0_INTR_0	227	183	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	183
J721S2_DEV_NAVSS0_INTR_0	227	184	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	184
J721S2_DEV_NAVSS0_INTR_0	227	185	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	185
J721S2_DEV_NAVSS0_INTR_0	227	186	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	186
J721S2_DEV_NAVSS0_INTR_0	227	187	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	187
J721S2_DEV_NAVSS0_INTR_0	227	188	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	188
J721S2_DEV_NAVSS0_INTR_0	227	189	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	189
J721S2_DEV_NAVSS0_INTR_0	227	190	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	190
J721S2_DEV_NAVSS0_INTR_0	227	191	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	191
J721S2_DEV_NAVSS0_INTR_0	227	192	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	192
J721S2_DEV_NAVSS0_INTR_0	227	193	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	193
J721S2_DEV_NAVSS0_INTR_0	227	194	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	194
J721S2_DEV_NAVSS0_INTR_0	227	195	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	195
J721S2_DEV_NAVSS0_INTR_0	227	196	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	196
J721S2_DEV_NAVSS0_INTR_0	227	197	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	197
J721S2_DEV_NAVSS0_INTR_0	227	198	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	198
J721S2_DEV_NAVSS0_INTR_0	227	199	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	199
J721S2_DEV_NAVSS0_INTR_0	227	200	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	200
J721S2_DEV_NAVSS0_INTR_0	227	201	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	201
J721S2_DEV_NAVSS0_INTR_0	227	202	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	202
J721S2_DEV_NAVSS0_INTR_0	227	203	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	203
J721S2_DEV_NAVSS0_INTR_0	227	204	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	204
J721S2_DEV_NAVSS0_INTR_0	227	205	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	205
J721S2_DEV_NAVSS0_INTR_0	227	206	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	206
J721S2_DEV_NAVSS0_INTR_0	227	207	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	207
J721S2_DEV_NAVSS0_INTR_0	227	208	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	208
J721S2_DEV_NAVSS0_INTR_0	227	209	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	209
J721S2_DEV_NAVSS0_INTR_0	227	210	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	210
J721S2_DEV_NAVSS0_INTR_0	227	211	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	211
J721S2_DEV_NAVSS0_INTR_0	227	212	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	212
J721S2_DEV_NAVSS0_INTR_0	227	213	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	213
J721S2_DEV_NAVSS0_INTR_0	227	214	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	214
J721S2_DEV_NAVSS0_INTR_0	227	215	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	215
J721S2_DEV_NAVSS0_INTR_0	227	216	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	216
J721S2_DEV_NAVSS0_INTR_0	227	217	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	217
J721S2_DEV_NAVSS0_INTR_0	227	218	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	218
J721S2_DEV_NAVSS0_INTR_0	227	219	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	219
J721S2_DEV_NAVSS0_INTR_0	227	220	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	220
J721S2_DEV_NAVSS0_INTR_0	227	221	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	221
J721S2_DEV_NAVSS0_INTR_0	227	222	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	222
J721S2_DEV_NAVSS0_INTR_0	227	223	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	223
J721S2_DEV_NAVSS0_INTR_0	227	224	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	224
J721S2_DEV_NAVSS0_INTR_0	227	225	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	225
J721S2_DEV_NAVSS0_INTR_0	227	226	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	226
J721S2_DEV_NAVSS0_INTR_0	227	227	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	227
J721S2_DEV_NAVSS0_INTR_0	227	228	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	228
J721S2_DEV_NAVSS0_INTR_0	227	229	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	229
J721S2_DEV_NAVSS0_INTR_0	227	230	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	230
J721S2_DEV_NAVSS0_INTR_0	227	231	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	231
J721S2_DEV_NAVSS0_INTR_0	227	232	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	232
J721S2_DEV_NAVSS0_INTR_0	227	233	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	233
J721S2_DEV_NAVSS0_INTR_0	227	234	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	234
J721S2_DEV_NAVSS0_INTR_0	227	235	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	235
J721S2_DEV_NAVSS0_INTR_0	227	236	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	236
J721S2_DEV_NAVSS0_INTR_0	227	237	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	237
J721S2_DEV_NAVSS0_INTR_0	227	238	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	238
J721S2_DEV_NAVSS0_INTR_0	227	239	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	239
J721S2_DEV_NAVSS0_INTR_0	227	240	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	240
J721S2_DEV_NAVSS0_INTR_0	227	241	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	241
J721S2_DEV_NAVSS0_INTR_0	227	242	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	242
J721S2_DEV_NAVSS0_INTR_0	227	243	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	243
J721S2_DEV_NAVSS0_INTR_0	227	244	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	244
J721S2_DEV_NAVSS0_INTR_0	227	245	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	245
J721S2_DEV_NAVSS0_INTR_0	227	246	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	246
J721S2_DEV_NAVSS0_INTR_0	227	247	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	247
J721S2_DEV_NAVSS0_INTR_0	227	248	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	248
J721S2_DEV_NAVSS0_INTR_0	227	249	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	249
J721S2_DEV_NAVSS0_INTR_0	227	250	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	250
J721S2_DEV_NAVSS0_INTR_0	227	251	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	251
J721S2_DEV_NAVSS0_INTR_0	227	252	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	252
J721S2_DEV_NAVSS0_INTR_0	227	253	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	253
J721S2_DEV_NAVSS0_INTR_0	227	254	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	254
J721S2_DEV_NAVSS0_INTR_0	227	255	J721S2_DEV_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	255
J721S2_DEV_NAVSS0_INTR_0	227	256	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	0
J721S2_DEV_NAVSS0_INTR_0	227	257	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	1
J721S2_DEV_NAVSS0_INTR_0	227	258	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	2
J721S2_DEV_NAVSS0_INTR_0	227	259	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	3
J721S2_DEV_NAVSS0_INTR_0	227	260	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	4
J721S2_DEV_NAVSS0_INTR_0	227	261	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	5
J721S2_DEV_NAVSS0_INTR_0	227	262	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	6
J721S2_DEV_NAVSS0_INTR_0	227	263	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	7
J721S2_DEV_NAVSS0_INTR_0	227	264	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	8
J721S2_DEV_NAVSS0_INTR_0	227	265	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	9
J721S2_DEV_NAVSS0_INTR_0	227	266	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	10
J721S2_DEV_NAVSS0_INTR_0	227	267	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	11
J721S2_DEV_NAVSS0_INTR_0	227	268	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	12
J721S2_DEV_NAVSS0_INTR_0	227	269	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	13
J721S2_DEV_NAVSS0_INTR_0	227	270	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	14
J721S2_DEV_NAVSS0_INTR_0	227	271	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	15
J721S2_DEV_NAVSS0_INTR_0	227	272	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	16
J721S2_DEV_NAVSS0_INTR_0	227	273	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	17
J721S2_DEV_NAVSS0_INTR_0	227	274	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	18
J721S2_DEV_NAVSS0_INTR_0	227	275	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	19
J721S2_DEV_NAVSS0_INTR_0	227	276	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	20
J721S2_DEV_NAVSS0_INTR_0	227	277	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	21
J721S2_DEV_NAVSS0_INTR_0	227	278	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	22
J721S2_DEV_NAVSS0_INTR_0	227	279	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	23
J721S2_DEV_NAVSS0_INTR_0	227	280	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	24
J721S2_DEV_NAVSS0_INTR_0	227	281	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	25
J721S2_DEV_NAVSS0_INTR_0	227	282	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	26
J721S2_DEV_NAVSS0_INTR_0	227	283	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	27
J721S2_DEV_NAVSS0_INTR_0	227	284	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	28
J721S2_DEV_NAVSS0_INTR_0	227	285	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	29
J721S2_DEV_NAVSS0_INTR_0	227	286	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	30
J721S2_DEV_NAVSS0_INTR_0	227	287	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	31
J721S2_DEV_NAVSS0_INTR_0	227	288	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	32
J721S2_DEV_NAVSS0_INTR_0	227	289	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	33
J721S2_DEV_NAVSS0_INTR_0	227	290	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	34
J721S2_DEV_NAVSS0_INTR_0	227	291	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	35
J721S2_DEV_NAVSS0_INTR_0	227	292	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	36
J721S2_DEV_NAVSS0_INTR_0	227	293	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	37
J721S2_DEV_NAVSS0_INTR_0	227	294	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	38
J721S2_DEV_NAVSS0_INTR_0	227	295	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	39
J721S2_DEV_NAVSS0_INTR_0	227	296	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	40
J721S2_DEV_NAVSS0_INTR_0	227	297	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	41
J721S2_DEV_NAVSS0_INTR_0	227	298	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	42
J721S2_DEV_NAVSS0_INTR_0	227	299	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	43
J721S2_DEV_NAVSS0_INTR_0	227	300	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	44
J721S2_DEV_NAVSS0_INTR_0	227	301	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	45
J721S2_DEV_NAVSS0_INTR_0	227	302	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	46
J721S2_DEV_NAVSS0_INTR_0	227	303	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	47
J721S2_DEV_NAVSS0_INTR_0	227	304	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	48
J721S2_DEV_NAVSS0_INTR_0	227	305	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	49
J721S2_DEV_NAVSS0_INTR_0	227	306	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	50
J721S2_DEV_NAVSS0_INTR_0	227	307	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	51
J721S2_DEV_NAVSS0_INTR_0	227	308	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	52
J721S2_DEV_NAVSS0_INTR_0	227	309	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	53
J721S2_DEV_NAVSS0_INTR_0	227	310	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	54
J721S2_DEV_NAVSS0_INTR_0	227	311	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	55
J721S2_DEV_NAVSS0_INTR_0	227	312	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	56
J721S2_DEV_NAVSS0_INTR_0	227	313	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	57
J721S2_DEV_NAVSS0_INTR_0	227	314	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	58
J721S2_DEV_NAVSS0_INTR_0	227	315	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	59
J721S2_DEV_NAVSS0_INTR_0	227	316	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	60
J721S2_DEV_NAVSS0_INTR_0	227	317	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	61
J721S2_DEV_NAVSS0_INTR_0	227	318	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	62
J721S2_DEV_NAVSS0_INTR_0	227	319	J721S2_DEV_NAVSS0_MODSS_INTA_1	intaggr_vintr_pend	63
J721S2_DEV_NAVSS0_INTR_0	227	320	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	0
J721S2_DEV_NAVSS0_INTR_0	227	321	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	1
J721S2_DEV_NAVSS0_INTR_0	227	322	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	2
J721S2_DEV_NAVSS0_INTR_0	227	323	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	3
J721S2_DEV_NAVSS0_INTR_0	227	324	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	4
J721S2_DEV_NAVSS0_INTR_0	227	325	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	5
J721S2_DEV_NAVSS0_INTR_0	227	326	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	6
J721S2_DEV_NAVSS0_INTR_0	227	327	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	7
J721S2_DEV_NAVSS0_INTR_0	227	328	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	8
J721S2_DEV_NAVSS0_INTR_0	227	329	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	9
J721S2_DEV_NAVSS0_INTR_0	227	330	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	10
J721S2_DEV_NAVSS0_INTR_0	227	331	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	11
J721S2_DEV_NAVSS0_INTR_0	227	332	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	12
J721S2_DEV_NAVSS0_INTR_0	227	333	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	13
J721S2_DEV_NAVSS0_INTR_0	227	334	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	14
J721S2_DEV_NAVSS0_INTR_0	227	335	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	15
J721S2_DEV_NAVSS0_INTR_0	227	336	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	16
J721S2_DEV_NAVSS0_INTR_0	227	337	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	17
J721S2_DEV_NAVSS0_INTR_0	227	338	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	18
J721S2_DEV_NAVSS0_INTR_0	227	339	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	19
J721S2_DEV_NAVSS0_INTR_0	227	340	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	20
J721S2_DEV_NAVSS0_INTR_0	227	341	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	21
J721S2_DEV_NAVSS0_INTR_0	227	342	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	22
J721S2_DEV_NAVSS0_INTR_0	227	343	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	23
J721S2_DEV_NAVSS0_INTR_0	227	344	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	24
J721S2_DEV_NAVSS0_INTR_0	227	345	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	25
J721S2_DEV_NAVSS0_INTR_0	227	346	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	26
J721S2_DEV_NAVSS0_INTR_0	227	347	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	27
J721S2_DEV_NAVSS0_INTR_0	227	348	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	28
J721S2_DEV_NAVSS0_INTR_0	227	349	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	29
J721S2_DEV_NAVSS0_INTR_0	227	350	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	30
J721S2_DEV_NAVSS0_INTR_0	227	351	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	31
J721S2_DEV_NAVSS0_INTR_0	227	352	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	32
J721S2_DEV_NAVSS0_INTR_0	227	353	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	33
J721S2_DEV_NAVSS0_INTR_0	227	354	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	34
J721S2_DEV_NAVSS0_INTR_0	227	355	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	35
J721S2_DEV_NAVSS0_INTR_0	227	356	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	36
J721S2_DEV_NAVSS0_INTR_0	227	357	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	37
J721S2_DEV_NAVSS0_INTR_0	227	358	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	38
J721S2_DEV_NAVSS0_INTR_0	227	359	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	39
J721S2_DEV_NAVSS0_INTR_0	227	360	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	40
J721S2_DEV_NAVSS0_INTR_0	227	361	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	41
J721S2_DEV_NAVSS0_INTR_0	227	362	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	42
J721S2_DEV_NAVSS0_INTR_0	227	363	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	43
J721S2_DEV_NAVSS0_INTR_0	227	364	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	44
J721S2_DEV_NAVSS0_INTR_0	227	365	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	45
J721S2_DEV_NAVSS0_INTR_0	227	366	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	46
J721S2_DEV_NAVSS0_INTR_0	227	367	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	47
J721S2_DEV_NAVSS0_INTR_0	227	368	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	48
J721S2_DEV_NAVSS0_INTR_0	227	369	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	49
J721S2_DEV_NAVSS0_INTR_0	227	370	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	50
J721S2_DEV_NAVSS0_INTR_0	227	371	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	51
J721S2_DEV_NAVSS0_INTR_0	227	372	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	52
J721S2_DEV_NAVSS0_INTR_0	227	373	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	53
J721S2_DEV_NAVSS0_INTR_0	227	374	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	54
J721S2_DEV_NAVSS0_INTR_0	227	375	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	55
J721S2_DEV_NAVSS0_INTR_0	227	376	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	56
J721S2_DEV_NAVSS0_INTR_0	227	377	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	57
J721S2_DEV_NAVSS0_INTR_0	227	378	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	58
J721S2_DEV_NAVSS0_INTR_0	227	379	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	59
J721S2_DEV_NAVSS0_INTR_0	227	380	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	60
J721S2_DEV_NAVSS0_INTR_0	227	381	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	61
J721S2_DEV_NAVSS0_INTR_0	227	382	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	62
J721S2_DEV_NAVSS0_INTR_0	227	383	J721S2_DEV_NAVSS0_MODSS_INTA_0	intaggr_vintr_pend	63
J721S2_DEV_NAVSS0_INTR_0	227	384	J721S2_DEV_NAVSS0_MCRC_0	dma_event_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	385	J721S2_DEV_NAVSS0_MCRC_0	dma_event_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	386	J721S2_DEV_NAVSS0_MCRC_0	dma_event_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	387	J721S2_DEV_NAVSS0_MCRC_0	dma_event_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	388	J721S2_DEV_NAVSS0_MCRC_0	intaggr_vintr_pend	4
J721S2_DEV_NAVSS0_INTR_0	227	389	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	390	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	391	J721S2_DEV_NAVSS0_CPTS_0	event_pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	392	J721S2_DEV_NAVSS0_MAILBOX_11	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	393	J721S2_DEV_NAVSS0_MAILBOX_11	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	394	J721S2_DEV_NAVSS0_MAILBOX_11	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	395	J721S2_DEV_NAVSS0_MAILBOX_11	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	396	J721S2_DEV_NAVSS0_MAILBOX_10	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	397	J721S2_DEV_NAVSS0_MAILBOX_10	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	398	J721S2_DEV_NAVSS0_MAILBOX_10	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	399	J721S2_DEV_NAVSS0_MAILBOX_10	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	400	J721S2_DEV_NAVSS0_MAILBOX_9	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	401	J721S2_DEV_NAVSS0_MAILBOX_9	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	402	J721S2_DEV_NAVSS0_MAILBOX_9	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	403	J721S2_DEV_NAVSS0_MAILBOX_9	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	404	J721S2_DEV_NAVSS0_MAILBOX_8	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	405	J721S2_DEV_NAVSS0_MAILBOX_8	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	406	J721S2_DEV_NAVSS0_MAILBOX_8	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	407	J721S2_DEV_NAVSS0_MAILBOX_8	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	408	J721S2_DEV_NAVSS0_MAILBOX_7	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	409	J721S2_DEV_NAVSS0_MAILBOX_7	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	410	J721S2_DEV_NAVSS0_MAILBOX_7	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	411	J721S2_DEV_NAVSS0_MAILBOX_7	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	412	J721S2_DEV_NAVSS0_MAILBOX_6	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	413	J721S2_DEV_NAVSS0_MAILBOX_6	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	414	J721S2_DEV_NAVSS0_MAILBOX_6	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	415	J721S2_DEV_NAVSS0_MAILBOX_6	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	416	J721S2_DEV_NAVSS0_MAILBOX_5	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	417	J721S2_DEV_NAVSS0_MAILBOX_5	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	418	J721S2_DEV_NAVSS0_MAILBOX_5	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	419	J721S2_DEV_NAVSS0_MAILBOX_5	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	420	J721S2_DEV_NAVSS0_MAILBOX_4	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	421	J721S2_DEV_NAVSS0_MAILBOX_4	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	422	J721S2_DEV_NAVSS0_MAILBOX_4	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	423	J721S2_DEV_NAVSS0_MAILBOX_4	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	424	J721S2_DEV_NAVSS0_MAILBOX_3	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	425	J721S2_DEV_NAVSS0_MAILBOX_3	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	426	J721S2_DEV_NAVSS0_MAILBOX_3	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	427	J721S2_DEV_NAVSS0_MAILBOX_3	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	428	J721S2_DEV_NAVSS0_MAILBOX_2	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	429	J721S2_DEV_NAVSS0_MAILBOX_2	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	430	J721S2_DEV_NAVSS0_MAILBOX_2	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	431	J721S2_DEV_NAVSS0_MAILBOX_2	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	432	J721S2_DEV_NAVSS0_MAILBOX_1	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	433	J721S2_DEV_NAVSS0_MAILBOX_1	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	434	J721S2_DEV_NAVSS0_MAILBOX_1	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	435	J721S2_DEV_NAVSS0_MAILBOX_1	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	436	J721S2_DEV_NAVSS0_MAILBOX_0	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	437	J721S2_DEV_NAVSS0_MAILBOX_0	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	438	J721S2_DEV_NAVSS0_MAILBOX_0	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	439	J721S2_DEV_NAVSS0_MAILBOX_0	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	440	J721S2_DEV_NAVSS0_MAILBOX1_11	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	441	J721S2_DEV_NAVSS0_MAILBOX1_11	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	442	J721S2_DEV_NAVSS0_MAILBOX1_11	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	443	J721S2_DEV_NAVSS0_MAILBOX1_11	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	444	J721S2_DEV_NAVSS0_MAILBOX1_10	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	445	J721S2_DEV_NAVSS0_MAILBOX1_10	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	446	J721S2_DEV_NAVSS0_MAILBOX1_10	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	447	J721S2_DEV_NAVSS0_MAILBOX1_10	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	448	J721S2_DEV_NAVSS0_MAILBOX1_9	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	449	J721S2_DEV_NAVSS0_MAILBOX1_9	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	450	J721S2_DEV_NAVSS0_MAILBOX1_9	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	451	J721S2_DEV_NAVSS0_MAILBOX1_9	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	452	J721S2_DEV_NAVSS0_MAILBOX1_8	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	453	J721S2_DEV_NAVSS0_MAILBOX1_8	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	454	J721S2_DEV_NAVSS0_MAILBOX1_8	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	455	J721S2_DEV_NAVSS0_MAILBOX1_8	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	456	J721S2_DEV_NAVSS0_MAILBOX1_7	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	457	J721S2_DEV_NAVSS0_MAILBOX1_7	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	458	J721S2_DEV_NAVSS0_MAILBOX1_7	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	459	J721S2_DEV_NAVSS0_MAILBOX1_7	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	460	J721S2_DEV_NAVSS0_MAILBOX1_6	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	461	J721S2_DEV_NAVSS0_MAILBOX1_6	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	462	J721S2_DEV_NAVSS0_MAILBOX1_6	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	463	J721S2_DEV_NAVSS0_MAILBOX1_6	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	464	J721S2_DEV_NAVSS0_MAILBOX1_5	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	465	J721S2_DEV_NAVSS0_MAILBOX1_5	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	466	J721S2_DEV_NAVSS0_MAILBOX1_5	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	467	J721S2_DEV_NAVSS0_MAILBOX1_5	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	468	J721S2_DEV_NAVSS0_MAILBOX1_4	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	469	J721S2_DEV_NAVSS0_MAILBOX1_4	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	470	J721S2_DEV_NAVSS0_MAILBOX1_4	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	471	J721S2_DEV_NAVSS0_MAILBOX1_4	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	472	J721S2_DEV_NAVSS0_MAILBOX1_3	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	473	J721S2_DEV_NAVSS0_MAILBOX1_3	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	474	J721S2_DEV_NAVSS0_MAILBOX1_3	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	475	J721S2_DEV_NAVSS0_MAILBOX1_3	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	476	J721S2_DEV_NAVSS0_MAILBOX1_2	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	477	J721S2_DEV_NAVSS0_MAILBOX1_2	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	478	J721S2_DEV_NAVSS0_MAILBOX1_2	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	479	J721S2_DEV_NAVSS0_MAILBOX1_2	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	480	J721S2_DEV_NAVSS0_MAILBOX1_1	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	481	J721S2_DEV_NAVSS0_MAILBOX1_1	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	482	J721S2_DEV_NAVSS0_MAILBOX1_1	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	483	J721S2_DEV_NAVSS0_MAILBOX1_1	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	484	J721S2_DEV_NAVSS0_MAILBOX1_0	pend_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	485	J721S2_DEV_NAVSS0_MAILBOX1_0	pend_intr	1
J721S2_DEV_NAVSS0_INTR_0	227	486	J721S2_DEV_NAVSS0_MAILBOX1_0	pend_intr	2
J721S2_DEV_NAVSS0_INTR_0	227	487	J721S2_DEV_NAVSS0_MAILBOX1_0	pend_intr	3
J721S2_DEV_NAVSS0_INTR_0	227	488	J721S2_DEV_NAVSS0_PVU_1	exp_intr	0
J721S2_DEV_NAVSS0_INTR_0	227	489	J721S2_DEV_NAVSS0_PVU_0	exp_intr	0

NAVSS0_INTR_0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	0	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	64
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	64
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	1	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	65
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	65
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	2	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	66
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	66
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	3	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	67
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	67
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	4	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	68
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	68
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	5	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	69
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	69
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	6	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	70
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	70
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	7	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	71
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	71
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	8	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	72
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	72
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	9	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	73
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	73
J721S2_DEV_NAVSS0_INTR_0	227	10	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	74
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	74
J721S2_DEV_NAVSS0_INTR_0	227	11	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	75
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	75
J721S2_DEV_NAVSS0_INTR_0	227	12	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	76
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	76
J721S2_DEV_NAVSS0_INTR_0	227	13	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	77
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	77
J721S2_DEV_NAVSS0_INTR_0	227	14	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	78
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	78
J721S2_DEV_NAVSS0_INTR_0	227	15	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	79
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	79
J721S2_DEV_NAVSS0_INTR_0	227	16	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	80
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	80
J721S2_DEV_NAVSS0_INTR_0	227	17	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	81
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	81
J721S2_DEV_NAVSS0_INTR_0	227	18	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	82
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	82
J721S2_DEV_NAVSS0_INTR_0	227	19	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	83
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	83
J721S2_DEV_NAVSS0_INTR_0	227	20	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	84
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	84
J721S2_DEV_NAVSS0_INTR_0	227	21	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	85
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	85
J721S2_DEV_NAVSS0_INTR_0	227	22	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	86
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	86
J721S2_DEV_NAVSS0_INTR_0	227	23	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	87
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	87
J721S2_DEV_NAVSS0_INTR_0	227	24	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	88
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	88
J721S2_DEV_NAVSS0_INTR_0	227	25	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	89
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	89
J721S2_DEV_NAVSS0_INTR_0	227	26	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	90
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	90
J721S2_DEV_NAVSS0_INTR_0	227	27	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	91
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	91
J721S2_DEV_NAVSS0_INTR_0	227	28	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	92
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	92
J721S2_DEV_NAVSS0_INTR_0	227	29	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	93
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	93
J721S2_DEV_NAVSS0_INTR_0	227	30	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	94
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	94
J721S2_DEV_NAVSS0_INTR_0	227	31	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	95
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	95
J721S2_DEV_NAVSS0_INTR_0	227	32	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	96
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	96
J721S2_DEV_NAVSS0_INTR_0	227	33	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	97
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	97
J721S2_DEV_NAVSS0_INTR_0	227	34	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	98
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	98
J721S2_DEV_NAVSS0_INTR_0	227	35	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	99
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	99
J721S2_DEV_NAVSS0_INTR_0	227	36	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	100
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	100
J721S2_DEV_NAVSS0_INTR_0	227	37	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	101
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	101
J721S2_DEV_NAVSS0_INTR_0	227	38	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	102
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	102
J721S2_DEV_NAVSS0_INTR_0	227	39	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	103
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	103
J721S2_DEV_NAVSS0_INTR_0	227	40	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	104
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	104
J721S2_DEV_NAVSS0_INTR_0	227	41	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	105
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	105
J721S2_DEV_NAVSS0_INTR_0	227	42	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	106
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	106
J721S2_DEV_NAVSS0_INTR_0	227	43	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	107
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	107
J721S2_DEV_NAVSS0_INTR_0	227	44	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	108
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	108
J721S2_DEV_NAVSS0_INTR_0	227	45	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	109
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	109
J721S2_DEV_NAVSS0_INTR_0	227	46	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	110
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	110
J721S2_DEV_NAVSS0_INTR_0	227	47	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	111
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	111
J721S2_DEV_NAVSS0_INTR_0	227	48	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	112
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	112
J721S2_DEV_NAVSS0_INTR_0	227	49	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	113
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	113
J721S2_DEV_NAVSS0_INTR_0	227	50	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	114
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	114
J721S2_DEV_NAVSS0_INTR_0	227	51	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	115
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	115
J721S2_DEV_NAVSS0_INTR_0	227	52	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	116
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	116
J721S2_DEV_NAVSS0_INTR_0	227	53	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	117
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	117
J721S2_DEV_NAVSS0_INTR_0	227	54	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	118
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	118
J721S2_DEV_NAVSS0_INTR_0	227	55	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	119
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	119
J721S2_DEV_NAVSS0_INTR_0	227	56	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	120
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	120
J721S2_DEV_NAVSS0_INTR_0	227	57	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	121
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	121
J721S2_DEV_NAVSS0_INTR_0	227	58	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	122
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	122
J721S2_DEV_NAVSS0_INTR_0	227	59	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	123
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	123
J721S2_DEV_NAVSS0_INTR_0	227	60	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	124
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	124
J721S2_DEV_NAVSS0_INTR_0	227	61	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	125
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	125
J721S2_DEV_NAVSS0_INTR_0	227	62	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	126
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	126
J721S2_DEV_NAVSS0_INTR_0	227	63	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	127
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	127
J721S2_DEV_NAVSS0_INTR_0	227	64	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	448
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	448
J721S2_DEV_NAVSS0_INTR_0	227	65	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	449
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	449
J721S2_DEV_NAVSS0_INTR_0	227	66	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	450
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	450
J721S2_DEV_NAVSS0_INTR_0	227	67	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	451
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	451
J721S2_DEV_NAVSS0_INTR_0	227	68	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	452
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	452
J721S2_DEV_NAVSS0_INTR_0	227	69	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	453
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	453
J721S2_DEV_NAVSS0_INTR_0	227	70	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	454
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	454
J721S2_DEV_NAVSS0_INTR_0	227	71	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	455
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	455
J721S2_DEV_NAVSS0_INTR_0	227	72	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	456
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	456
J721S2_DEV_NAVSS0_INTR_0	227	73	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	457
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	457
J721S2_DEV_NAVSS0_INTR_0	227	74	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	458
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	458
J721S2_DEV_NAVSS0_INTR_0	227	75	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	459
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	459
J721S2_DEV_NAVSS0_INTR_0	227	76	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	460
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	460
J721S2_DEV_NAVSS0_INTR_0	227	77	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	461
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	461
J721S2_DEV_NAVSS0_INTR_0	227	78	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	462
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	462
J721S2_DEV_NAVSS0_INTR_0	227	79	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	463
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	463
J721S2_DEV_NAVSS0_INTR_0	227	80	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	464
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	464
J721S2_DEV_NAVSS0_INTR_0	227	81	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	465
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	465
J721S2_DEV_NAVSS0_INTR_0	227	82	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	466
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	466
J721S2_DEV_NAVSS0_INTR_0	227	83	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	467
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	467
J721S2_DEV_NAVSS0_INTR_0	227	84	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	468
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	468
J721S2_DEV_NAVSS0_INTR_0	227	85	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	469
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	469
J721S2_DEV_NAVSS0_INTR_0	227	86	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	470
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	470
J721S2_DEV_NAVSS0_INTR_0	227	87	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	471
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	471
J721S2_DEV_NAVSS0_INTR_0	227	88	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	472
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	472
J721S2_DEV_NAVSS0_INTR_0	227	89	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	473
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	473
J721S2_DEV_NAVSS0_INTR_0	227	90	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	474
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	474
J721S2_DEV_NAVSS0_INTR_0	227	91	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	475
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	475
J721S2_DEV_NAVSS0_INTR_0	227	92	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	476
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	476
J721S2_DEV_NAVSS0_INTR_0	227	93	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	477
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	477
J721S2_DEV_NAVSS0_INTR_0	227	94	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	478
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	478
J721S2_DEV_NAVSS0_INTR_0	227	95	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	479
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	479
J721S2_DEV_NAVSS0_INTR_0	227	96	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	480
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	480
J721S2_DEV_NAVSS0_INTR_0	227	97	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	481
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	481
J721S2_DEV_NAVSS0_INTR_0	227	98	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	482
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	482
J721S2_DEV_NAVSS0_INTR_0	227	99	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	483
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	483
J721S2_DEV_NAVSS0_INTR_0	227	100	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	484
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	484
J721S2_DEV_NAVSS0_INTR_0	227	101	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	485
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	485
J721S2_DEV_NAVSS0_INTR_0	227	102	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	486
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	486
J721S2_DEV_NAVSS0_INTR_0	227	103	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	487
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	487
J721S2_DEV_NAVSS0_INTR_0	227	104	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	488
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	488
J721S2_DEV_NAVSS0_INTR_0	227	105	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	489
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	489
J721S2_DEV_NAVSS0_INTR_0	227	106	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	490
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	490
J721S2_DEV_NAVSS0_INTR_0	227	107	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	491
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	491
J721S2_DEV_NAVSS0_INTR_0	227	108	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	492
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	492
J721S2_DEV_NAVSS0_INTR_0	227	109	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	493
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	493
J721S2_DEV_NAVSS0_INTR_0	227	110	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	494
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	494
J721S2_DEV_NAVSS0_INTR_0	227	111	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	495
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	495
J721S2_DEV_NAVSS0_INTR_0	227	112	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	496
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	496
J721S2_DEV_NAVSS0_INTR_0	227	113	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	497
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	497
J721S2_DEV_NAVSS0_INTR_0	227	114	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	498
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	498
J721S2_DEV_NAVSS0_INTR_0	227	115	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	499
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	499
J721S2_DEV_NAVSS0_INTR_0	227	116	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	500
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	500
J721S2_DEV_NAVSS0_INTR_0	227	117	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	501
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	501
J721S2_DEV_NAVSS0_INTR_0	227	118	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	502
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	502
J721S2_DEV_NAVSS0_INTR_0	227	119	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	503
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	503
J721S2_DEV_NAVSS0_INTR_0	227	120	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	504
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	504
J721S2_DEV_NAVSS0_INTR_0	227	121	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	505
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	505
J721S2_DEV_NAVSS0_INTR_0	227	122	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	506
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	506
J721S2_DEV_NAVSS0_INTR_0	227	123	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	507
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	507
J721S2_DEV_NAVSS0_INTR_0	227	124	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	508
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	508
J721S2_DEV_NAVSS0_INTR_0	227	125	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	509
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	509
J721S2_DEV_NAVSS0_INTR_0	227	126	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	510
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	510
J721S2_DEV_NAVSS0_INTR_0	227	127	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	511
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	511
J721S2_DEV_NAVSS0_INTR_0	227	128	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	672
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	672
J721S2_DEV_NAVSS0_INTR_0	227	129	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	673
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	673
J721S2_DEV_NAVSS0_INTR_0	227	130	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	674
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	674
J721S2_DEV_NAVSS0_INTR_0	227	131	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	675
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	675
J721S2_DEV_NAVSS0_INTR_0	227	132	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	676
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	676
J721S2_DEV_NAVSS0_INTR_0	227	133	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	677
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	677
J721S2_DEV_NAVSS0_INTR_0	227	134	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	678
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	678
J721S2_DEV_NAVSS0_INTR_0	227	135	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	679
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	679
J721S2_DEV_NAVSS0_INTR_0	227	136	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	680
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	680
J721S2_DEV_NAVSS0_INTR_0	227	137	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	681
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	681
J721S2_DEV_NAVSS0_INTR_0	227	138	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	682
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	682
J721S2_DEV_NAVSS0_INTR_0	227	139	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	683
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	683
J721S2_DEV_NAVSS0_INTR_0	227	140	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	684
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	684
J721S2_DEV_NAVSS0_INTR_0	227	141	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	685
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	685
J721S2_DEV_NAVSS0_INTR_0	227	142	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	686
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	686
J721S2_DEV_NAVSS0_INTR_0	227	143	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	687
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	687
J721S2_DEV_NAVSS0_INTR_0	227	144	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	688
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	688
J721S2_DEV_NAVSS0_INTR_0	227	145	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	689
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	689
J721S2_DEV_NAVSS0_INTR_0	227	146	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	690
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	690
J721S2_DEV_NAVSS0_INTR_0	227	147	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	691
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	691
J721S2_DEV_NAVSS0_INTR_0	227	148	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	692
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	692
J721S2_DEV_NAVSS0_INTR_0	227	149	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	693
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	693
J721S2_DEV_NAVSS0_INTR_0	227	150	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	694
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	694
J721S2_DEV_NAVSS0_INTR_0	227	151	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	695
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	695
J721S2_DEV_NAVSS0_INTR_0	227	152	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	696
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	696
J721S2_DEV_NAVSS0_INTR_0	227	153	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	697
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	697
J721S2_DEV_NAVSS0_INTR_0	227	154	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	698
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	698
J721S2_DEV_NAVSS0_INTR_0	227	155	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	699
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	699
J721S2_DEV_NAVSS0_INTR_0	227	156	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	700
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	700
J721S2_DEV_NAVSS0_INTR_0	227	157	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	701
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	701
J721S2_DEV_NAVSS0_INTR_0	227	158	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	702
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	702
J721S2_DEV_NAVSS0_INTR_0	227	159	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	703
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	703
J721S2_DEV_NAVSS0_INTR_0	227	160	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	704
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	704
J721S2_DEV_NAVSS0_INTR_0	227	161	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	705
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	705
J721S2_DEV_NAVSS0_INTR_0	227	162	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	706
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	706
J721S2_DEV_NAVSS0_INTR_0	227	163	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	707
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	707
J721S2_DEV_NAVSS0_INTR_0	227	164	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	708
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	708
J721S2_DEV_NAVSS0_INTR_0	227	165	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	709
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	709
J721S2_DEV_NAVSS0_INTR_0	227	166	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	710
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	710
J721S2_DEV_NAVSS0_INTR_0	227	167	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	711
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	711
J721S2_DEV_NAVSS0_INTR_0	227	168	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	712
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	712
J721S2_DEV_NAVSS0_INTR_0	227	169	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	713
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	713
J721S2_DEV_NAVSS0_INTR_0	227	170	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	714
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	714
J721S2_DEV_NAVSS0_INTR_0	227	171	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	715
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	715
J721S2_DEV_NAVSS0_INTR_0	227	172	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	716
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	716
J721S2_DEV_NAVSS0_INTR_0	227	173	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	717
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	717
J721S2_DEV_NAVSS0_INTR_0	227	174	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	718
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	718
J721S2_DEV_NAVSS0_INTR_0	227	175	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	719
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	719
J721S2_DEV_NAVSS0_INTR_0	227	176	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	720
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	720
J721S2_DEV_NAVSS0_INTR_0	227	177	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	721
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	721
J721S2_DEV_NAVSS0_INTR_0	227	178	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	722
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	722
J721S2_DEV_NAVSS0_INTR_0	227	179	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	723
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	723
J721S2_DEV_NAVSS0_INTR_0	227	180	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	724
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	724
J721S2_DEV_NAVSS0_INTR_0	227	181	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	725
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	725
J721S2_DEV_NAVSS0_INTR_0	227	182	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	726
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	726
J721S2_DEV_NAVSS0_INTR_0	227	183	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	727
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	727
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	184	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	728
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	728
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	185	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	729
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	729
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	186	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	730
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	730
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	187	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	731
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	731
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	188	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	732
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	732
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	189	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	733
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	733
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	190	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	734
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	734
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	191	J721S2_DEV_COMPUTE_CLUSTER0_CLEC	soc_events_in	735
			J721S2_DEV_COMPUTE_CLUSTER0_GIC500SS	spi	735
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	192	J721S2_DEV_R5FSS0_CORE0	intr	224
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	193	J721S2_DEV_R5FSS0_CORE0	intr	225
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	194	J721S2_DEV_R5FSS0_CORE0	intr	226
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	195	J721S2_DEV_R5FSS0_CORE0	intr	227
J721S2_DEV_NAVSS0_INTR_0	227	196	J721S2_DEV_R5FSS0_CORE0	intr	228
J721S2_DEV_NAVSS0_INTR_0	227	197	J721S2_DEV_R5FSS0_CORE0	intr	229
J721S2_DEV_NAVSS0_INTR_0	227	198	J721S2_DEV_R5FSS0_CORE0	intr	230
J721S2_DEV_NAVSS0_INTR_0	227	199	J721S2_DEV_R5FSS0_CORE0	intr	231
J721S2_DEV_NAVSS0_INTR_0	227	200	J721S2_DEV_R5FSS0_CORE0	intr	232
J721S2_DEV_NAVSS0_INTR_0	227	201	J721S2_DEV_R5FSS0_CORE0	intr	233
J721S2_DEV_NAVSS0_INTR_0	227	202	J721S2_DEV_R5FSS0_CORE0	intr	234
J721S2_DEV_NAVSS0_INTR_0	227	203	J721S2_DEV_R5FSS0_CORE0	intr	235
J721S2_DEV_NAVSS0_INTR_0	227	204	J721S2_DEV_R5FSS0_CORE0	intr	236
J721S2_DEV_NAVSS0_INTR_0	227	205	J721S2_DEV_R5FSS0_CORE0	intr	237
J721S2_DEV_NAVSS0_INTR_0	227	206	J721S2_DEV_R5FSS0_CORE0	intr	238
J721S2_DEV_NAVSS0_INTR_0	227	207	J721S2_DEV_R5FSS0_CORE0	intr	239
J721S2_DEV_NAVSS0_INTR_0	227	208	J721S2_DEV_R5FSS0_CORE0	intr	240
J721S2_DEV_NAVSS0_INTR_0	227	209	J721S2_DEV_R5FSS0_CORE0	intr	241
J721S2_DEV_NAVSS0_INTR_0	227	210	J721S2_DEV_R5FSS0_CORE0	intr	242
J721S2_DEV_NAVSS0_INTR_0	227	211	J721S2_DEV_R5FSS0_CORE0	intr	243
J721S2_DEV_NAVSS0_INTR_0	227	212	J721S2_DEV_R5FSS0_CORE0	intr	244
J721S2_DEV_NAVSS0_INTR_0	227	213	J721S2_DEV_R5FSS0_CORE0	intr	245
J721S2_DEV_NAVSS0_INTR_0	227	214	J721S2_DEV_R5FSS0_CORE0	intr	246
J721S2_DEV_NAVSS0_INTR_0	227	215	J721S2_DEV_R5FSS0_CORE0	intr	247
J721S2_DEV_NAVSS0_INTR_0	227	216	J721S2_DEV_R5FSS0_CORE0	intr	248
J721S2_DEV_NAVSS0_INTR_0	227	217	J721S2_DEV_R5FSS0_CORE0	intr	249
J721S2_DEV_NAVSS0_INTR_0	227	218	J721S2_DEV_R5FSS0_CORE0	intr	250
J721S2_DEV_NAVSS0_INTR_0	227	219	J721S2_DEV_R5FSS0_CORE0	intr	251
J721S2_DEV_NAVSS0_INTR_0	227	220	J721S2_DEV_R5FSS0_CORE0	intr	252
J721S2_DEV_NAVSS0_INTR_0	227	221	J721S2_DEV_R5FSS0_CORE0	intr	253
J721S2_DEV_NAVSS0_INTR_0	227	222	J721S2_DEV_R5FSS0_CORE0	intr	254
J721S2_DEV_NAVSS0_INTR_0	227	223	J721S2_DEV_R5FSS0_CORE0	intr	255
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	224	J721S2_DEV_R5FSS0_CORE1	intr	224
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	225	J721S2_DEV_R5FSS0_CORE1	intr	225
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	226	J721S2_DEV_R5FSS0_CORE1	intr	226
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	227	J721S2_DEV_R5FSS0_CORE1	intr	227
J721S2_DEV_NAVSS0_INTR_0	227	228	J721S2_DEV_R5FSS0_CORE1	intr	228
J721S2_DEV_NAVSS0_INTR_0	227	229	J721S2_DEV_R5FSS0_CORE1	intr	229
J721S2_DEV_NAVSS0_INTR_0	227	230	J721S2_DEV_R5FSS0_CORE1	intr	230
J721S2_DEV_NAVSS0_INTR_0	227	231	J721S2_DEV_R5FSS0_CORE1	intr	231
J721S2_DEV_NAVSS0_INTR_0	227	232	J721S2_DEV_R5FSS0_CORE1	intr	232
J721S2_DEV_NAVSS0_INTR_0	227	233	J721S2_DEV_R5FSS0_CORE1	intr	233
J721S2_DEV_NAVSS0_INTR_0	227	234	J721S2_DEV_R5FSS0_CORE1	intr	234
J721S2_DEV_NAVSS0_INTR_0	227	235	J721S2_DEV_R5FSS0_CORE1	intr	235
J721S2_DEV_NAVSS0_INTR_0	227	236	J721S2_DEV_R5FSS0_CORE1	intr	236
J721S2_DEV_NAVSS0_INTR_0	227	237	J721S2_DEV_R5FSS0_CORE1	intr	237
J721S2_DEV_NAVSS0_INTR_0	227	238	J721S2_DEV_R5FSS0_CORE1	intr	238
J721S2_DEV_NAVSS0_INTR_0	227	239	J721S2_DEV_R5FSS0_CORE1	intr	239
J721S2_DEV_NAVSS0_INTR_0	227	240	J721S2_DEV_R5FSS0_CORE1	intr	240
J721S2_DEV_NAVSS0_INTR_0	227	241	J721S2_DEV_R5FSS0_CORE1	intr	241
J721S2_DEV_NAVSS0_INTR_0	227	242	J721S2_DEV_R5FSS0_CORE1	intr	242
J721S2_DEV_NAVSS0_INTR_0	227	243	J721S2_DEV_R5FSS0_CORE1	intr	243
J721S2_DEV_NAVSS0_INTR_0	227	244	J721S2_DEV_R5FSS0_CORE1	intr	244
J721S2_DEV_NAVSS0_INTR_0	227	245	J721S2_DEV_R5FSS0_CORE1	intr	245
J721S2_DEV_NAVSS0_INTR_0	227	246	J721S2_DEV_R5FSS0_CORE1	intr	246
J721S2_DEV_NAVSS0_INTR_0	227	247	J721S2_DEV_R5FSS0_CORE1	intr	247
J721S2_DEV_NAVSS0_INTR_0	227	248	J721S2_DEV_R5FSS0_CORE1	intr	248
J721S2_DEV_NAVSS0_INTR_0	227	249	J721S2_DEV_R5FSS0_CORE1	intr	249
J721S2_DEV_NAVSS0_INTR_0	227	250	J721S2_DEV_R5FSS0_CORE1	intr	250
J721S2_DEV_NAVSS0_INTR_0	227	251	J721S2_DEV_R5FSS0_CORE1	intr	251
J721S2_DEV_NAVSS0_INTR_0	227	252	J721S2_DEV_R5FSS0_CORE1	intr	252
J721S2_DEV_NAVSS0_INTR_0	227	253	J721S2_DEV_R5FSS0_CORE1	intr	253
J721S2_DEV_NAVSS0_INTR_0	227	254	J721S2_DEV_R5FSS0_CORE1	intr	254
J721S2_DEV_NAVSS0_INTR_0	227	255	J721S2_DEV_R5FSS0_CORE1	intr	255
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	256	J721S2_DEV_R5FSS1_CORE0	intr	224
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	257	J721S2_DEV_R5FSS1_CORE0	intr	225
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	258	J721S2_DEV_R5FSS1_CORE0	intr	226
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	259	J721S2_DEV_R5FSS1_CORE0	intr	227
J721S2_DEV_NAVSS0_INTR_0	227	260	J721S2_DEV_R5FSS1_CORE0	intr	228
J721S2_DEV_NAVSS0_INTR_0	227	261	J721S2_DEV_R5FSS1_CORE0	intr	229
J721S2_DEV_NAVSS0_INTR_0	227	262	J721S2_DEV_R5FSS1_CORE0	intr	230
J721S2_DEV_NAVSS0_INTR_0	227	263	J721S2_DEV_R5FSS1_CORE0	intr	231
J721S2_DEV_NAVSS0_INTR_0	227	264	J721S2_DEV_R5FSS1_CORE0	intr	232
J721S2_DEV_NAVSS0_INTR_0	227	265	J721S2_DEV_R5FSS1_CORE0	intr	233
J721S2_DEV_NAVSS0_INTR_0	227	266	J721S2_DEV_R5FSS1_CORE0	intr	234
J721S2_DEV_NAVSS0_INTR_0	227	267	J721S2_DEV_R5FSS1_CORE0	intr	235
J721S2_DEV_NAVSS0_INTR_0	227	268	J721S2_DEV_R5FSS1_CORE0	intr	236
J721S2_DEV_NAVSS0_INTR_0	227	269	J721S2_DEV_R5FSS1_CORE0	intr	237
J721S2_DEV_NAVSS0_INTR_0	227	270	J721S2_DEV_R5FSS1_CORE0	intr	238
J721S2_DEV_NAVSS0_INTR_0	227	271	J721S2_DEV_R5FSS1_CORE0	intr	239
J721S2_DEV_NAVSS0_INTR_0	227	272	J721S2_DEV_R5FSS1_CORE0	intr	240
J721S2_DEV_NAVSS0_INTR_0	227	273	J721S2_DEV_R5FSS1_CORE0	intr	241
J721S2_DEV_NAVSS0_INTR_0	227	274	J721S2_DEV_R5FSS1_CORE0	intr	242
J721S2_DEV_NAVSS0_INTR_0	227	275	J721S2_DEV_R5FSS1_CORE0	intr	243
J721S2_DEV_NAVSS0_INTR_0	227	276	J721S2_DEV_R5FSS1_CORE0	intr	244
J721S2_DEV_NAVSS0_INTR_0	227	277	J721S2_DEV_R5FSS1_CORE0	intr	245
J721S2_DEV_NAVSS0_INTR_0	227	278	J721S2_DEV_R5FSS1_CORE0	intr	246
J721S2_DEV_NAVSS0_INTR_0	227	279	J721S2_DEV_R5FSS1_CORE0	intr	247
J721S2_DEV_NAVSS0_INTR_0	227	280	J721S2_DEV_R5FSS1_CORE0	intr	248
J721S2_DEV_NAVSS0_INTR_0	227	281	J721S2_DEV_R5FSS1_CORE0	intr	249
J721S2_DEV_NAVSS0_INTR_0	227	282	J721S2_DEV_R5FSS1_CORE0	intr	250
J721S2_DEV_NAVSS0_INTR_0	227	283	J721S2_DEV_R5FSS1_CORE0	intr	251
J721S2_DEV_NAVSS0_INTR_0	227	284	J721S2_DEV_R5FSS1_CORE0	intr	252
J721S2_DEV_NAVSS0_INTR_0	227	285	J721S2_DEV_R5FSS1_CORE0	intr	253
J721S2_DEV_NAVSS0_INTR_0	227	286	J721S2_DEV_R5FSS1_CORE0	intr	254
J721S2_DEV_NAVSS0_INTR_0	227	287	J721S2_DEV_R5FSS1_CORE0	intr	255
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	288	J721S2_DEV_R5FSS1_CORE1	intr	224
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	289	J721S2_DEV_R5FSS1_CORE1	intr	225
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	290	J721S2_DEV_R5FSS1_CORE1	intr	226
J721S2_DEV_NAVSS0_INTR_0 (Reserved by System Firmware)	227	291	J721S2_DEV_R5FSS1_CORE1	intr	227
J721S2_DEV_NAVSS0_INTR_0	227	292	J721S2_DEV_R5FSS1_CORE1	intr	228
J721S2_DEV_NAVSS0_INTR_0	227	293	J721S2_DEV_R5FSS1_CORE1	intr	229
J721S2_DEV_NAVSS0_INTR_0	227	294	J721S2_DEV_R5FSS1_CORE1	intr	230
J721S2_DEV_NAVSS0_INTR_0	227	295	J721S2_DEV_R5FSS1_CORE1	intr	231
J721S2_DEV_NAVSS0_INTR_0	227	296	J721S2_DEV_R5FSS1_CORE1	intr	232
J721S2_DEV_NAVSS0_INTR_0	227	297	J721S2_DEV_R5FSS1_CORE1	intr	233
J721S2_DEV_NAVSS0_INTR_0	227	298	J721S2_DEV_R5FSS1_CORE1	intr	234
J721S2_DEV_NAVSS0_INTR_0	227	299	J721S2_DEV_R5FSS1_CORE1	intr	235
J721S2_DEV_NAVSS0_INTR_0	227	300	J721S2_DEV_R5FSS1_CORE1	intr	236
J721S2_DEV_NAVSS0_INTR_0	227	301	J721S2_DEV_R5FSS1_CORE1	intr	237
J721S2_DEV_NAVSS0_INTR_0	227	302	J721S2_DEV_R5FSS1_CORE1	intr	238
J721S2_DEV_NAVSS0_INTR_0	227	303	J721S2_DEV_R5FSS1_CORE1	intr	239
J721S2_DEV_NAVSS0_INTR_0	227	304	J721S2_DEV_R5FSS1_CORE1	intr	240
J721S2_DEV_NAVSS0_INTR_0	227	305	J721S2_DEV_R5FSS1_CORE1	intr	241
J721S2_DEV_NAVSS0_INTR_0	227	306	J721S2_DEV_R5FSS1_CORE1	intr	242
J721S2_DEV_NAVSS0_INTR_0	227	307	J721S2_DEV_R5FSS1_CORE1	intr	243
J721S2_DEV_NAVSS0_INTR_0	227	308	J721S2_DEV_R5FSS1_CORE1	intr	244
J721S2_DEV_NAVSS0_INTR_0	227	309	J721S2_DEV_R5FSS1_CORE1	intr	245
J721S2_DEV_NAVSS0_INTR_0	227	310	J721S2_DEV_R5FSS1_CORE1	intr	246
J721S2_DEV_NAVSS0_INTR_0	227	311	J721S2_DEV_R5FSS1_CORE1	intr	247
J721S2_DEV_NAVSS0_INTR_0	227	312	J721S2_DEV_R5FSS1_CORE1	intr	248
J721S2_DEV_NAVSS0_INTR_0	227	313	J721S2_DEV_R5FSS1_CORE1	intr	249
J721S2_DEV_NAVSS0_INTR_0	227	314	J721S2_DEV_R5FSS1_CORE1	intr	250
J721S2_DEV_NAVSS0_INTR_0	227	315	J721S2_DEV_R5FSS1_CORE1	intr	251
J721S2_DEV_NAVSS0_INTR_0	227	316	J721S2_DEV_R5FSS1_CORE1	intr	252
J721S2_DEV_NAVSS0_INTR_0	227	317	J721S2_DEV_R5FSS1_CORE1	intr	253
J721S2_DEV_NAVSS0_INTR_0	227	318	J721S2_DEV_R5FSS1_CORE1	intr	254
J721S2_DEV_NAVSS0_INTR_0	227	319	J721S2_DEV_R5FSS1_CORE1	intr	255
J721S2_DEV_NAVSS0_INTR_0	227	320	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	321	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	322	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	323	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	324	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	325	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	326	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	327	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	328	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	329	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	330	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	331	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	332	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	333	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	334	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	335	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	336	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	337	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	338	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	339	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	340	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	341	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	342	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	343	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	344	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	345	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	346	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	347	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	348	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	349	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	350	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	351	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	352	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	353	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	354	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	355	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	356	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	357	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	358	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	359	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	360	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	361	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	362	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	363	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	364	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	365	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	366	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	367	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	368	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	369	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	370	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	371	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	372	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	373	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	374	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	375	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	376	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	377	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	378	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	379	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	380	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	381	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	382	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	383	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	384	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	385	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	386	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	387	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	388	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	389	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	390	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	391	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	392	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	393	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	394	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	395	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	396	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	397	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	398	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	399	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	400	J721S2_DEV_MCU_R5FSS0_CORE0	intr	376
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	376
J721S2_DEV_NAVSS0_INTR_0	227	401	J721S2_DEV_MCU_R5FSS0_CORE0	intr	377
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	377
J721S2_DEV_NAVSS0_INTR_0	227	402	J721S2_DEV_MCU_R5FSS0_CORE0	intr	378
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	378
J721S2_DEV_NAVSS0_INTR_0	227	403	J721S2_DEV_MCU_R5FSS0_CORE0	intr	379
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	379
J721S2_DEV_NAVSS0_INTR_0	227	404	J721S2_DEV_MCU_R5FSS0_CORE0	intr	380
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	380
J721S2_DEV_NAVSS0_INTR_0	227	405	J721S2_DEV_MCU_R5FSS0_CORE0	intr	381
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	381
J721S2_DEV_NAVSS0_INTR_0	227	406	J721S2_DEV_MCU_R5FSS0_CORE0	intr	382
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	382
J721S2_DEV_NAVSS0_INTR_0	227	407	J721S2_DEV_MCU_R5FSS0_CORE0	intr	383
			J721S2_DEV_MCU_R5FSS0_CORE1	intr	383
J721S2_DEV_NAVSS0_INTR_0	227	408	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	0
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	32
J721S2_DEV_NAVSS0_INTR_0	227	409	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	1
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	33
J721S2_DEV_NAVSS0_INTR_0	227	410	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	2
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	34
J721S2_DEV_NAVSS0_INTR_0	227	411	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	3
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	35
J721S2_DEV_NAVSS0_INTR_0	227	412	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	4
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	36
J721S2_DEV_NAVSS0_INTR_0	227	413	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	5
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	37
J721S2_DEV_NAVSS0_INTR_0	227	414	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	6
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	38
J721S2_DEV_NAVSS0_INTR_0	227	415	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	7
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	39
J721S2_DEV_NAVSS0_INTR_0	227	416	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	8
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	40
J721S2_DEV_NAVSS0_INTR_0	227	417	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	9
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	41
J721S2_DEV_NAVSS0_INTR_0	227	418	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	10
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	42
J721S2_DEV_NAVSS0_INTR_0	227	419	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	11
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	43
J721S2_DEV_NAVSS0_INTR_0	227	420	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	12
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	44
J721S2_DEV_NAVSS0_INTR_0	227	421	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	13
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	45
J721S2_DEV_NAVSS0_INTR_0	227	422	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	14
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	46
J721S2_DEV_NAVSS0_INTR_0	227	423	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	15
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	47
J721S2_DEV_NAVSS0_INTR_0	227	424	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	16
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	48
J721S2_DEV_NAVSS0_INTR_0	227	425	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	17
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	49
J721S2_DEV_NAVSS0_INTR_0	227	426	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	18
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	50
J721S2_DEV_NAVSS0_INTR_0	227	427	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	19
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	51
J721S2_DEV_NAVSS0_INTR_0	227	428	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	20
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	52
J721S2_DEV_NAVSS0_INTR_0	227	429	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	21
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	53
J721S2_DEV_NAVSS0_INTR_0	227	430	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	22
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	54
J721S2_DEV_NAVSS0_INTR_0	227	431	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	23
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	55
J721S2_DEV_NAVSS0_INTR_0	227	432	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	24
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	56
J721S2_DEV_NAVSS0_INTR_0	227	433	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	25
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	57
J721S2_DEV_NAVSS0_INTR_0	227	434	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	26
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	58
J721S2_DEV_NAVSS0_INTR_0	227	435	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	27
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	59
J721S2_DEV_NAVSS0_INTR_0	227	436	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	28
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	60
J721S2_DEV_NAVSS0_INTR_0	227	437	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	29
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	61
J721S2_DEV_NAVSS0_INTR_0	227	438	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	30
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	62
J721S2_DEV_NAVSS0_INTR_0	227	439	J721S2_DEV_VUSR_DUAL0	v0_vusr_in_int	31
			J721S2_DEV_VUSR_DUAL0	v1_vusr_in_int	63
J721S2_DEV_NAVSS0_INTR_0	227	440	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	441	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	442	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	443	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	444	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	445	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	446	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	447	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	448	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	449	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	450	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	451	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	452	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	453	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	454	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	455	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	456	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	457	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	458	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	459	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	460	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	461	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	462	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	463	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	464	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	465	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	466	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	467	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	468	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	469	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	470	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	471	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	472	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	473	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	474	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	475	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	476	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	477	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	478	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	479	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	480	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	481	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	482	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	483	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	484	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	485	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	486	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	487	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	488	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	489	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	490	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	491	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	492	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	493	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	494	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	495	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	496	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	497	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	498	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	499	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	500	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	501	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	502	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	503	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	504	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	505	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	506	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	507	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	508	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	509	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	510	Use TRM - Not managed by TISCI
J721S2_DEV_NAVSS0_INTR_0	227	511	Use TRM - Not managed by TISCI

MCU_NAVSS0_INTR_ROUTER_0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Input Index	Source Name	Source Interface	Source Index
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	0	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	0
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	1	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	1
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	2	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	2
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	3	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	3
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	4	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	4
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	5	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	5
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	6	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	6
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	7	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	7
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	8	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	8
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	9	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	9
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	10	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	10
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	11	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	11
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	12	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	12
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	13	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	13
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	14	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	14
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	15	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	15
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	16	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	16
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	17	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	17
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	18	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	18
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	19	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	19
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	20	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	20
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	21	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	21
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	22	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	22
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	23	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	23
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	24	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	24
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	25	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	25
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	26	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	26
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	27	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	27
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	28	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	28
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	29	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	29
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	30	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	30
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	31	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	31
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	32	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	32
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	33	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	33
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	34	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	34
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	35	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	35
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	36	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	36
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	37	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	37
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	38	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	38
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	39	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	39
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	40	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	40
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	41	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	41
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	42	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	42
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	43	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	43
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	44	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	44
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	45	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	45
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	46	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	46
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	47	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	47
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	48	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	48
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	49	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	49
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	50	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	50
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	51	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	51
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	52	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	52
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	53	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	53
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	54	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	54
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	55	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	55
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	56	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	56
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	57	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	57
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	58	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	58
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	59	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	59
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	60	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	60
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	61	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	61
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	62	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	62
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	63	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	63
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	64	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	64
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	65	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	65
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	66	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	66
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	67	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	67
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	68	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	68
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	69	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	69
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	70	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	70
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	71	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	71
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	72	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	72
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	73	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	73
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	74	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	74
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	75	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	75
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	76	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	76
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	77	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	77
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	78	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	78
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	79	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	79
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	80	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	80
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	81	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	81
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	82	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	82
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	83	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	83
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	84	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	84
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	85	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	85
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	86	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	86
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	87	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	87
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	88	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	88
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	89	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	89
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	90	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	90
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	91	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	91
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	92	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	92
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	93	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	93
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	94	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	94
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	95	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	95
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	96	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	96
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	97	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	97
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	98	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	98
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	99	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	99
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	100	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	100
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	101	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	101
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	102	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	102
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	103	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	103
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	104	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	104
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	105	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	105
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	106	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	106
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	107	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	107
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	108	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	108
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	109	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	109
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	110	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	110
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	111	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	111
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	112	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	112
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	113	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	113
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	114	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	114
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	115	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	115
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	116	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	116
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	117	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	117
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	118	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	118
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	119	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	119
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	120	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	120
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	121	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	121
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	122	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	122
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	123	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	123
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	124	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	124
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	125	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	125
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	126	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	126
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	127	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	127
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	128	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	128
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	129	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	129
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	130	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	130
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	131	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	131
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	132	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	132
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	133	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	133
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	134	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	134
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	135	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	135
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	136	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	136
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	137	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	137
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	138	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	138
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	139	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	139
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	140	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	140
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	141	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	141
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	142	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	142
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	143	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	143
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	144	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	144
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	145	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	145
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	146	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	146
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	147	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	147
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	148	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	148
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	149	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	149
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	150	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	150
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	151	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	151
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	152	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	152
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	153	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	153
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	154	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	154
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	155	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	155
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	156	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	156
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	157	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	157
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	158	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	158
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	159	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	159
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	160	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	160
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	161	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	161
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	162	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	162
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	163	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	163
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	164	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	164
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	165	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	165
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	166	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	166
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	167	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	167
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	168	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	168
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	169	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	169
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	170	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	170
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	171	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	171
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	172	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	172
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	173	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	173
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	174	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	174
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	175	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	175
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	176	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	176
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	177	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	177
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	178	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	178
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	179	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	179
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	180	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	180
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	181	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	181
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	182	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	182
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	183	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	183
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	184	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	184
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	185	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	185
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	186	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	186
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	187	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	187
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	188	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	188
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	189	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	189
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	190	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	190
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	191	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	191
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	192	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	192
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	193	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	193
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	194	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	194
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	195	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	195
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	196	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	196
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	197	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	197
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	198	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	198
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	199	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	199
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	200	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	200
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	201	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	201
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	202	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	202
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	203	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	203
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	204	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	204
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	205	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	205
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	206	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	206
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	207	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	207
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	208	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	208
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	209	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	209
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	210	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	210
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	211	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	211
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	212	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	212
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	213	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	213
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	214	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	214
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	215	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	215
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	216	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	216
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	217	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	217
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	218	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	218
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	219	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	219
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	220	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	220
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	221	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	221
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	222	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	222
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	223	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	223
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	224	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	224
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	225	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	225
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	226	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	226
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	227	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	227
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	228	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	228
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	229	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	229
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	230	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	230
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	231	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	231
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	232	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	232
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	233	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	233
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	234	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	234
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	235	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	235
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	236	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	236
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	237	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	237
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	238	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	238
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	239	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	239
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	240	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	240
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	241	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	241
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	242	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	242
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	243	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	243
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	244	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	244
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	245	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	245
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	246	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	246
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	247	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	247
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	248	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	248
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	249	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	249
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	250	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	250
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	251	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	251
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	252	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	252
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	253	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	253
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	254	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	254
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	255	J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	intaggr_vintr_pend	255
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	256	J721S2_DEV_MCU_NAVSS0_MCRC_0	dma_event_intr	0
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	257	J721S2_DEV_MCU_NAVSS0_MCRC_0	dma_event_intr	1
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	258	J721S2_DEV_MCU_NAVSS0_MCRC_0	dma_event_intr	2
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	259	J721S2_DEV_MCU_NAVSS0_MCRC_0	dma_event_intr	3
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	260	J721S2_DEV_MCU_NAVSS0_MCRC_0	intaggr_vintr_pend	4

MCU_NAVSS0_INTR_ROUTER_0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name	IR Device ID	IR Output Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	0	J721S2_DEV_MCU_R5FSS0_CORE0	intr	64
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	1	J721S2_DEV_MCU_R5FSS0_CORE0	intr	65
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	2	J721S2_DEV_MCU_R5FSS0_CORE0	intr	66
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	3	J721S2_DEV_MCU_R5FSS0_CORE0	intr	67
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	4	J721S2_DEV_MCU_R5FSS0_CORE0	intr	68
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	5	J721S2_DEV_MCU_R5FSS0_CORE0	intr	69
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	6	J721S2_DEV_MCU_R5FSS0_CORE0	intr	70
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	7	J721S2_DEV_MCU_R5FSS0_CORE0	intr	71
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	8	J721S2_DEV_MCU_R5FSS0_CORE0	intr	72
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	9	J721S2_DEV_MCU_R5FSS0_CORE0	intr	73
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	10	J721S2_DEV_MCU_R5FSS0_CORE0	intr	74
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	11	J721S2_DEV_MCU_R5FSS0_CORE0	intr	75
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	12	J721S2_DEV_MCU_R5FSS0_CORE0	intr	76
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	13	J721S2_DEV_MCU_R5FSS0_CORE0	intr	77
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	14	J721S2_DEV_MCU_R5FSS0_CORE0	intr	78
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	15	J721S2_DEV_MCU_R5FSS0_CORE0	intr	79
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	16	J721S2_DEV_MCU_R5FSS0_CORE0	intr	80
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	17	J721S2_DEV_MCU_R5FSS0_CORE0	intr	81
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	18	J721S2_DEV_MCU_R5FSS0_CORE0	intr	82
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	19	J721S2_DEV_MCU_R5FSS0_CORE0	intr	83
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	20	J721S2_DEV_MCU_R5FSS0_CORE0	intr	84
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	21	J721S2_DEV_MCU_R5FSS0_CORE0	intr	85
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	22	J721S2_DEV_MCU_R5FSS0_CORE0	intr	86
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	23	J721S2_DEV_MCU_R5FSS0_CORE0	intr	87
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	24	J721S2_DEV_WKUP_HSM0	nvic	48
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	25	J721S2_DEV_WKUP_HSM0	nvic	49
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	26	J721S2_DEV_WKUP_HSM0	nvic	50
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	27	J721S2_DEV_WKUP_HSM0	nvic	51
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	28	J721S2_DEV_WKUP_HSM0	nvic	52
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	29	J721S2_DEV_WKUP_HSM0	nvic	53
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	30	J721S2_DEV_WKUP_HSM0	nvic	54
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	31	J721S2_DEV_WKUP_HSM0	nvic	55
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	32	J721S2_DEV_MCU_R5FSS0_CORE1	intr	64
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	33	J721S2_DEV_MCU_R5FSS0_CORE1	intr	65
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	34	J721S2_DEV_MCU_R5FSS0_CORE1	intr	66
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0 (Reserved by System Firmware)	268	35	J721S2_DEV_MCU_R5FSS0_CORE1	intr	67
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	36	J721S2_DEV_MCU_R5FSS0_CORE1	intr	68
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	37	J721S2_DEV_MCU_R5FSS0_CORE1	intr	69
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	38	J721S2_DEV_MCU_R5FSS0_CORE1	intr	70
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	39	J721S2_DEV_MCU_R5FSS0_CORE1	intr	71
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	40	J721S2_DEV_MCU_R5FSS0_CORE1	intr	72
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	41	J721S2_DEV_MCU_R5FSS0_CORE1	intr	73
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	42	J721S2_DEV_MCU_R5FSS0_CORE1	intr	74
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	43	J721S2_DEV_MCU_R5FSS0_CORE1	intr	75
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	44	J721S2_DEV_MCU_R5FSS0_CORE1	intr	76
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	45	J721S2_DEV_MCU_R5FSS0_CORE1	intr	77
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	46	J721S2_DEV_MCU_R5FSS0_CORE1	intr	78
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	47	J721S2_DEV_MCU_R5FSS0_CORE1	intr	79
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	48	J721S2_DEV_MCU_R5FSS0_CORE1	intr	80
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	49	J721S2_DEV_MCU_R5FSS0_CORE1	intr	81
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	50	J721S2_DEV_MCU_R5FSS0_CORE1	intr	82
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	51	J721S2_DEV_MCU_R5FSS0_CORE1	intr	83
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	52	J721S2_DEV_MCU_R5FSS0_CORE1	intr	84
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	53	J721S2_DEV_MCU_R5FSS0_CORE1	intr	85
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	54	J721S2_DEV_MCU_R5FSS0_CORE1	intr	86
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	55	J721S2_DEV_MCU_R5FSS0_CORE1	intr	87
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	56	J721S2_DEV_WKUP_HSM0	nvic	56
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	57	J721S2_DEV_WKUP_HSM0	nvic	57
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	58	J721S2_DEV_WKUP_HSM0	nvic	58
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	59	J721S2_DEV_WKUP_HSM0	nvic	59
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	60	J721S2_DEV_WKUP_HSM0	nvic	60
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	61	J721S2_DEV_WKUP_HSM0	nvic	61
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	62	J721S2_DEV_WKUP_HSM0	nvic	62
J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	268	63	J721S2_DEV_WKUP_HSM0	nvic	63

Interrupt Aggregator Device IDs

Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J721S2 Device IDs these are the valid Interrupt Aggregator device IDs.

Interrupt Aggregator Device Name	Interrupt Aggregator Device ID
J721S2_DEV_NAVSS0_MODSS_INTA_0	254
J721S2_DEV_NAVSS0_MODSS_INTA_1	255
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275

Interrupt Aggregator Virtual Interrupts

This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Interrupt Aggregator Name	Virtual Interrupt Range
J721S2_DEV_NAVSS0_MODSS_INTA_0	0 to 63
J721S2_DEV_NAVSS0_MODSS_INTA_1	0 to 63
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE)	0 to 33
J721S2_DEV_NAVSS0_UDMASS_INTA_0	34 to 255
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE)	0 to 21
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	22 to 255

NAVSS0_MODSS_INTA_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name	IA Device ID	IA VINT Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	0	J721S2_DEV_NAVSS0_INTR_0	in_intr	320
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	1	J721S2_DEV_NAVSS0_INTR_0	in_intr	321
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	2	J721S2_DEV_NAVSS0_INTR_0	in_intr	322
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	3	J721S2_DEV_NAVSS0_INTR_0	in_intr	323
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	4	J721S2_DEV_NAVSS0_INTR_0	in_intr	324
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	5	J721S2_DEV_NAVSS0_INTR_0	in_intr	325
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	6	J721S2_DEV_NAVSS0_INTR_0	in_intr	326
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	7	J721S2_DEV_NAVSS0_INTR_0	in_intr	327
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	8	J721S2_DEV_NAVSS0_INTR_0	in_intr	328
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	9	J721S2_DEV_NAVSS0_INTR_0	in_intr	329
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	10	J721S2_DEV_NAVSS0_INTR_0	in_intr	330
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	11	J721S2_DEV_NAVSS0_INTR_0	in_intr	331
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	12	J721S2_DEV_NAVSS0_INTR_0	in_intr	332
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	13	J721S2_DEV_NAVSS0_INTR_0	in_intr	333
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	14	J721S2_DEV_NAVSS0_INTR_0	in_intr	334
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	15	J721S2_DEV_NAVSS0_INTR_0	in_intr	335
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	16	J721S2_DEV_NAVSS0_INTR_0	in_intr	336
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	17	J721S2_DEV_NAVSS0_INTR_0	in_intr	337
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	18	J721S2_DEV_NAVSS0_INTR_0	in_intr	338
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	19	J721S2_DEV_NAVSS0_INTR_0	in_intr	339
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	20	J721S2_DEV_NAVSS0_INTR_0	in_intr	340
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	21	J721S2_DEV_NAVSS0_INTR_0	in_intr	341
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	22	J721S2_DEV_NAVSS0_INTR_0	in_intr	342
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	23	J721S2_DEV_NAVSS0_INTR_0	in_intr	343
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	24	J721S2_DEV_NAVSS0_INTR_0	in_intr	344
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	25	J721S2_DEV_NAVSS0_INTR_0	in_intr	345
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	26	J721S2_DEV_NAVSS0_INTR_0	in_intr	346
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	27	J721S2_DEV_NAVSS0_INTR_0	in_intr	347
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	28	J721S2_DEV_NAVSS0_INTR_0	in_intr	348
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	29	J721S2_DEV_NAVSS0_INTR_0	in_intr	349
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	30	J721S2_DEV_NAVSS0_INTR_0	in_intr	350
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	31	J721S2_DEV_NAVSS0_INTR_0	in_intr	351
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	32	J721S2_DEV_NAVSS0_INTR_0	in_intr	352
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	33	J721S2_DEV_NAVSS0_INTR_0	in_intr	353
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	34	J721S2_DEV_NAVSS0_INTR_0	in_intr	354
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	35	J721S2_DEV_NAVSS0_INTR_0	in_intr	355
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	36	J721S2_DEV_NAVSS0_INTR_0	in_intr	356
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	37	J721S2_DEV_NAVSS0_INTR_0	in_intr	357
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	38	J721S2_DEV_NAVSS0_INTR_0	in_intr	358
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	39	J721S2_DEV_NAVSS0_INTR_0	in_intr	359
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	40	J721S2_DEV_NAVSS0_INTR_0	in_intr	360
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	41	J721S2_DEV_NAVSS0_INTR_0	in_intr	361
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	42	J721S2_DEV_NAVSS0_INTR_0	in_intr	362
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	43	J721S2_DEV_NAVSS0_INTR_0	in_intr	363
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	44	J721S2_DEV_NAVSS0_INTR_0	in_intr	364
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	45	J721S2_DEV_NAVSS0_INTR_0	in_intr	365
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	46	J721S2_DEV_NAVSS0_INTR_0	in_intr	366
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	47	J721S2_DEV_NAVSS0_INTR_0	in_intr	367
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	48	J721S2_DEV_NAVSS0_INTR_0	in_intr	368
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	49	J721S2_DEV_NAVSS0_INTR_0	in_intr	369
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	50	J721S2_DEV_NAVSS0_INTR_0	in_intr	370
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	51	J721S2_DEV_NAVSS0_INTR_0	in_intr	371
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	52	J721S2_DEV_NAVSS0_INTR_0	in_intr	372
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	53	J721S2_DEV_NAVSS0_INTR_0	in_intr	373
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	54	J721S2_DEV_NAVSS0_INTR_0	in_intr	374
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	55	J721S2_DEV_NAVSS0_INTR_0	in_intr	375
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	56	J721S2_DEV_NAVSS0_INTR_0	in_intr	376
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	57	J721S2_DEV_NAVSS0_INTR_0	in_intr	377
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	58	J721S2_DEV_NAVSS0_INTR_0	in_intr	378
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	59	J721S2_DEV_NAVSS0_INTR_0	in_intr	379
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	60	J721S2_DEV_NAVSS0_INTR_0	in_intr	380
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	61	J721S2_DEV_NAVSS0_INTR_0	in_intr	381
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	62	J721S2_DEV_NAVSS0_INTR_0	in_intr	382
J721S2_DEV_NAVSS0_MODSS_INTA_0	254	63	J721S2_DEV_NAVSS0_INTR_0	in_intr	383

NAVSS0_MODSS_INTA_1 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name	IA Device ID	IA VINT Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	0	J721S2_DEV_NAVSS0_INTR_0	in_intr	256
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	1	J721S2_DEV_NAVSS0_INTR_0	in_intr	257
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	2	J721S2_DEV_NAVSS0_INTR_0	in_intr	258
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	3	J721S2_DEV_NAVSS0_INTR_0	in_intr	259
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	4	J721S2_DEV_NAVSS0_INTR_0	in_intr	260
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	5	J721S2_DEV_NAVSS0_INTR_0	in_intr	261
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	6	J721S2_DEV_NAVSS0_INTR_0	in_intr	262
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	7	J721S2_DEV_NAVSS0_INTR_0	in_intr	263
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	8	J721S2_DEV_NAVSS0_INTR_0	in_intr	264
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	9	J721S2_DEV_NAVSS0_INTR_0	in_intr	265
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	10	J721S2_DEV_NAVSS0_INTR_0	in_intr	266
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	11	J721S2_DEV_NAVSS0_INTR_0	in_intr	267
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	12	J721S2_DEV_NAVSS0_INTR_0	in_intr	268
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	13	J721S2_DEV_NAVSS0_INTR_0	in_intr	269
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	14	J721S2_DEV_NAVSS0_INTR_0	in_intr	270
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	15	J721S2_DEV_NAVSS0_INTR_0	in_intr	271
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	16	J721S2_DEV_NAVSS0_INTR_0	in_intr	272
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	17	J721S2_DEV_NAVSS0_INTR_0	in_intr	273
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	18	J721S2_DEV_NAVSS0_INTR_0	in_intr	274
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	19	J721S2_DEV_NAVSS0_INTR_0	in_intr	275
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	20	J721S2_DEV_NAVSS0_INTR_0	in_intr	276
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	21	J721S2_DEV_NAVSS0_INTR_0	in_intr	277
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	22	J721S2_DEV_NAVSS0_INTR_0	in_intr	278
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	23	J721S2_DEV_NAVSS0_INTR_0	in_intr	279
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	24	J721S2_DEV_NAVSS0_INTR_0	in_intr	280
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	25	J721S2_DEV_NAVSS0_INTR_0	in_intr	281
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	26	J721S2_DEV_NAVSS0_INTR_0	in_intr	282
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	27	J721S2_DEV_NAVSS0_INTR_0	in_intr	283
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	28	J721S2_DEV_NAVSS0_INTR_0	in_intr	284
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	29	J721S2_DEV_NAVSS0_INTR_0	in_intr	285
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	30	J721S2_DEV_NAVSS0_INTR_0	in_intr	286
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	31	J721S2_DEV_NAVSS0_INTR_0	in_intr	287
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	32	J721S2_DEV_NAVSS0_INTR_0	in_intr	288
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	33	J721S2_DEV_NAVSS0_INTR_0	in_intr	289
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	34	J721S2_DEV_NAVSS0_INTR_0	in_intr	290
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	35	J721S2_DEV_NAVSS0_INTR_0	in_intr	291
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	36	J721S2_DEV_NAVSS0_INTR_0	in_intr	292
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	37	J721S2_DEV_NAVSS0_INTR_0	in_intr	293
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	38	J721S2_DEV_NAVSS0_INTR_0	in_intr	294
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	39	J721S2_DEV_NAVSS0_INTR_0	in_intr	295
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	40	J721S2_DEV_NAVSS0_INTR_0	in_intr	296
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	41	J721S2_DEV_NAVSS0_INTR_0	in_intr	297
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	42	J721S2_DEV_NAVSS0_INTR_0	in_intr	298
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	43	J721S2_DEV_NAVSS0_INTR_0	in_intr	299
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	44	J721S2_DEV_NAVSS0_INTR_0	in_intr	300
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	45	J721S2_DEV_NAVSS0_INTR_0	in_intr	301
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	46	J721S2_DEV_NAVSS0_INTR_0	in_intr	302
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	47	J721S2_DEV_NAVSS0_INTR_0	in_intr	303
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	48	J721S2_DEV_NAVSS0_INTR_0	in_intr	304
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	49	J721S2_DEV_NAVSS0_INTR_0	in_intr	305
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	50	J721S2_DEV_NAVSS0_INTR_0	in_intr	306
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	51	J721S2_DEV_NAVSS0_INTR_0	in_intr	307
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	52	J721S2_DEV_NAVSS0_INTR_0	in_intr	308
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	53	J721S2_DEV_NAVSS0_INTR_0	in_intr	309
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	54	J721S2_DEV_NAVSS0_INTR_0	in_intr	310
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	55	J721S2_DEV_NAVSS0_INTR_0	in_intr	311
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	56	J721S2_DEV_NAVSS0_INTR_0	in_intr	312
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	57	J721S2_DEV_NAVSS0_INTR_0	in_intr	313
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	58	J721S2_DEV_NAVSS0_INTR_0	in_intr	314
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	59	J721S2_DEV_NAVSS0_INTR_0	in_intr	315
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	60	J721S2_DEV_NAVSS0_INTR_0	in_intr	316
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	61	J721S2_DEV_NAVSS0_INTR_0	in_intr	317
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	62	J721S2_DEV_NAVSS0_INTR_0	in_intr	318
J721S2_DEV_NAVSS0_MODSS_INTA_1	255	63	J721S2_DEV_NAVSS0_INTR_0	in_intr	319

NAVSS0_UDMASS_INTA_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name	IA Device ID	IA VINT Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	0	J721S2_DEV_NAVSS0_INTR_0	in_intr	0
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	1	J721S2_DEV_NAVSS0_INTR_0	in_intr	1
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	2	J721S2_DEV_NAVSS0_INTR_0	in_intr	2
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	3	J721S2_DEV_NAVSS0_INTR_0	in_intr	3
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	4	J721S2_DEV_NAVSS0_INTR_0	in_intr	4
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	5	J721S2_DEV_NAVSS0_INTR_0	in_intr	5
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	6	J721S2_DEV_NAVSS0_INTR_0	in_intr	6
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	7	J721S2_DEV_NAVSS0_INTR_0	in_intr	7
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	8	J721S2_DEV_NAVSS0_INTR_0	in_intr	8
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	9	J721S2_DEV_NAVSS0_INTR_0	in_intr	9
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	10	J721S2_DEV_NAVSS0_INTR_0	in_intr	10
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	11	J721S2_DEV_NAVSS0_INTR_0	in_intr	11
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	12	J721S2_DEV_NAVSS0_INTR_0	in_intr	12
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	13	J721S2_DEV_NAVSS0_INTR_0	in_intr	13
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	14	J721S2_DEV_NAVSS0_INTR_0	in_intr	14
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	15	J721S2_DEV_NAVSS0_INTR_0	in_intr	15
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	16	J721S2_DEV_NAVSS0_INTR_0	in_intr	16
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	17	J721S2_DEV_NAVSS0_INTR_0	in_intr	17
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	18	J721S2_DEV_NAVSS0_INTR_0	in_intr	18
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	19	J721S2_DEV_NAVSS0_INTR_0	in_intr	19
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	20	J721S2_DEV_NAVSS0_INTR_0	in_intr	20
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	21	J721S2_DEV_NAVSS0_INTR_0	in_intr	21
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	22	J721S2_DEV_NAVSS0_INTR_0	in_intr	22
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	23	J721S2_DEV_NAVSS0_INTR_0	in_intr	23
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	24	J721S2_DEV_NAVSS0_INTR_0	in_intr	24
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	25	J721S2_DEV_NAVSS0_INTR_0	in_intr	25
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	26	J721S2_DEV_NAVSS0_INTR_0	in_intr	26
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	27	J721S2_DEV_NAVSS0_INTR_0	in_intr	27
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	28	J721S2_DEV_NAVSS0_INTR_0	in_intr	28
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	29	J721S2_DEV_NAVSS0_INTR_0	in_intr	29
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	30	J721S2_DEV_NAVSS0_INTR_0	in_intr	30
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	31	J721S2_DEV_NAVSS0_INTR_0	in_intr	31
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	32	J721S2_DEV_NAVSS0_INTR_0	in_intr	32
J721S2_DEV_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	265	33	J721S2_DEV_NAVSS0_INTR_0	in_intr	33
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	34	J721S2_DEV_NAVSS0_INTR_0	in_intr	34
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	35	J721S2_DEV_NAVSS0_INTR_0	in_intr	35
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	36	J721S2_DEV_NAVSS0_INTR_0	in_intr	36
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	37	J721S2_DEV_NAVSS0_INTR_0	in_intr	37
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	38	J721S2_DEV_NAVSS0_INTR_0	in_intr	38
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	39	J721S2_DEV_NAVSS0_INTR_0	in_intr	39
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	40	J721S2_DEV_NAVSS0_INTR_0	in_intr	40
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	41	J721S2_DEV_NAVSS0_INTR_0	in_intr	41
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	42	J721S2_DEV_NAVSS0_INTR_0	in_intr	42
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	43	J721S2_DEV_NAVSS0_INTR_0	in_intr	43
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	44	J721S2_DEV_NAVSS0_INTR_0	in_intr	44
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	45	J721S2_DEV_NAVSS0_INTR_0	in_intr	45
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	46	J721S2_DEV_NAVSS0_INTR_0	in_intr	46
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	47	J721S2_DEV_NAVSS0_INTR_0	in_intr	47
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	48	J721S2_DEV_NAVSS0_INTR_0	in_intr	48
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	49	J721S2_DEV_NAVSS0_INTR_0	in_intr	49
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	50	J721S2_DEV_NAVSS0_INTR_0	in_intr	50
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	51	J721S2_DEV_NAVSS0_INTR_0	in_intr	51
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	52	J721S2_DEV_NAVSS0_INTR_0	in_intr	52
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	53	J721S2_DEV_NAVSS0_INTR_0	in_intr	53
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	54	J721S2_DEV_NAVSS0_INTR_0	in_intr	54
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	55	J721S2_DEV_NAVSS0_INTR_0	in_intr	55
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	56	J721S2_DEV_NAVSS0_INTR_0	in_intr	56
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	57	J721S2_DEV_NAVSS0_INTR_0	in_intr	57
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	58	J721S2_DEV_NAVSS0_INTR_0	in_intr	58
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	59	J721S2_DEV_NAVSS0_INTR_0	in_intr	59
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	60	J721S2_DEV_NAVSS0_INTR_0	in_intr	60
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	61	J721S2_DEV_NAVSS0_INTR_0	in_intr	61
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	62	J721S2_DEV_NAVSS0_INTR_0	in_intr	62
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	63	J721S2_DEV_NAVSS0_INTR_0	in_intr	63
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	64	J721S2_DEV_NAVSS0_INTR_0	in_intr	64
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	65	J721S2_DEV_NAVSS0_INTR_0	in_intr	65
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	66	J721S2_DEV_NAVSS0_INTR_0	in_intr	66
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	67	J721S2_DEV_NAVSS0_INTR_0	in_intr	67
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	68	J721S2_DEV_NAVSS0_INTR_0	in_intr	68
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	69	J721S2_DEV_NAVSS0_INTR_0	in_intr	69
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	70	J721S2_DEV_NAVSS0_INTR_0	in_intr	70
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	71	J721S2_DEV_NAVSS0_INTR_0	in_intr	71
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	72	J721S2_DEV_NAVSS0_INTR_0	in_intr	72
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	73	J721S2_DEV_NAVSS0_INTR_0	in_intr	73
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	74	J721S2_DEV_NAVSS0_INTR_0	in_intr	74
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	75	J721S2_DEV_NAVSS0_INTR_0	in_intr	75
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	76	J721S2_DEV_NAVSS0_INTR_0	in_intr	76
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	77	J721S2_DEV_NAVSS0_INTR_0	in_intr	77
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	78	J721S2_DEV_NAVSS0_INTR_0	in_intr	78
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	79	J721S2_DEV_NAVSS0_INTR_0	in_intr	79
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	80	J721S2_DEV_NAVSS0_INTR_0	in_intr	80
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	81	J721S2_DEV_NAVSS0_INTR_0	in_intr	81
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	82	J721S2_DEV_NAVSS0_INTR_0	in_intr	82
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	83	J721S2_DEV_NAVSS0_INTR_0	in_intr	83
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	84	J721S2_DEV_NAVSS0_INTR_0	in_intr	84
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	85	J721S2_DEV_NAVSS0_INTR_0	in_intr	85
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	86	J721S2_DEV_NAVSS0_INTR_0	in_intr	86
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	87	J721S2_DEV_NAVSS0_INTR_0	in_intr	87
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	88	J721S2_DEV_NAVSS0_INTR_0	in_intr	88
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	89	J721S2_DEV_NAVSS0_INTR_0	in_intr	89
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	90	J721S2_DEV_NAVSS0_INTR_0	in_intr	90
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	91	J721S2_DEV_NAVSS0_INTR_0	in_intr	91
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	92	J721S2_DEV_NAVSS0_INTR_0	in_intr	92
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	93	J721S2_DEV_NAVSS0_INTR_0	in_intr	93
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	94	J721S2_DEV_NAVSS0_INTR_0	in_intr	94
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	95	J721S2_DEV_NAVSS0_INTR_0	in_intr	95
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	96	J721S2_DEV_NAVSS0_INTR_0	in_intr	96
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	97	J721S2_DEV_NAVSS0_INTR_0	in_intr	97
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	98	J721S2_DEV_NAVSS0_INTR_0	in_intr	98
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	99	J721S2_DEV_NAVSS0_INTR_0	in_intr	99
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	100	J721S2_DEV_NAVSS0_INTR_0	in_intr	100
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	101	J721S2_DEV_NAVSS0_INTR_0	in_intr	101
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	102	J721S2_DEV_NAVSS0_INTR_0	in_intr	102
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	103	J721S2_DEV_NAVSS0_INTR_0	in_intr	103
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	104	J721S2_DEV_NAVSS0_INTR_0	in_intr	104
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	105	J721S2_DEV_NAVSS0_INTR_0	in_intr	105
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	106	J721S2_DEV_NAVSS0_INTR_0	in_intr	106
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	107	J721S2_DEV_NAVSS0_INTR_0	in_intr	107
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	108	J721S2_DEV_NAVSS0_INTR_0	in_intr	108
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	109	J721S2_DEV_NAVSS0_INTR_0	in_intr	109
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	110	J721S2_DEV_NAVSS0_INTR_0	in_intr	110
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	111	J721S2_DEV_NAVSS0_INTR_0	in_intr	111
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	112	J721S2_DEV_NAVSS0_INTR_0	in_intr	112
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	113	J721S2_DEV_NAVSS0_INTR_0	in_intr	113
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	114	J721S2_DEV_NAVSS0_INTR_0	in_intr	114
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	115	J721S2_DEV_NAVSS0_INTR_0	in_intr	115
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	116	J721S2_DEV_NAVSS0_INTR_0	in_intr	116
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	117	J721S2_DEV_NAVSS0_INTR_0	in_intr	117
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	118	J721S2_DEV_NAVSS0_INTR_0	in_intr	118
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	119	J721S2_DEV_NAVSS0_INTR_0	in_intr	119
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	120	J721S2_DEV_NAVSS0_INTR_0	in_intr	120
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	121	J721S2_DEV_NAVSS0_INTR_0	in_intr	121
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	122	J721S2_DEV_NAVSS0_INTR_0	in_intr	122
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	123	J721S2_DEV_NAVSS0_INTR_0	in_intr	123
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	124	J721S2_DEV_NAVSS0_INTR_0	in_intr	124
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	125	J721S2_DEV_NAVSS0_INTR_0	in_intr	125
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	126	J721S2_DEV_NAVSS0_INTR_0	in_intr	126
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	127	J721S2_DEV_NAVSS0_INTR_0	in_intr	127
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	128	J721S2_DEV_NAVSS0_INTR_0	in_intr	128
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	129	J721S2_DEV_NAVSS0_INTR_0	in_intr	129
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	130	J721S2_DEV_NAVSS0_INTR_0	in_intr	130
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	131	J721S2_DEV_NAVSS0_INTR_0	in_intr	131
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	132	J721S2_DEV_NAVSS0_INTR_0	in_intr	132
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	133	J721S2_DEV_NAVSS0_INTR_0	in_intr	133
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	134	J721S2_DEV_NAVSS0_INTR_0	in_intr	134
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	135	J721S2_DEV_NAVSS0_INTR_0	in_intr	135
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	136	J721S2_DEV_NAVSS0_INTR_0	in_intr	136
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	137	J721S2_DEV_NAVSS0_INTR_0	in_intr	137
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	138	J721S2_DEV_NAVSS0_INTR_0	in_intr	138
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	139	J721S2_DEV_NAVSS0_INTR_0	in_intr	139
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	140	J721S2_DEV_NAVSS0_INTR_0	in_intr	140
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	141	J721S2_DEV_NAVSS0_INTR_0	in_intr	141
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	142	J721S2_DEV_NAVSS0_INTR_0	in_intr	142
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	143	J721S2_DEV_NAVSS0_INTR_0	in_intr	143
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	144	J721S2_DEV_NAVSS0_INTR_0	in_intr	144
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	145	J721S2_DEV_NAVSS0_INTR_0	in_intr	145
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	146	J721S2_DEV_NAVSS0_INTR_0	in_intr	146
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	147	J721S2_DEV_NAVSS0_INTR_0	in_intr	147
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	148	J721S2_DEV_NAVSS0_INTR_0	in_intr	148
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	149	J721S2_DEV_NAVSS0_INTR_0	in_intr	149
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	150	J721S2_DEV_NAVSS0_INTR_0	in_intr	150
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	151	J721S2_DEV_NAVSS0_INTR_0	in_intr	151
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	152	J721S2_DEV_NAVSS0_INTR_0	in_intr	152
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	153	J721S2_DEV_NAVSS0_INTR_0	in_intr	153
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	154	J721S2_DEV_NAVSS0_INTR_0	in_intr	154
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	155	J721S2_DEV_NAVSS0_INTR_0	in_intr	155
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	156	J721S2_DEV_NAVSS0_INTR_0	in_intr	156
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	157	J721S2_DEV_NAVSS0_INTR_0	in_intr	157
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	158	J721S2_DEV_NAVSS0_INTR_0	in_intr	158
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	159	J721S2_DEV_NAVSS0_INTR_0	in_intr	159
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	160	J721S2_DEV_NAVSS0_INTR_0	in_intr	160
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	161	J721S2_DEV_NAVSS0_INTR_0	in_intr	161
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	162	J721S2_DEV_NAVSS0_INTR_0	in_intr	162
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	163	J721S2_DEV_NAVSS0_INTR_0	in_intr	163
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	164	J721S2_DEV_NAVSS0_INTR_0	in_intr	164
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	165	J721S2_DEV_NAVSS0_INTR_0	in_intr	165
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	166	J721S2_DEV_NAVSS0_INTR_0	in_intr	166
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	167	J721S2_DEV_NAVSS0_INTR_0	in_intr	167
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	168	J721S2_DEV_NAVSS0_INTR_0	in_intr	168
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	169	J721S2_DEV_NAVSS0_INTR_0	in_intr	169
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	170	J721S2_DEV_NAVSS0_INTR_0	in_intr	170
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	171	J721S2_DEV_NAVSS0_INTR_0	in_intr	171
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	172	J721S2_DEV_NAVSS0_INTR_0	in_intr	172
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	173	J721S2_DEV_NAVSS0_INTR_0	in_intr	173
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	174	J721S2_DEV_NAVSS0_INTR_0	in_intr	174
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	175	J721S2_DEV_NAVSS0_INTR_0	in_intr	175
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	176	J721S2_DEV_NAVSS0_INTR_0	in_intr	176
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	177	J721S2_DEV_NAVSS0_INTR_0	in_intr	177
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	178	J721S2_DEV_NAVSS0_INTR_0	in_intr	178
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	179	J721S2_DEV_NAVSS0_INTR_0	in_intr	179
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	180	J721S2_DEV_NAVSS0_INTR_0	in_intr	180
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	181	J721S2_DEV_NAVSS0_INTR_0	in_intr	181
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	182	J721S2_DEV_NAVSS0_INTR_0	in_intr	182
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	183	J721S2_DEV_NAVSS0_INTR_0	in_intr	183
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	184	J721S2_DEV_NAVSS0_INTR_0	in_intr	184
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	185	J721S2_DEV_NAVSS0_INTR_0	in_intr	185
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	186	J721S2_DEV_NAVSS0_INTR_0	in_intr	186
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	187	J721S2_DEV_NAVSS0_INTR_0	in_intr	187
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	188	J721S2_DEV_NAVSS0_INTR_0	in_intr	188
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	189	J721S2_DEV_NAVSS0_INTR_0	in_intr	189
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	190	J721S2_DEV_NAVSS0_INTR_0	in_intr	190
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	191	J721S2_DEV_NAVSS0_INTR_0	in_intr	191
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	192	J721S2_DEV_NAVSS0_INTR_0	in_intr	192
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	193	J721S2_DEV_NAVSS0_INTR_0	in_intr	193
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	194	J721S2_DEV_NAVSS0_INTR_0	in_intr	194
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	195	J721S2_DEV_NAVSS0_INTR_0	in_intr	195
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	196	J721S2_DEV_NAVSS0_INTR_0	in_intr	196
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	197	J721S2_DEV_NAVSS0_INTR_0	in_intr	197
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	198	J721S2_DEV_NAVSS0_INTR_0	in_intr	198
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	199	J721S2_DEV_NAVSS0_INTR_0	in_intr	199
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	200	J721S2_DEV_NAVSS0_INTR_0	in_intr	200
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	201	J721S2_DEV_NAVSS0_INTR_0	in_intr	201
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	202	J721S2_DEV_NAVSS0_INTR_0	in_intr	202
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	203	J721S2_DEV_NAVSS0_INTR_0	in_intr	203
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	204	J721S2_DEV_NAVSS0_INTR_0	in_intr	204
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	205	J721S2_DEV_NAVSS0_INTR_0	in_intr	205
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	206	J721S2_DEV_NAVSS0_INTR_0	in_intr	206
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	207	J721S2_DEV_NAVSS0_INTR_0	in_intr	207
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	208	J721S2_DEV_NAVSS0_INTR_0	in_intr	208
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	209	J721S2_DEV_NAVSS0_INTR_0	in_intr	209
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	210	J721S2_DEV_NAVSS0_INTR_0	in_intr	210
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	211	J721S2_DEV_NAVSS0_INTR_0	in_intr	211
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	212	J721S2_DEV_NAVSS0_INTR_0	in_intr	212
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	213	J721S2_DEV_NAVSS0_INTR_0	in_intr	213
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	214	J721S2_DEV_NAVSS0_INTR_0	in_intr	214
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	215	J721S2_DEV_NAVSS0_INTR_0	in_intr	215
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	216	J721S2_DEV_NAVSS0_INTR_0	in_intr	216
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	217	J721S2_DEV_NAVSS0_INTR_0	in_intr	217
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	218	J721S2_DEV_NAVSS0_INTR_0	in_intr	218
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	219	J721S2_DEV_NAVSS0_INTR_0	in_intr	219
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	220	J721S2_DEV_NAVSS0_INTR_0	in_intr	220
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	221	J721S2_DEV_NAVSS0_INTR_0	in_intr	221
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	222	J721S2_DEV_NAVSS0_INTR_0	in_intr	222
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	223	J721S2_DEV_NAVSS0_INTR_0	in_intr	223
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	224	J721S2_DEV_NAVSS0_INTR_0	in_intr	224
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	225	J721S2_DEV_NAVSS0_INTR_0	in_intr	225
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	226	J721S2_DEV_NAVSS0_INTR_0	in_intr	226
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	227	J721S2_DEV_NAVSS0_INTR_0	in_intr	227
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	228	J721S2_DEV_NAVSS0_INTR_0	in_intr	228
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	229	J721S2_DEV_NAVSS0_INTR_0	in_intr	229
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	230	J721S2_DEV_NAVSS0_INTR_0	in_intr	230
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	231	J721S2_DEV_NAVSS0_INTR_0	in_intr	231
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	232	J721S2_DEV_NAVSS0_INTR_0	in_intr	232
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	233	J721S2_DEV_NAVSS0_INTR_0	in_intr	233
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	234	J721S2_DEV_NAVSS0_INTR_0	in_intr	234
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	235	J721S2_DEV_NAVSS0_INTR_0	in_intr	235
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	236	J721S2_DEV_NAVSS0_INTR_0	in_intr	236
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	237	J721S2_DEV_NAVSS0_INTR_0	in_intr	237
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	238	J721S2_DEV_NAVSS0_INTR_0	in_intr	238
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	239	J721S2_DEV_NAVSS0_INTR_0	in_intr	239
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	240	J721S2_DEV_NAVSS0_INTR_0	in_intr	240
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	241	J721S2_DEV_NAVSS0_INTR_0	in_intr	241
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	242	J721S2_DEV_NAVSS0_INTR_0	in_intr	242
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	243	J721S2_DEV_NAVSS0_INTR_0	in_intr	243
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	244	J721S2_DEV_NAVSS0_INTR_0	in_intr	244
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	245	J721S2_DEV_NAVSS0_INTR_0	in_intr	245
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	246	J721S2_DEV_NAVSS0_INTR_0	in_intr	246
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	247	J721S2_DEV_NAVSS0_INTR_0	in_intr	247
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	248	J721S2_DEV_NAVSS0_INTR_0	in_intr	248
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	249	J721S2_DEV_NAVSS0_INTR_0	in_intr	249
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	250	J721S2_DEV_NAVSS0_INTR_0	in_intr	250
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	251	J721S2_DEV_NAVSS0_INTR_0	in_intr	251
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	252	J721S2_DEV_NAVSS0_INTR_0	in_intr	252
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	253	J721S2_DEV_NAVSS0_INTR_0	in_intr	253
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	254	J721S2_DEV_NAVSS0_INTR_0	in_intr	254
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	255	J721S2_DEV_NAVSS0_INTR_0	in_intr	255

MCU_NAVSS0_UDMASS_INTA_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name	IA Device ID	IA VINT Index	Destination Name	Destination Interface	Destination Index
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	0	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	0
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	1	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	1
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	2	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	2
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	3	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	3
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	4	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	4
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	5	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	5
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	6	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	6
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	7	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	7
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	8	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	8
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	9	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	9
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	10	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	10
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	11	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	11
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	12	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	12
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	13	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	13
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	14	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	14
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	15	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	15
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	16	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	16
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	17	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	17
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	18	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	18
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	19	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	19
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	20	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	20
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware)	275	21	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	21
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	22	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	22
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	23	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	23
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	24	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	24
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	25	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	25
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	26	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	26
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	27	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	27
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	28	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	28
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	29	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	29
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	30	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	30
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	31	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	31
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	32	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	32
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	33	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	33
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	34	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	34
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	35	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	35
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	36	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	36
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	37	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	37
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	38	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	38
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	39	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	39
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	40	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	40
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	41	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	41
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	42	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	42
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	43	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	43
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	44	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	44
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	45	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	45
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	46	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	46
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	47	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	47
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	48	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	48
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	49	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	49
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	50	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	50
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	51	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	51
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	52	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	52
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	53	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	53
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	54	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	54
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	55	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	55
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	56	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	56
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	57	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	57
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	58	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	58
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	59	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	59
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	60	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	60
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	61	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	61
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	62	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	62
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	63	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	63
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	64	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	64
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	65	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	65
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	66	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	66
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	67	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	67
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	68	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	68
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	69	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	69
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	70	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	70
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	71	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	71
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	72	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	72
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	73	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	73
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	74	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	74
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	75	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	75
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	76	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	76
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	77	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	77
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	78	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	78
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	79	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	79
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	80	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	80
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	81	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	81
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	82	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	82
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	83	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	83
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	84	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	84
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	85	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	85
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	86	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	86
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	87	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	87
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	88	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	88
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	89	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	89
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	90	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	90
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	91	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	91
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	92	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	92
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	93	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	93
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	94	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	94
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	95	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	95
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	96	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	96
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	97	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	97
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	98	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	98
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	99	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	99
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	100	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	100
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	101	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	101
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	102	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	102
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	103	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	103
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	104	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	104
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	105	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	105
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	106	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	106
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	107	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	107
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	108	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	108
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	109	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	109
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	110	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	110
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	111	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	111
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	112	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	112
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	113	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	113
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	114	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	114
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	115	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	115
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	116	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	116
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	117	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	117
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	118	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	118
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	119	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	119
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	120	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	120
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	121	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	121
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	122	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	122
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	123	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	123
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	124	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	124
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	125	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	125
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	126	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	126
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	127	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	127
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	128	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	128
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	129	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	129
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	130	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	130
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	131	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	131
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	132	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	132
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	133	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	133
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	134	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	134
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	135	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	135
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	136	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	136
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	137	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	137
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	138	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	138
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	139	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	139
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	140	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	140
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	141	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	141
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	142	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	142
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	143	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	143
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	144	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	144
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	145	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	145
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	146	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	146
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	147	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	147
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	148	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	148
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	149	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	149
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	150	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	150
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	151	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	151
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	152	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	152
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	153	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	153
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	154	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	154
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	155	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	155
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	156	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	156
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	157	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	157
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	158	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	158
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	159	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	159
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	160	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	160
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	161	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	161
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	162	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	162
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	163	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	163
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	164	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	164
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	165	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	165
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	166	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	166
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	167	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	167
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	168	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	168
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	169	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	169
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	170	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	170
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	171	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	171
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	172	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	172
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	173	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	173
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	174	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	174
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	175	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	175
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	176	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	176
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	177	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	177
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	178	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	178
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	179	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	179
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	180	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	180
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	181	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	181
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	182	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	182
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	183	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	183
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	184	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	184
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	185	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	185
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	186	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	186
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	187	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	187
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	188	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	188
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	189	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	189
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	190	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	190
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	191	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	191
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	192	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	192
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	193	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	193
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	194	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	194
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	195	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	195
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	196	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	196
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	197	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	197
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	198	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	198
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	199	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	199
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	200	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	200
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	201	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	201
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	202	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	202
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	203	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	203
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	204	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	204
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	205	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	205
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	206	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	206
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	207	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	207
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	208	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	208
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	209	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	209
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	210	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	210
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	211	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	211
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	212	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	212
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	213	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	213
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	214	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	214
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	215	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	215
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	216	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	216
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	217	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	217
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	218	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	218
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	219	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	219
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	220	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	220
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	221	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	221
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	222	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	222
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	223	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	223
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	224	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	224
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	225	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	225
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	226	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	226
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	227	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	227
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	228	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	228
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	229	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	229
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	230	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	230
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	231	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	231
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	232	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	232
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	233	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	233
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	234	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	234
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	235	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	235
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	236	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	236
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	237	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	237
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	238	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	238
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	239	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	239
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	240	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	240
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	241	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	241
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	242	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	242
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	243	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	243
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	244	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	244
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	245	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	245
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	246	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	246
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	247	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	247
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	248	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	248
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	249	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	249
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	250	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	250
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	251	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	251
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	252	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	252
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	253	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	253
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	254	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	254
J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0	275	255	J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0	in_intr	255

Global Events

This section describes J721S2 global events. The global events are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Global Event Name	Global Event Range
NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE)	0 to 33
NAVSS0_UDMASS_INTA_0 SEVT	34 to 4607
MCU_NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE)	16384 to 16405
MCU_NAVSS0_UDMASS_INTA_0 SEVT	16406 to 17919
NAVSS0_MODSS_INTA_0 SEVT	20480 to 21503
NAVSS0_MODSS_INTA_1 SEVT	22528 to 23551
NAVSS0_UDMASS_INTA_0 MEVT	32768 to 33279
MCU_NAVSS0_UDMASS_INTA_0 MEVT	34816 to 34943
NAVSS0_UDMASS_INTA_0 GEVT	36864 to 37375
MCU_NAVSS0_UDMASS_INTA_0 GEVT	39936 to 40191
NAVSS0_UDMAP_0 TRIGGER	49152 to 50175
NAVSS0_BCDMA_0 TRIGGER	50176 to 50271
MCU_NAVSS0_UDMAP_0 TRIGGER	56320 to 56575

Event-Based Interrupt Source IDs

Device Name	Device ID	Interrupt Source Name	Interrupt Source Index
J721S2_DEV_NAVSS0_RINGACC_0	259	Ring events	0 to 767
J721S2_DEV_NAVSS0_RINGACC_0	259	Ring events	878 to 1023
J721S2_DEV_MCU_NAVSS0_RINGACC0	272	Ring events	0 to 255
J721S2_DEV_NAVSS0_RINGACC_0	259	Ring monitor events	1024 to 1055
J721S2_DEV_MCU_NAVSS0_RINGACC0	272	Ring monitor events	1024 to 1055
J721S2_DEV_NAVSS0_RINGACC_0	259	Ring global error event	2048
J721S2_DEV_MCU_NAVSS0_RINGACC0	272	Ring global error event	2048
J721S2_DEV_NAVSS0_UDMAP_0	263	UDMA transmit channel OES events	0 to 340
J721S2_DEV_NAVSS0_UDMAP_0	263	UDMA transmit channel EOES events	512 to 852
J721S2_DEV_NAVSS0_UDMAP_0	263	UDMA receive channel OES events	1024 to 1105
J721S2_DEV_NAVSS0_UDMAP_0	263	UDMA receive channel EOES events	1152 to 1233
J721S2_DEV_NAVSS0_UDMAP_0	263	UDMA global configuration invalid flow event	1280
J721S2_DEV_MCU_NAVSS0_UDMAP_0	273	UDMA transmit channel OES events	0 to 47
J721S2_DEV_MCU_NAVSS0_UDMAP_0	273	UDMA transmit channel EOES events	512 to 559
J721S2_DEV_MCU_NAVSS0_UDMAP_0	273	UDMA receive channel OES events	1024 to 1071
J721S2_DEV_MCU_NAVSS0_UDMAP_0	273	UDMA receive channel EOES events	1152 to 1199
J721S2_DEV_MCU_NAVSS0_UDMAP_0	273	UDMA global configuration invalid flow event	1280
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_error events	1536 to 1551
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_data_completion events	2048 to 2063
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_ring_completion events	2560 to 2575
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_error events	3072 to 3103
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_data_completion events	3584 to 3615
J721S2_DEV_NAVSS0_UDMASS_INTA_0	265	NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_ring_completion events	4096 to 4127