AM65X_SR2 Clock Identifiers

Clock for AM6 Device

This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in AM6 SoC.

TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.

Device wise clock ID list for AM6 SoC

This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs

The following table describes functions implemented by clocks

Function	Description
Input clock	Clock input to the SoC subsystem
Output clock	Clock output from the SoC subsystem
Input muxed clock	Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source
Parent input clock option to XYZ	One of the parent clocks that can be used as a source clock to a input muxed clock

Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:

This device has no defined clocks.

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

Clocks for BOARD0 Device

Device: AM6_DEV_BOARD0 (ID = 157)

Note

BOARD0 is a special device that represents the board on which the SoC is mounted.

Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.

Function documented here implies:

Function	Description
Input clock	Clock is supplied from SoC to the board (It is an output of the SoC)
Output clock	Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)

NOTE: Clocks which can be bi-directional are listed as Output clock

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
5	DEV_BOARD0_BUS_MCU_OSPI1CLK_IN	Input clock
7	DEV_BOARD0_BUS_REFCLK1P_IN	Input muxed clock
8	DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN
9	DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN
10	DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN
11	DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN
12	DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN	Input clock
13	DEV_BOARD0_BUS_MCU_OBSCLK_IN	Input clock
14	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
15	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
16	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
17	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
18	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
19	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
20	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
21	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
22	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
23	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
24	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
25	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
26	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
27	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
28	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
29	DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN
36	DEV_BOARD0_BUS_OBSCLK_IN	Input clock
37	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
38	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
39	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
40	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
41	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
42	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
43	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
44	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
45	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
46	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
47	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
48	DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN
54	DEV_BOARD0_BUS_MCU_OSPI0CLK_IN	Input clock
55	DEV_BOARD0_BUS_DSS0PCLK_IN	Input clock
58	DEV_BOARD0_BUS_REFCLK0P_IN	Input muxed clock
59	DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN
60	DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN
61	DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN
62	DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN
68	DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN	Input clock
69	DEV_BOARD0_BUS_MCU_CLKOUT_IN	Input muxed clock
70	DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN
71	DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10	Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN
73	DEV_BOARD0_BUS_SYSCLKOUT_IN	Input clock
74	DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN	Input clock
75	DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT	Output clock
76	DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT	Output clock
77	DEV_BOARD0_BUS_GPMCCLK_OUT	Output clock
78	DEV_BOARD0_BUS_MCASP2AHCLKX_OUT	Output clock
79	DEV_BOARD0_BUS_MCASP2AHCLKR_OUT	Output clock
80	DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT	Output clock
81	DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT	Output clock
82	DEV_BOARD0_BUS_MCASP0ACLKR_OUT	Output clock
83	DEV_BOARD0_BUS_MCASP0ACLKX_OUT	Output clock
84	DEV_BOARD0_BUS_EXT_REFCLK1_OUT	Output clock
85	DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT	Output clock
86	DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT	Output clock
88	DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT	Output clock
89	DEV_BOARD0_BUS_SPI1CLK_OUT	Output clock
90	DEV_BOARD0_BUS_MCASP2ACLKR_OUT	Output clock
91	DEV_BOARD0_BUS_MCASP1ACLKX_OUT	Output clock
92	DEV_BOARD0_BUS_MCASP1ACLKR_OUT	Output clock
93	DEV_BOARD0_BUS_MCASP2ACLKX_OUT	Output clock
94	DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT	Output clock
95	DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT	Output clock
96	DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT	Output clock
97	DEV_BOARD0_BUS_MCU_SPI0CLK_OUT	Output clock
98	DEV_BOARD0_BUS_MCU_SPI1CLK_OUT	Output clock
99	DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT	Output clock
100	DEV_BOARD0_BUS_SPI2CLK_OUT	Output clock
101	DEV_BOARD0_BUS_WKUP_TCK_OUT	Output clock
102	DEV_BOARD0_BUS_SPI3CLK_OUT	Output clock
104	DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT	Output clock
105	DEV_BOARD0_BUS_MCASP0AHCLKR_OUT	Output clock
106	DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT	Output clock
107	DEV_BOARD0_BUS_MCASP0AHCLKX_OUT	Output clock
108	DEV_BOARD0_BUS_CCDC0_PCLK_OUT	Output clock
109	DEV_BOARD0_HFOSC1_CLK_OUT	Output clock
110	DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT	Output clock
111	DEV_BOARD0_BUS_MCASP1AHCLKX_OUT	Output clock
113	DEV_BOARD0_BUS_MCASP1AHCLKR_OUT	Output clock
115	DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT	Output clock
116	DEV_BOARD0_BUS_SPI0CLK_OUT	Output clock
119	DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT	Output clock
120	DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT	Output clock
121	DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT	Output clock
122	DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT	Output clock
123	DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT	Output clock
124	DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT	Output clock

Clocks for CAL0 Device

Device: AM6_DEV_CAL0 (ID = 2)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CAL0_BUS_CLK	Input clock
1	DEV_CAL0_BUS_CP_C_CLK	Input clock

Clocks for CBASS0 Device

Device: AM6_DEV_CBASS0 (ID = 82)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK	Input clock
1	DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK	Input clock

Clocks for CBASS_DEBUG0 Device

Device: AM6_DEV_CBASS_DEBUG0 (ID = 83)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK	Input clock
1	DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK	Input clock

Clocks for CBASS_FW0 Device

Device: AM6_DEV_CBASS_FW0 (ID = 84)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK	Input clock
1	DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK	Input clock

Clocks for CBASS_INFRA0 Device

Device: AM6_DEV_CBASS_INFRA0 (ID = 85)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK	Input muxed clock
1	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
2	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
3	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
4	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
5	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
6	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
7	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
8	DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK	Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK
9	DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK	Input clock
10	DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK	Input clock

Clocks for CCDEBUGSS0 Device

Device: AM6_DEV_CCDEBUGSS0 (ID = 66)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CCDEBUGSS0_BUS_ATB1_CLK	Input clock
1	DEV_CCDEBUGSS0_BUS_ATB0_CLK	Input clock
2	DEV_CCDEBUGSS0_BUS_SYS_CLK	Input clock
3	DEV_CCDEBUGSS0_BUS_DBG_CLK	Input clock
4	DEV_CCDEBUGSS0_BUS_CFG_CLK	Input clock

Clocks for CMPEVENT_INTRTR0 Device

Device: AM6_DEV_CMPEVENT_INTRTR0 (ID = 3)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for COMPUTE_CLUSTER_A53_0 Device

Device: AM6_DEV_COMPUTE_CLUSTER_A53_0 (ID = 202)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK	Input clock

Clocks for COMPUTE_CLUSTER_A53_1 Device

Device: AM6_DEV_COMPUTE_CLUSTER_A53_1 (ID = 203)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK	Input clock

Clocks for COMPUTE_CLUSTER_A53_2 Device

Device: AM6_DEV_COMPUTE_CLUSTER_A53_2 (ID = 204)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK	Input clock

Clocks for COMPUTE_CLUSTER_A53_3 Device

Device: AM6_DEV_COMPUTE_CLUSTER_A53_3 (ID = 205)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK	Input clock

Clocks for COMPUTE_CLUSTER_CPAC0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER_CPAC1 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER_CPAC_PBIST0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER_CPAC_PBIST1 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER_MSMC0 Device

Device: AM6_DEV_COMPUTE_CLUSTER_MSMC0 (ID = 196)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK	Input clock

Clocks for COMPUTE_CLUSTER_PBIST0 Device

Device: AM6_DEV_COMPUTE_CLUSTER_PBIST0 (ID = 197)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK	Input clock
1	DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK	Input clock

Clocks for CPT2_AGGR0 Device

Device: AM6_DEV_CPT2_AGGR0 (ID = 6)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR0_BUS_VCLK_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_CAL0_0 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 (ID = 213)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_DSS_2 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 (ID = 214)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 (ID = 211)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 (ID = 212)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 (ID = 209)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 (ID = 206)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 (ID = 208)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MCU_FSS_S0_2 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 (ID = 215)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MCU_FSS_S1_3 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 (ID = 207)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK	Input clock

Clocks for CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 Device

Device: AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 (ID = 210)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK	Input clock
1	DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK	Input clock

Clocks for CTRL_MMR0 Device

Device: AM6_DEV_CTRL_MMR0 (ID = 99)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CTRL_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for DCC0 Device

Device: AM6_DEV_DCC0 (ID = 9)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC0_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC0_BUS_DCC_CLKSRC4_CLK	Input clock
2	DEV_DCC0_BUS_DCC_CLKSRC3_CLK	Input clock
3	DEV_DCC0_BUS_VBUS_CLK	Input clock
4	DEV_DCC0_BUS_DCC_CLKSRC1_CLK	Input clock
5	DEV_DCC0_BUS_DCC_INPUT01_CLK	Input clock
6	DEV_DCC0_BUS_DCC_CLKSRC5_CLK	Input clock
7	DEV_DCC0_BUS_DCC_INPUT02_CLK	Input clock
8	DEV_DCC0_BUS_DCC_CLKSRC0_CLK	Input clock
9	DEV_DCC0_BUS_DCC_CLKSRC6_CLK	Input clock
10	DEV_DCC0_BUS_DCC_INPUT10_CLK	Input clock
11	DEV_DCC0_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC1 Device

Device: AM6_DEV_DCC1 (ID = 10)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC1_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC1_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC1_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC1_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC1_BUS_VBUS_CLK	Input clock
5	DEV_DCC1_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC1_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC1_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC1_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC1_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC1_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_DCC1_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_DCC1_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC2 Device

Device: AM6_DEV_DCC2 (ID = 11)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC2_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC2_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC2_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC2_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC2_BUS_VBUS_CLK	Input clock
5	DEV_DCC2_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC2_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC2_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC2_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC2_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC2_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_DCC2_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_DCC2_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC3 Device

Device: AM6_DEV_DCC3 (ID = 12)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC3_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC3_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC3_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC3_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC3_BUS_VBUS_CLK	Input clock
5	DEV_DCC3_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC3_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC3_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC3_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC3_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC3_BUS_DCC_INPUT10_CLK	Input clock
11	DEV_DCC3_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC4 Device

Device: AM6_DEV_DCC4 (ID = 13)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC4_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC4_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC4_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC4_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC4_BUS_VBUS_CLK	Input clock
5	DEV_DCC4_BUS_DCC_INPUT01_CLK	Input clock
6	DEV_DCC4_BUS_DCC_CLKSRC5_CLK	Input clock
7	DEV_DCC4_BUS_DCC_INPUT02_CLK	Input clock
8	DEV_DCC4_BUS_DCC_CLKSRC0_CLK	Input clock
9	DEV_DCC4_BUS_DCC_CLKSRC6_CLK	Input clock
10	DEV_DCC4_BUS_DCC_INPUT10_CLK	Input clock
11	DEV_DCC4_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC5 Device

Device: AM6_DEV_DCC5 (ID = 14)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC5_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC5_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC5_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC5_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC5_BUS_VBUS_CLK	Input clock
5	DEV_DCC5_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC5_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC5_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC5_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC5_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC5_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_DCC5_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_DCC5_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC6 Device

Device: AM6_DEV_DCC6 (ID = 15)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC6_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC6_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC6_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC6_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC6_BUS_VBUS_CLK	Input clock
5	DEV_DCC6_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC6_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC6_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC6_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC6_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC6_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_DCC6_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_DCC6_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DCC7 Device

Device: AM6_DEV_DCC7 (ID = 16)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC7_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_DCC7_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_DCC7_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_DCC7_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC7_BUS_VBUS_CLK	Input clock
5	DEV_DCC7_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_DCC7_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_DCC7_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_DCC7_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_DCC7_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_DCC7_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_DCC7_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_DCC7_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for DDRSS0 Device

Device: AM6_DEV_DDRSS0 (ID = 20)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DDRSS0_BUS_DDRSS_VBUS_CLK	Input clock
1	DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK	Input clock
2	DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock
3	DEV_DDRSS0_BUS_DDRSS_TCLK	Input clock
4	DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock
5	DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock
6	DEV_DDRSS0_BUS_DDRSS_CFG_CLK	Input clock
7	DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock
8	DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock
9	DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK	Input clock

Clocks for DEBUGSS0 Device

Device: AM6_DEV_DEBUGSS0 (ID = 68)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DEBUGSS0_BUS_ATB1_CLK	Input clock
1	DEV_DEBUGSS0_BUS_ATB5_CLK	Input clock
2	DEV_DEBUGSS0_BUS_ATB0_CLK	Input clock
3	DEV_DEBUGSS0_BUS_SYS_CLK	Input clock
4	DEV_DEBUGSS0_BUS_ATB4_CLK	Input clock
5	DEV_DEBUGSS0_BUS_CFG_CLK	Input clock
6	DEV_DEBUGSS0_BUS_ATB2_CLK	Input clock
7	DEV_DEBUGSS0_BUS_DBG_CLK	Input clock
8	DEV_DEBUGSS0_BUS_ATB3_CLK	Input clock

Clocks for DEBUGSS_WRAP0 Device

Device: AM6_DEV_DEBUGSS_WRAP0 (ID = 21)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK	Input clock
1	DEV_DEBUGSS_WRAP0_BUS_ATB_CLK	Input clock
2	DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK	Input clock
3	DEV_DEBUGSS_WRAP0_BUS_CORE_CLK	Input clock

Clocks for DEBUGSUSPENDRTR0 Device

Device: AM6_DEV_DEBUGSUSPENDRTR0 (ID = 81)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK	Input clock

Clocks for DFTSS0 Device

Device: AM6_DEV_DFTSS0 (ID = 117)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DFTSS0_BUS_VBUSP_CLK_CLK	Input clock

Clocks for DSS0 Device

Device: AM6_DEV_DSS0 (ID = 67)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0	Input clock
1	DEV_DSS0_BUS_DSS_FUNC_CLK	Input clock
2	DEV_DSS0_BUS_DPI_1_IN_CLK	Input muxed clock
3	DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07	Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK
4	DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT	Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK
5	DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1	Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK
6	DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0	Input clock
7	DEV_DSS0_BUS_DPI_1_OUT_CLK	Output clock

Clocks for DUMMY_IP_LPSC_DEBUG2DMSC_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_DMSC_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_EMIF_DATA_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_MAIN2MCU_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_MCU2MAIN_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_MCU2WKUP_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD Device

This device has no defined clocks.

Clocks for DUMMY_IP_LPSC_WKUP2MCU_VD Device

This device has no defined clocks.

Clocks for ECAP0 Device

Device: AM6_DEV_ECAP0 (ID = 39)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECAP0_BUS_VBUS_CLK	Input clock

Clocks for ECC_AGGR0 Device

Device: AM6_DEV_ECC_AGGR0 (ID = 86)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECC_AGGR0_BUS_AGGR_CLK	Input clock

Clocks for ECC_AGGR1 Device

Device: AM6_DEV_ECC_AGGR1 (ID = 87)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECC_AGGR1_BUS_AGGR_CLK	Input clock

Clocks for ECC_AGGR2 Device

Device: AM6_DEV_ECC_AGGR2 (ID = 88)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECC_AGGR2_BUS_AGGR_CLK	Input clock

Clocks for EFUSE0 Device

Device: AM6_DEV_EFUSE0 (ID = 69)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK	Input clock

Clocks for EHRPWM0 Device

Device: AM6_DEV_EHRPWM0 (ID = 40)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM0_BUS_VBUSP_CLK	Input clock

Clocks for EHRPWM1 Device

Device: AM6_DEV_EHRPWM1 (ID = 41)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM1_BUS_VBUSP_CLK	Input clock

Clocks for EHRPWM2 Device

Device: AM6_DEV_EHRPWM2 (ID = 42)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM2_BUS_VBUSP_CLK	Input clock

Clocks for EHRPWM3 Device

Device: AM6_DEV_EHRPWM3 (ID = 43)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM3_BUS_VBUSP_CLK	Input clock

Clocks for EHRPWM4 Device

Device: AM6_DEV_EHRPWM4 (ID = 44)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM4_BUS_VBUSP_CLK	Input clock

Clocks for EHRPWM5 Device

Device: AM6_DEV_EHRPWM5 (ID = 45)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EHRPWM5_BUS_VBUSP_CLK	Input clock

Clocks for ELM0 Device

Device: AM6_DEV_ELM0 (ID = 46)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ELM0_BUS_VBUSP_CLK	Input clock

Clocks for EQEP0 Device

Device: AM6_DEV_EQEP0 (ID = 49)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP0_BUS_VBUS_CLK	Input clock

Clocks for EQEP1 Device

Device: AM6_DEV_EQEP1 (ID = 50)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP1_BUS_VBUS_CLK	Input clock

Clocks for EQEP2 Device

Device: AM6_DEV_EQEP2 (ID = 51)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP2_BUS_VBUS_CLK	Input clock

Clocks for ESM0 Device

Device: AM6_DEV_ESM0 (ID = 52)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ESM0_BUS_CLK	Input clock

Clocks for FSS_MCU_0 Device

This device has no defined clocks.

Clocks for GIC0 Device

Device: AM6_DEV_GIC0 (ID = 56)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GIC0_BUS_VCLK_CLK	Input clock

Clocks for GPIO0 Device

Device: AM6_DEV_GPIO0 (ID = 57)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO0_BUS_MMR_CLK	Input clock

Clocks for GPIO1 Device

Device: AM6_DEV_GPIO1 (ID = 58)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO1_BUS_MMR_CLK	Input clock

Clocks for GPIOMUX_INTRTR0 Device

Device: AM6_DEV_GPIOMUX_INTRTR0 (ID = 100)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for GPMC0 Device

Device: AM6_DEV_GPMC0 (ID = 60)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPMC0_BUS_FUNC_CLK	Input muxed clock
1	DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK
2	DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3	Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK
3	DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2	Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK
4	DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4	Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK
5	DEV_GPMC0_BUS_PI_GPMC_RET_CLK	Input clock
6	DEV_GPMC0_BUS_VBUSP_CLK	Input clock
7	DEV_GPMC0_BUS_PO_GPMC_DEV_CLK	Output clock

Clocks for GPU0 Device

Device: AM6_DEV_GPU0 (ID = 65)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPU0_BUS_MEM_CLK	Input clock
1	DEV_GPU0_BUS_HYD_CORE_CLK	Input clock
2	DEV_GPU0_BUS_SGX_CORE_CLK	Input clock
3	DEV_GPU0_BUS_SYS_CLK	Input clock

Clocks for GS80PRG_MCU_WRAP_WKUP_0 Device

Device: AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 (ID = 232)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK	Input clock
1	DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK	Input clock

Clocks for GS80PRG_SOC_WRAP_WKUP_0 Device

Device: AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 (ID = 231)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK	Input clock
1	DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK	Input clock

Clocks for GTC0 Device

Device: AM6_DEV_GTC0 (ID = 61)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GTC0_BUS_VBUSP_CLK	Input muxed clock
1	DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
2	DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
3	DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
4	DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
5	DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
6	DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
7	DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK
8	DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK	Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK

Clocks for I2C0 Device

Device: AM6_DEV_I2C0 (ID = 110)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C0_BUS_CLK	Input clock
1	DEV_I2C0_BUS_PISYS_CLK	Input clock

Clocks for I2C1 Device

Device: AM6_DEV_I2C1 (ID = 111)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C1_BUS_CLK	Input clock
1	DEV_I2C1_BUS_PISYS_CLK	Input clock

Clocks for I2C2 Device

Device: AM6_DEV_I2C2 (ID = 112)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C2_BUS_CLK	Input clock
1	DEV_I2C2_BUS_PISYS_CLK	Input clock

Clocks for I2C3 Device

Device: AM6_DEV_I2C3 (ID = 113)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C3_BUS_CLK	Input clock
1	DEV_I2C3_BUS_PISYS_CLK	Input clock

Clocks for ICEMELTER_WKUP_0 Device

This device has no defined clocks.

Clocks for K3_ARM_ATB_FUNNEL_3_32_MCU_0 Device

Device: AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 (ID = 217)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK	Input clock

Clocks for K3_LED_MAIN_0 Device

This device has no defined clocks.

Clocks for MAIN2MCU_LVL_INTRTR0 Device

Device: AM6_DEV_MAIN2MCU_LVL_INTRTR0 (ID = 97)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for MAIN2MCU_PLS_INTRTR0 Device

Device: AM6_DEV_MAIN2MCU_PLS_INTRTR0 (ID = 98)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for MCASP0 Device

Device: AM6_DEV_MCASP0 (ID = 104)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP0_BUS_AUX_CLK	Input muxed clock
1	DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
2	DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
3	DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
4	DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
5	DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
6	DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
7	DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
8	DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_MCASP0_BUS_AUX_CLK
9	DEV_MCASP0_BUS_VBUSP_CLK	Input clock

Clocks for MCASP1 Device

Device: AM6_DEV_MCASP1 (ID = 105)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP1_BUS_AUX_CLK	Input muxed clock
1	DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
2	DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
3	DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
4	DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
5	DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
6	DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
7	DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
8	DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_MCASP1_BUS_AUX_CLK
9	DEV_MCASP1_BUS_VBUSP_CLK	Input clock

Clocks for MCASP2 Device

Device: AM6_DEV_MCASP2 (ID = 106)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP2_BUS_AUX_CLK	Input muxed clock
1	DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
2	DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
3	DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
4	DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
5	DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
6	DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
7	DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
8	DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_MCASP2_BUS_AUX_CLK
9	DEV_MCASP2_BUS_VBUSP_CLK	Input clock

Clocks for MCSPI0 Device

Device: AM6_DEV_MCSPI0 (ID = 137)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI0_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCSPI0_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCSPI0_BUS_VBUSP_CLK	Input clock
3	DEV_MCSPI0_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCSPI1 Device

Device: AM6_DEV_MCSPI1 (ID = 138)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI1_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCSPI1_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCSPI1_BUS_VBUSP_CLK	Input clock
3	DEV_MCSPI1_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCSPI2 Device

Device: AM6_DEV_MCSPI2 (ID = 139)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI2_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCSPI2_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCSPI2_BUS_VBUSP_CLK	Input clock
3	DEV_MCSPI2_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCSPI3 Device

Device: AM6_DEV_MCSPI3 (ID = 140)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI3_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCSPI3_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCSPI3_BUS_VBUSP_CLK	Input clock
3	DEV_MCSPI3_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCSPI4 Device

Device: AM6_DEV_MCSPI4 (ID = 141)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI4_BUS_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI4_BUS_VBUSP_CLK	Input clock
2	DEV_MCSPI4_BUS_IO_CLKSPII_CLK	Input clock
3	DEV_MCSPI4_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCU_ADC0 Device

Device: AM6_DEV_MCU_ADC0 (ID = 0)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ADC0_BUS_VBUS_CLK	Input clock
1	DEV_MCU_ADC0_BUS_SYS_CLK	Input clock
2	DEV_MCU_ADC0_BUS_ADC_CLK	Input muxed clock
3	DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK
4	DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK
5	DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK
6	DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK

Clocks for MCU_ADC1 Device

Device: AM6_DEV_MCU_ADC1 (ID = 1)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ADC1_BUS_VBUS_CLK	Input clock
1	DEV_MCU_ADC1_BUS_SYS_CLK	Input clock
2	DEV_MCU_ADC1_BUS_ADC_CLK	Input muxed clock
3	DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK
4	DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK
5	DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK
6	DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK

Clocks for MCU_ARMSS0 Device

This device has no defined clocks.

Clocks for MCU_ARMSS0_CPU0 Device

Device: AM6_DEV_MCU_ARMSS0_CPU0 (ID = 159)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK	Input clock
1	DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE	Input muxed clock
2	DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE
3	DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK	Input muxed clock
4	DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK
5	DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK

Clocks for MCU_ARMSS0_CPU1 Device

Device: AM6_DEV_MCU_ARMSS0_CPU1 (ID = 245)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK	Input clock
1	DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE	Input muxed clock
2	DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE
3	DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK	Input muxed clock
4	DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK
5	DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK

Clocks for MCU_CBASS0 Device

Device: AM6_DEV_MCU_CBASS0 (ID = 89)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK	Input clock
1	DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK	Input clock
2	DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK	Input clock

Clocks for MCU_CBASS_DEBUG0 Device

Device: AM6_DEV_MCU_CBASS_DEBUG0 (ID = 90)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK	Input clock

Clocks for MCU_CBASS_FW0 Device

Device: AM6_DEV_MCU_CBASS_FW0 (ID = 91)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK	Input clock
1	DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK	Input clock

Clocks for MCU_CPSW0 Device

Device: AM6_DEV_MCU_CPSW0 (ID = 5)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CPSW0_BUS_GMII1_MR_CLK	Input clock
1	DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK	Input clock
2	DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK	Input clock
3	DEV_MCU_CPSW0_BUS_GMII1_MT_CLK	Input clock
4	DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK	Input clock
5	DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK	Input clock
6	DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK	Input muxed clock
7	DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK
8	DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT	Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK
9	DEV_MCU_CPSW0_BUS_GMII_RFT_CLK	Input clock
10	DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK	Input clock

Clocks for MCU_CPT2_AGGR0 Device

Device: AM6_DEV_MCU_CPT2_AGGR0 (ID = 7)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK	Input clock

Clocks for MCU_CTRL_MMR0 Device

Device: AM6_DEV_MCU_CTRL_MMR0 (ID = 107)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for MCU_DCC0 Device

Device: AM6_DEV_MCU_DCC0 (ID = 17)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC0_BUS_VBUS_CLK	Input clock
5	DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for MCU_DCC1 Device

Device: AM6_DEV_MCU_DCC1 (ID = 18)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC1_BUS_VBUS_CLK	Input clock
5	DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for MCU_DCC2 Device

Device: AM6_DEV_MCU_DCC2 (ID = 19)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK	Input clock
1	DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK	Input clock
2	DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK	Input clock
3	DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC2_BUS_VBUS_CLK	Input clock
5	DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK	Input clock
6	DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK	Input clock
7	DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK	Input clock
8	DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK	Input clock
9	DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK	Input clock
10	DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK	Input clock
11	DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK	Input clock

Clocks for MCU_DEBUGSS0 Device

Device: AM6_DEV_MCU_DEBUGSS0 (ID = 71)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DEBUGSS0_BUS_ATB1_CLK	Input clock
1	DEV_MCU_DEBUGSS0_BUS_ATB0_CLK	Input clock
2	DEV_MCU_DEBUGSS0_BUS_SYS_CLK	Input clock
3	DEV_MCU_DEBUGSS0_BUS_CFG_CLK	Input clock
4	DEV_MCU_DEBUGSS0_BUS_ATB2_CLK	Input clock
5	DEV_MCU_DEBUGSS0_BUS_DBG_CLK	Input clock
6	DEV_MCU_DEBUGSS0_BUS_ATB3_CLK	Input clock

Clocks for MCU_ECC_AGGR0 Device

Device: AM6_DEV_MCU_ECC_AGGR0 (ID = 92)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK	Input clock

Clocks for MCU_ECC_AGGR1 Device

Device: AM6_DEV_MCU_ECC_AGGR1 (ID = 93)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK	Input clock

Clocks for MCU_EFUSE0 Device

Device: AM6_DEV_MCU_EFUSE0 (ID = 72)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK	Input clock

Clocks for MCU_ESM0 Device

Device: AM6_DEV_MCU_ESM0 (ID = 53)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ESM0_BUS_CLK	Input clock

Clocks for MCU_FSS0_FSAS_0 Device

This device has no defined clocks.

Clocks for MCU_FSS0_HYPERBUS0 Device

Device: AM6_DEV_MCU_FSS0_HYPERBUS0 (ID = 247)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK	Input clock
1	DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK	Input clock
2	DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK	Input clock
3	DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK	Input clock

Clocks for MCU_FSS0_OSPI_0 Device

Device: AM6_DEV_MCU_FSS0_OSPI_0 (ID = 248)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK	Input muxed clock
1	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK
2	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK
3	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK	Input muxed clock
4	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT	Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK
5	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK
6	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK	Input clock
7	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK	Input clock
8	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK	Input clock
9	DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK	Output clock

Clocks for MCU_FSS0_OSPI_1 Device

Device: AM6_DEV_MCU_FSS0_OSPI_1 (ID = 249)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK	Input clock
1	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK	Input muxed clock
2	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT	Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK
3	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK
4	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK	Input clock
5	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK	Input clock
6	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK	Input muxed clock
7	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK
8	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK
9	DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK	Output clock

Clocks for MCU_I2C0 Device

Device: AM6_DEV_MCU_I2C0 (ID = 114)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_I2C0_BUS_CLK	Input clock
1	DEV_MCU_I2C0_BUS_PISYS_CLK	Input clock

Clocks for MCU_MCAN0 Device

Device: AM6_DEV_MCU_MCAN0 (ID = 102)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK	Input muxed clock
1	DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK
2	DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2	Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK
3	DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2	Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK
4	DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK
5	DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK	Input clock

Clocks for MCU_MCAN1 Device

Device: AM6_DEV_MCU_MCAN1 (ID = 103)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK	Input muxed clock
1	DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK
2	DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2	Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK
3	DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2	Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK
4	DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK
5	DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK	Input clock

Clocks for MCU_MCSPI0 Device

Device: AM6_DEV_MCU_MCSPI0 (ID = 142)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCU_MCSPI0_BUS_VBUSP_CLK	Input clock
3	DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCU_MCSPI1 Device

Device: AM6_DEV_MCU_MCSPI1 (ID = 143)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK	Input clock
1	DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK	Input clock
2	DEV_MCU_MCSPI1_BUS_VBUSP_CLK	Input clock
3	DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCU_MCSPI2 Device

Device: AM6_DEV_MCU_MCSPI2 (ID = 144)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK	Input clock
1	DEV_MCU_MCSPI2_BUS_VBUSP_CLK	Input clock
2	DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK	Input clock
3	DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK	Output clock

Clocks for MCU_MSRAM0 Device

Device: AM6_DEV_MCU_MSRAM0 (ID = 116)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MSRAM0_BUS_CCLK_CLK	Input clock
1	DEV_MCU_MSRAM0_BUS_VCLK_CLK	Input clock

Clocks for MCU_NAVSS0 Device

Device: AM6_DEV_MCU_NAVSS0 (ID = 119)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_MCU_NAVSS0_BUS_CPSW0CLK	Input clock
2	DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK	Input clock
3	DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK	Input clock

Clocks for MCU_NAVSS0_INTR_AGGR_0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_INTR_ROUTER_0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_MCRC0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_PROXY0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_RINGACC0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_UDMAP0 Device

This device has no defined clocks.

Clocks for MCU_PBIST0 Device

Device: AM6_DEV_MCU_PBIST0 (ID = 75)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PBIST0_BUS_CLK1_CLK	Input clock
1	DEV_MCU_PBIST0_BUS_CLK4_CLK	Input clock
2	DEV_MCU_PBIST0_BUS_CLK2_CLK	Input clock

Clocks for MCU_PDMA0 Device

Device: AM6_DEV_MCU_PDMA0 (ID = 125)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PDMA0_BUS_VCLK	Input clock

Clocks for MCU_PDMA1 Device

Device: AM6_DEV_MCU_PDMA1 (ID = 126)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PDMA1_BUS_VCLK	Input clock

Clocks for MCU_PLL_MMR0 Device

Device: AM6_DEV_MCU_PLL_MMR0 (ID = 108)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for MCU_PSRAM0 Device

Device: AM6_DEV_MCU_PSRAM0 (ID = 127)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PSRAM0_BUS_CLK_CLK	Input clock

Clocks for MCU_ROM0 Device

Device: AM6_DEV_MCU_ROM0 (ID = 78)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ROM0_BUS_CLK_CLK	Input clock

Clocks for MCU_RTI0 Device

Device: AM6_DEV_MCU_RTI0 (ID = 134)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_RTI0_BUS_RTI_CLK	Input muxed clock
1	DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK
2	DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK
3	DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK
4	DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK
5	DEV_MCU_RTI0_BUS_VBUSP_CLK	Input clock

Clocks for MCU_RTI1 Device

Device: AM6_DEV_MCU_RTI1 (ID = 135)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_RTI1_BUS_RTI_CLK	Input muxed clock
1	DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK
2	DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK
3	DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK
4	DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK
5	DEV_MCU_RTI1_BUS_VBUSP_CLK	Input clock

Clocks for MCU_SEC_MMR0 Device

Device: AM6_DEV_MCU_SEC_MMR0 (ID = 109)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for MCU_TIMER0 Device

Device: AM6_DEV_MCU_TIMER0 (ID = 35)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
2	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
3	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
4	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
5	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
6	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
8	DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK
9	DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK	Input clock

Clocks for MCU_TIMER1 Device

Device: AM6_DEV_MCU_TIMER1 (ID = 36)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
2	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
3	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
4	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
5	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
6	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
8	DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK
9	DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK	Input clock

Clocks for MCU_TIMER2 Device

Device: AM6_DEV_MCU_TIMER2 (ID = 37)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
2	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
3	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
4	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
5	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
6	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
8	DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK
9	DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK	Input clock

Clocks for MCU_TIMER3 Device

Device: AM6_DEV_MCU_TIMER3 (ID = 38)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
2	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
3	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
4	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
5	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
6	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
8	DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK
9	DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK	Input clock

Clocks for MCU_UART0 Device

Device: AM6_DEV_MCU_UART0 (ID = 149)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_UART0_BUS_FCLK_CLK	Input muxed clock
1	DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK
2	DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK
3	DEV_MCU_UART0_BUS_VBUSP_CLK	Input clock

Clocks for MMCSD0 Device

Device: AM6_DEV_MMCSD0 (ID = 47)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK	Input clock
1	DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK	Input clock

Clocks for MMCSD1 Device

Device: AM6_DEV_MMCSD1 (ID = 48)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK	Input clock
1	DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK	Input clock

Clocks for MX_EFUSE_MAIN_CHAIN_MAIN_0 Device

This device has no defined clocks.

Clocks for MX_EFUSE_MCU_CHAIN_MCU_0 Device

This device has no defined clocks.

Clocks for MX_WAKEUP_RESET_SYNC_WKUP_0 Device

This device has no defined clocks.

Clocks for NAVSS0 Device

Device: AM6_DEV_NAVSS0 (ID = 118)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_NAVSS0_BUS_ICSS_G2CLK	Input clock
2	DEV_NAVSS0_BUS_ICSS_G0CLK	Input clock
3	DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Input clock
4	DEV_NAVSS0_BUS_MSMC0CLK	Input clock
5	DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Input clock
6	DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Input clock
8	DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Input clock
9	DEV_NAVSS0_BUS_PDMA_MAIN1CLK	Input clock
10	DEV_NAVSS0_BUS_NBSS_VCLK	Input clock
11	DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Input clock
12	DEV_NAVSS0_BUS_NBSS_VD2CLK	Input clock
13	DEV_NAVSS0_BUS_ICSS_G1CLK	Input clock
14	DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT	Input clock
15	DEV_NAVSS0_BUS_CPTS0_GENF4_0	Output clock
16	DEV_NAVSS0_BUS_CPTS0_GENF5_0	Output clock
17	DEV_NAVSS0_BUS_CPTS0_GENF2_0	Output clock
18	DEV_NAVSS0_BUS_CPTS0_GENF3_0	Output clock

Clocks for NAVSS0_CPTS0 Device

This device has no defined clocks.

Clocks for NAVSS0_INTR_ROUTER_0 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER0 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER1 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER10 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER11 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER2 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER3 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER4 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER5 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER6 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER7 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER8 Device

This device has no defined clocks.

Clocks for NAVSS0_MAILBOX0_CLUSTER9 Device

This device has no defined clocks.

Clocks for NAVSS0_MCRC0 Device

This device has no defined clocks.

Clocks for NAVSS0_MODSS_INTA0 Device

This device has no defined clocks.

Clocks for NAVSS0_MODSS_INTA1 Device

This device has no defined clocks.

Clocks for NAVSS0_PROXY0 Device

This device has no defined clocks.

Clocks for NAVSS0_PVU0 Device

This device has no defined clocks.

Clocks for NAVSS0_PVU1 Device

This device has no defined clocks.

Clocks for NAVSS0_RINGACC0 Device

This device has no defined clocks.

Clocks for NAVSS0_TIMER_MGR0 Device

This device has no defined clocks.

Clocks for NAVSS0_TIMER_MGR1 Device

This device has no defined clocks.

Clocks for NAVSS0_UDMAP0 Device

This device has no defined clocks.

Clocks for NAVSS0_UDMASS_INTA0 Device

This device has no defined clocks.

Clocks for OLDI_TX_CORE_MAIN_0 Device

Device: AM6_DEV_OLDI_TX_CORE_MAIN_0 (ID = 216)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK	Input clock
1	DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0	Input clock
2	DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0	Input clock

Clocks for PBIST0 Device

Device: AM6_DEV_PBIST0 (ID = 73)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PBIST0_BUS_CLK1_CLK	Input clock
1	DEV_PBIST0_BUS_CLK4_CLK	Input clock
2	DEV_PBIST0_BUS_CLK2_CLK	Input clock

Clocks for PBIST1 Device

Device: AM6_DEV_PBIST1 (ID = 74)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PBIST1_BUS_CLK1_CLK	Input clock
1	DEV_PBIST1_BUS_CLK4_CLK	Input clock
2	DEV_PBIST1_BUS_CLK2_CLK	Input clock

Clocks for PCIE0 Device

Device: AM6_DEV_PCIE0 (ID = 120)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT	Input clock
1	DEV_PCIE0_BUS_PCIE_CBA_CLK	Input clock
2	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Input clock
3	DEV_PCIE0_BUS_PCIE_TXI0_CLK	Input clock
4	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Input clock
5	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Input clock
6	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Input clock
7	DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Input clock
8	DEV_PCIE0_BUS_PCIE_TXR1_CLK	Output clock
9	DEV_PCIE0_BUS_PCIE_TXR0_CLK	Output clock

Clocks for PCIE1 Device

Device: AM6_DEV_PCIE1 (ID = 121)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT	Input clock
1	DEV_PCIE1_BUS_PCIE_CBA_CLK	Input clock
2	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Input clock
3	DEV_PCIE1_BUS_PCIE_TXI0_CLK	Input clock
4	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Input clock
5	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Input clock
6	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Input clock
7	DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Input clock
8	DEV_PCIE1_BUS_PCIE_TXR0_CLK	Output clock

Clocks for PDMA0 Device

Device: AM6_DEV_PDMA0 (ID = 123)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PDMA0_BUS_VCLK	Input clock

Clocks for PDMA1 Device

Device: AM6_DEV_PDMA1 (ID = 124)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PDMA1_BUS_VCLK	Input clock

Clocks for PDMA_DEBUG0 Device

Device: AM6_DEV_PDMA_DEBUG0 (ID = 122)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PDMA_DEBUG0_BUS_VCLK	Input clock

Clocks for PLLCTRL0 Device

Device: AM6_DEV_PLLCTRL0 (ID = 76)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK	Input clock
1	DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK	Input clock
2	DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK	Input muxed clock
3	DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK
4	DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK

Clocks for PLL_MMR0 Device

Device: AM6_DEV_PLL_MMR0 (ID = 101)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PLL_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for PRU_ICSSG0 Device

Device: AM6_DEV_PRU_ICSSG0 (ID = 62)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK	Input clock
1	DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK	Input clock
2	DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK	Input clock
3	DEV_PRU_ICSSG0_BUS_VCLK_CLK	Input clock
4	DEV_PRU_ICSSG0_BUS_UCLK_CLK	Input clock
5	DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK	Input clock
6	DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK	Input clock
8	DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK	Input clock
9	DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK	Input clock
10	DEV_PRU_ICSSG0_BUS_IEP_CLK	Input muxed clock
11	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
12	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
13	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
14	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
15	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
16	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
17	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
18	DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK
19	DEV_PRU_ICSSG0_BUS_CORE_CLK	Input muxed clock
20	DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK
21	DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK

Clocks for PRU_ICSSG1 Device

Device: AM6_DEV_PRU_ICSSG1 (ID = 63)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK	Input clock
1	DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK	Input clock
2	DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK	Input clock
3	DEV_PRU_ICSSG1_BUS_VCLK_CLK	Input clock
4	DEV_PRU_ICSSG1_BUS_UCLK_CLK	Input clock
5	DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK	Input clock
6	DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK	Input clock
8	DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK	Input clock
9	DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK	Input clock
10	DEV_PRU_ICSSG1_BUS_IEP_CLK	Input muxed clock
11	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
12	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
13	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
14	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
15	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
16	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
17	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
18	DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK
19	DEV_PRU_ICSSG1_BUS_CORE_CLK	Input muxed clock
20	DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK
21	DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK

Clocks for PRU_ICSSG2 Device

Device: AM6_DEV_PRU_ICSSG2 (ID = 64)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK	Input clock
1	DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK	Input clock
2	DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK	Input clock
3	DEV_PRU_ICSSG2_BUS_VCLK_CLK	Input clock
4	DEV_PRU_ICSSG2_BUS_UCLK_CLK	Input clock
5	DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK	Input clock
6	DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK	Input clock
8	DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK	Input clock
9	DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK	Input clock
10	DEV_PRU_ICSSG2_BUS_IEP_CLK	Input muxed clock
11	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
12	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
13	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
14	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
15	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
16	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
17	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
18	DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK
19	DEV_PRU_ICSSG2_BUS_CORE_CLK	Input muxed clock
20	DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK
21	DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK
25	DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK	Output clock
26	DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK	Output clock

Clocks for PSC0 Device

Device: AM6_DEV_PSC0 (ID = 70)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PSC0_BUS_CLK	Input clock
1	DEV_PSC0_BUS_SLOW_CLK	Input clock

Clocks for PSRAMECC0 Device

Device: AM6_DEV_PSRAMECC0 (ID = 128)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PSRAMECC0_BUS_CLK_CLK	Input clock

Clocks for RTI0 Device

Device: AM6_DEV_RTI0 (ID = 130)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI0_BUS_RTI_CLK	Input muxed clock
1	DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
2	DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
3	DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
4	DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
5	DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
6	DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
7	DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
8	DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI0_BUS_RTI_CLK
9	DEV_RTI0_BUS_VBUSP_CLK	Input clock

Clocks for RTI1 Device

Device: AM6_DEV_RTI1 (ID = 131)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI1_BUS_RTI_CLK	Input muxed clock
1	DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
2	DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
3	DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
4	DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
5	DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
6	DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
7	DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
8	DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI1_BUS_RTI_CLK
9	DEV_RTI1_BUS_VBUSP_CLK	Input clock

Clocks for RTI2 Device

Device: AM6_DEV_RTI2 (ID = 132)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI2_BUS_RTI_CLK	Input muxed clock
1	DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
2	DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
3	DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
4	DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
5	DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
6	DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
7	DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
8	DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI2_BUS_RTI_CLK
9	DEV_RTI2_BUS_VBUSP_CLK	Input clock

Clocks for RTI3 Device

Device: AM6_DEV_RTI3 (ID = 133)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI3_BUS_RTI_CLK	Input muxed clock
1	DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
2	DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
3	DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
4	DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
5	DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
6	DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
7	DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
8	DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI3_BUS_RTI_CLK
9	DEV_RTI3_BUS_VBUSP_CLK	Input clock

Clocks for SA2_UL0 Device

Device: AM6_DEV_SA2_UL0 (ID = 136)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_SA2_UL0_BUS_PKA_IN_CLK	Input clock
1	DEV_SA2_UL0_BUS_X1_CLK	Input clock
2	DEV_SA2_UL0_BUS_X2_CLK	Input clock

Clocks for SERDES0 Device

Device: AM6_DEV_SERDES0 (ID = 153)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_SERDES0_BUS_IP3_LN0_TXRCLK	Input clock
2	DEV_SERDES0_BUS_CLK	Input clock
3	DEV_SERDES0_BUS_IP2_LN0_TXRCLK	Input clock
4	DEV_SERDES0_BUS_LI_REFCLK	Input muxed clock
5	DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK
6	DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK
7	DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK
8	DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK
10	DEV_SERDES0_BUS_LN0_TXCLK	Output clock
11	DEV_SERDES0_BUS_LN0_RXCLK	Output clock

Clocks for SERDES1 Device

Device: AM6_DEV_SERDES1 (ID = 154)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_SERDES1_BUS_IP3_LN0_TXRCLK	Input clock
2	DEV_SERDES1_BUS_CLK	Input clock
3	DEV_SERDES1_BUS_IP1_LN0_TXRCLK	Input clock
4	DEV_SERDES1_BUS_IP2_LN0_TXRCLK	Input clock
5	DEV_SERDES1_BUS_RI_REFCLK	Input muxed clock
6	DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK
7	DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK
8	DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK	Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK
9	DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK	Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK
11	DEV_SERDES1_BUS_LN0_TXCLK	Output clock
12	DEV_SERDES1_BUS_LN0_RXCLK	Output clock

Clocks for STM0 Device

Device: AM6_DEV_STM0 (ID = 8)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_STM0_BUS_CORE_CLK	Input clock
1	DEV_STM0_BUS_ATB_CLK	Input clock
2	DEV_STM0_BUS_VBUSP_CLK	Input clock

Clocks for TIMER0 Device

Device: AM6_DEV_TIMER0 (ID = 23)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER0_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
2	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
3	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
4	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
5	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
6	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
7	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
8	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
9	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
10	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
11	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
12	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
13	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
14	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
15	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
16	DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK
17	DEV_TIMER0_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER1 Device

Device: AM6_DEV_TIMER1 (ID = 24)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER1_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
2	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
3	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
4	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
5	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
6	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
7	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
8	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
9	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
10	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
11	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
12	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
13	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
14	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
15	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
16	DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK
17	DEV_TIMER1_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER10 Device

Device: AM6_DEV_TIMER10 (ID = 25)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER10_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
2	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
3	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
4	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
5	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
6	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
7	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
8	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
9	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
10	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
11	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
12	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
13	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
14	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
15	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
16	DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK
17	DEV_TIMER10_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER11 Device

Device: AM6_DEV_TIMER11 (ID = 26)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER11_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
2	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
3	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
4	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
5	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
6	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
7	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
8	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
9	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
10	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
11	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
12	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
13	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
14	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
15	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
16	DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK
17	DEV_TIMER11_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER2 Device

Device: AM6_DEV_TIMER2 (ID = 27)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER2_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
2	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
3	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
4	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
5	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
6	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
7	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
8	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
9	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
10	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
11	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
12	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
13	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
14	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
15	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
16	DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK
17	DEV_TIMER2_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER3 Device

Device: AM6_DEV_TIMER3 (ID = 28)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER3_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
2	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
3	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
4	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
5	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
6	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
7	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
8	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
9	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
10	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
11	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
12	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
13	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
14	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
15	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
16	DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK
17	DEV_TIMER3_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER4 Device

Device: AM6_DEV_TIMER4 (ID = 29)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER4_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
2	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
3	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
4	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
5	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
6	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
7	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
8	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
9	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
10	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
11	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
12	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
13	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
14	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
15	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
16	DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK
17	DEV_TIMER4_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER5 Device

Device: AM6_DEV_TIMER5 (ID = 30)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER5_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
2	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
3	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
4	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
5	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
6	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
7	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
8	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
9	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
10	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
11	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
12	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
13	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
14	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
15	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
16	DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK
17	DEV_TIMER5_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER6 Device

Device: AM6_DEV_TIMER6 (ID = 31)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER6_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
2	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
3	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
4	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
5	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
6	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
7	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
8	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
9	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
10	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
11	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
12	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
13	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
14	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
15	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
16	DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK
17	DEV_TIMER6_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER7 Device

Device: AM6_DEV_TIMER7 (ID = 32)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER7_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
2	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
3	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
4	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
5	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
6	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
7	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
8	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
9	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
10	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
11	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
12	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
13	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
14	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
15	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
16	DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK
17	DEV_TIMER7_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER8 Device

Device: AM6_DEV_TIMER8 (ID = 33)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER8_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
2	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
3	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
4	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
5	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
6	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
7	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
8	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
9	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
10	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
11	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
12	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
13	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
14	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
15	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
16	DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK
17	DEV_TIMER8_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMER9 Device

Device: AM6_DEV_TIMER9 (ID = 34)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER9_BUS_TIMER_TCLK_CLK	Input muxed clock
1	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
2	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
3	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
4	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
5	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
6	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
7	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
8	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
9	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
10	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
11	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
12	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
13	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
14	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
15	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
16	DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0	Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK
17	DEV_TIMER9_BUS_TIMER_HCLK_CLK	Input clock

Clocks for TIMESYNC_INTRTR0 Device

Device: AM6_DEV_TIMESYNC_INTRTR0 (ID = 145)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for UART0 Device

Device: AM6_DEV_UART0 (ID = 146)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART0_BUS_FCLK_CLK	Input clock
1	DEV_UART0_BUS_VBUSP_CLK	Input clock

Clocks for UART1 Device

Device: AM6_DEV_UART1 (ID = 147)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART1_BUS_FCLK_CLK	Input clock
1	DEV_UART1_BUS_VBUSP_CLK	Input clock

Clocks for UART2 Device

Device: AM6_DEV_UART2 (ID = 148)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART2_BUS_FCLK_CLK	Input clock
1	DEV_UART2_BUS_VBUSP_CLK	Input clock

Clocks for USB3SS0 Device

Device: AM6_DEV_USB3SS0 (ID = 151)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_USB3SS0_BUS_SUSP_CLK	Input clock
1	DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK	Input clock
2	DEV_USB3SS0_BUS_REF_CLK	Input muxed clock
3	DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0	Parent input clock option to DEV_USB3SS0_BUS_REF_CLK
4	DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48	Parent input clock option to DEV_USB3SS0_BUS_REF_CLK
5	DEV_USB3SS0_BUS_HSIC_CLK_CLK	Input clock
6	DEV_USB3SS0_BUS_BUS_CLK	Input clock
7	DEV_USB3SS0_BUS_PIPE3_TXB_CLK	Input muxed clock
8	DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK	Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK
9	DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK
10	DEV_USB3SS0_BUS_UTMI_CLK_CLK	Input clock

Clocks for USB3SS1 Device

Device: AM6_DEV_USB3SS1 (ID = 152)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_USB3SS1_BUS_SUSP_CLK	Input clock
1	DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK	Input clock
2	DEV_USB3SS1_BUS_REF_CLK	Input muxed clock
3	DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0	Parent input clock option to DEV_USB3SS1_BUS_REF_CLK
4	DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48	Parent input clock option to DEV_USB3SS1_BUS_REF_CLK
5	DEV_USB3SS1_BUS_HSIC_CLK_CLK	Input clock
6	DEV_USB3SS1_BUS_BUS_CLK	Input clock
7	DEV_USB3SS1_BUS_PIPE3_TXB_CLK	Input clock
8	DEV_USB3SS1_BUS_UTMI_CLK_CLK	Input clock

Clocks for VDC_DATA_VBUSM_32B_REF_MCU2WKUP Device

This device has no defined clocks.

Clocks for VDC_DATA_VBUSM_32B_REF_WKUP2MCU Device

This device has no defined clocks.

Clocks for VDC_DATA_VBUSM_64B_REF_MAIN2MCU Device

This device has no defined clocks.

Clocks for VDC_DATA_VBUSM_64B_REF_MCU2MAIN Device

This device has no defined clocks.

Clocks for VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC Device

This device has no defined clocks.

Clocks for VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA Device

This device has no defined clocks.

Clocks for VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA Device

This device has no defined clocks.

Clocks for VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU Device

This device has no defined clocks.

Clocks for VDC_NAV_PSIL_128B_REF_MAIN2MCU Device

This device has no defined clocks.

Clocks for VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN Device

This device has no defined clocks.

Clocks for VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU Device

This device has no defined clocks.

Clocks for WKUP_CBASS0 Device

Device: AM6_DEV_WKUP_CBASS0 (ID = 94)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK	Input clock
1	DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK	Input clock

Clocks for WKUP_CBASS_FW0 Device

Device: AM6_DEV_WKUP_CBASS_FW0 (ID = 96)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK	Input clock

Clocks for WKUP_CTRL_MMR0 Device

Device: AM6_DEV_WKUP_CTRL_MMR0 (ID = 155)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK	Input clock

Clocks for WKUP_DMSC0 Device

This device has no defined clocks.

Clocks for WKUP_DMSC0_CORTEX_M3_0 Device

This device has no defined clocks.

Clocks for WKUP_ECC_AGGR0 Device

Device: AM6_DEV_WKUP_ECC_AGGR0 (ID = 95)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK	Input clock

Clocks for WKUP_ESM0 Device

Device: AM6_DEV_WKUP_ESM0 (ID = 54)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_ESM0_BUS_CLK	Input clock

Clocks for WKUP_GPIO0 Device

Device: AM6_DEV_WKUP_GPIO0 (ID = 59)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_GPIO0_BUS_MMR_CLK	Input muxed clock
1	DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4	Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK
2	DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0	Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK
3	DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK
4	DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK

Clocks for WKUP_GPIOMUX_INTRTR0 Device

Device: AM6_DEV_WKUP_GPIOMUX_INTRTR0 (ID = 156)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK	Input clock

Clocks for WKUP_I2C0 Device

Device: AM6_DEV_WKUP_I2C0 (ID = 115)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_I2C0_BUS_CLK	Input clock
1	DEV_WKUP_I2C0_BUS_PISYS_CLK	Input muxed clock
2	DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK	Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK
3	DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK

Clocks for WKUP_PLLCTRL0 Device

Device: AM6_DEV_WKUP_PLLCTRL0 (ID = 77)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK	Input clock
1	DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK	Input clock
2	DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK	Input clock

Clocks for WKUP_PSC0 Device

Device: AM6_DEV_WKUP_PSC0 (ID = 79)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_PSC0_BUS_CLK	Input clock
1	DEV_WKUP_PSC0_BUS_SLOW_CLK	Input clock

Clocks for WKUP_UART0 Device

Device: AM6_DEV_WKUP_UART0 (ID = 150)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_UART0_BUS_FCLK_CLK	Input muxed clock
1	DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0	Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK
2	DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK	Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK
3	DEV_WKUP_UART0_BUS_VBUSP_CLK	Input clock

Clocks for WKUP_VTM0 Device

Device: AM6_DEV_WKUP_VTM0 (ID = 80)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_VTM0_BUS_FIX_REF_CLK	Input clock
1	DEV_WKUP_VTM0_BUS_VBUSP_CLK	Input clock