EDMA3 Resource Manager: edma3_rl

00001 /******************************************************************************
00002 **+-------------------------------------------------------------------------+**
00003 **|                            ****                                         |**
00004 **|                            ****                                         |**
00005 **|                            ******o***                                   |**
00006 **|                      ********_///_****                                  |**
00007 **|                      ***** /_//_/ ****                                  |**
00008 **|                       ** ** (__/ ****                                   |**
00009 **|                           *********                                     |**
00010 **|                            ****                                         |**
00011 **|                            ***                                          |**
00012 **|                                                                         |**
00013 **|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
00014 **|                        ALL RIGHTS RESERVED                              |**
00015 **|                                                                         |**
00016 **| Permission is hereby granted to licensees of Texas Instruments          |**
00017 **| Incorporated (TI) products to use this computer program for the sole    |**
00018 **| purpose of implementing a licensee product based on TI products.        |**
00019 **| No other rights to reproduce, use, or disseminate this computer         |**
00020 **| program, whether in part or in whole, are granted.                      |**
00021 **|                                                                         |**
00022 **| TI makes no representation or warranties with respect to the            |**
00023 **| performance of this computer program, and specifically disclaims        |**
00024 **| any responsibility for any damages, special or consequential,           |**
00025 **| connected with the use of this program.                                 |**
00026 **|                                                                         |**
00027 **+-------------------------------------------------------------------------+**
00028 ******************************************************************************/
00029 
00042 #ifndef _EDMA3_RL_TC_H_
00043 #define _EDMA3_RL_TC_H_
00044 
00045 #ifdef __cplusplus
00046 extern "C" {
00047 #endif
00048 
00049 /**************************************************************************\
00050 * Register Overlay Structure for DFIREG
00051 \**************************************************************************/
00052 typedef struct  {
00053     volatile unsigned int DFOPT;
00054     volatile unsigned int DFSRC;
00055     volatile unsigned int DFCNT;
00056     volatile unsigned int DFDST;
00057     volatile unsigned int DFBIDX;
00058     volatile unsigned int DFMPPRXY;
00059     volatile unsigned char RSVD0[40];
00060 } EDMA3_TCRL_DfiregRegs;
00061 
00062 /**************************************************************************\
00063 * Register Overlay Structure
00064 \**************************************************************************/
00065 typedef struct  {
00066     volatile unsigned int REV;
00067     volatile unsigned int TCCFG;
00068     volatile unsigned char RSVD0[248];
00069     volatile unsigned int TCSTAT;
00070     volatile unsigned int INTSTAT;
00071     volatile unsigned int INTEN;
00072     volatile unsigned int INTCLR;
00073     volatile unsigned int INTCMD;
00074     volatile unsigned char RSVD1[12];
00075     volatile unsigned int ERRSTAT;
00076     volatile unsigned int ERREN;
00077     volatile unsigned int ERRCLR;
00078     volatile unsigned int ERRDET;
00079     volatile unsigned int ERRCMD;
00080     volatile unsigned char RSVD2[12];
00081     volatile unsigned int RDRATE;
00082     volatile unsigned char RSVD3[188];
00083     volatile unsigned int POPT;
00084     volatile unsigned int PSRC;
00085     volatile unsigned int PCNT;
00086     volatile unsigned int PDST;
00087     volatile unsigned int PBIDX;
00088     volatile unsigned int PMPPRXY;
00089     volatile unsigned char RSVD4[40];
00090     volatile unsigned int SAOPT;
00091     volatile unsigned int SASRC;
00092     volatile unsigned int SACNT;
00093     volatile unsigned int SADST;
00094     volatile unsigned int SABIDX;
00095     volatile unsigned int SAMPPRXY;
00096     volatile unsigned int SACNTRLD;
00097     volatile unsigned int SASRCBREF;
00098     volatile unsigned int SADSTBREF;
00099     volatile unsigned char RSVD5[28];
00100     volatile unsigned int DFCNTRLD;
00101     volatile unsigned int DFSRCBREF;
00102     volatile unsigned int DFDSTBREF;
00103     volatile unsigned char RSVD6[116];
00104     EDMA3_TCRL_DfiregRegs DFIREG[4];
00105 } EDMA3_TCRL_Regs;
00106 
00107 /**************************************************************************\
00108 * Field Definition Macros
00109 \**************************************************************************/
00110 
00111 /* REV */
00112 
00113 #define EDMA3_TCRL_REV_TYPE_MASK         (0x00FF0000u)
00114 #define EDMA3_TCRL_REV_TYPE_SHIFT        (0x00000010u)
00115 #define EDMA3_TCRL_REV_TYPE_RESETVAL     (0x00000006u)
00116 
00117 #define EDMA3_TCRL_REV_CLASS_MASK        (0x0000FF00u)
00118 #define EDMA3_TCRL_REV_CLASS_SHIFT       (0x00000008u)
00119 #define EDMA3_TCRL_REV_CLASS_RESETVAL    (0x00000004u)
00120 
00121 #define EDMA3_TCRL_REV_REV_MASK          (0x000000FFu)
00122 #define EDMA3_TCRL_REV_REV_SHIFT         (0x00000000u)
00123 #define EDMA3_TCRL_REV_REV_RESETVAL      (0x00000001u)
00124 
00125 #define EDMA3_TCRL_REV_RESETVAL          (0x00060401u)
00126 
00127 /* TCCFG */
00128 
00129 #define EDMA3_TCRL_TCCFG_DREGDEPTH_MASK  (0x00000300u)
00130 #define EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT (0x00000008u)
00131 #define EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL (0x00000000u)
00132 
00133 /*----DREGDEPTH Tokens----*/
00134 #define EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY (0x00000000u)
00135 #define EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY (0x00000001u)
00136 #define EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY (0x00000002u)
00137 
00138 #define EDMA3_TCRL_TCCFG_BUSWIDTH_MASK   (0x00000030u)
00139 #define EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT  (0x00000004u)
00140 #define EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL (0x00000000u)
00141 
00142 /*----BUSWIDTH Tokens----*/
00143 #define EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT  (0x00000000u)
00144 #define EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY  (0x00000001u)
00145 #define EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT (0x00000002u)
00146 
00147 #define EDMA3_TCRL_TCCFG_FIFOSIZE_MASK   (0x00000007u)
00148 #define EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT  (0x00000000u)
00149 #define EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL (0x00000000u)
00150 
00151 /*----FIFOSIZE Tokens----*/
00152 #define EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE (0x00000000u)
00153 #define EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE (0x00000001u)
00154 #define EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE (0x00000002u)
00155 #define EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE (0x00000003u)
00156 #define EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE (0x00000004u)
00157 
00158 #define EDMA3_TCRL_TCCFG_RESETVAL        (0x00000000u)
00159 
00160 /* TCSTAT */
00161 
00162 #define EDMA3_TCRL_TCSTAT_DFSTRT_MASK  (0x00003000u)
00163 #define EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT (0x0000000Cu)
00164 #define EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL (0x00000000u)
00165 
00166 #define EDMA3_TCRL_TCSTAT_ATCV_MASK    (0x00000100u)
00167 #define EDMA3_TCRL_TCSTAT_ATCV_SHIFT   (0x00000008u)
00168 #define EDMA3_TCRL_TCSTAT_ATCV_RESETVAL (0x00000000u)
00169 
00170 /*----ATCV Tokens----*/
00171 #define EDMA3_TCRL_TCSTAT_ATCV_IDLE    (0x00000000u)
00172 #define EDMA3_TCRL_TCSTAT_ATCV_BUSY    (0x00000001u)
00173 
00174 #define EDMA3_TCRL_TCSTAT_DSTACT_MASK  (0x00000070u)
00175 #define EDMA3_TCRL_TCSTAT_DSTACT_SHIFT (0x00000004u)
00176 #define EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL (0x00000000u)
00177 
00178 /*----DSTACT Tokens----*/
00179 #define EDMA3_TCRL_TCSTAT_DSTACT_EMPTY (0x00000000u)
00180 #define EDMA3_TCRL_TCSTAT_DSTACT_1TR   (0x00000001u)
00181 #define EDMA3_TCRL_TCSTAT_DSTACT_2TR   (0x00000002u)
00182 #define EDMA3_TCRL_TCSTAT_DSTACT_3TR   (0x00000003u)
00183 #define EDMA3_TCRL_TCSTAT_DSTACT_4TR   (0x00000004u)
00184 
00185 #define EDMA3_TCRL_TCSTAT_WSACTV_MASK  (0x00000004u)
00186 #define EDMA3_TCRL_TCSTAT_WSACTV_SHIFT (0x00000002u)
00187 #define EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL (0x00000000u)
00188 
00189 /*----WSACTV Tokens----*/
00190 #define EDMA3_TCRL_TCSTAT_WSACTV_NONE  (0x00000000u)
00191 #define EDMA3_TCRL_TCSTAT_WSACTV_PEND  (0x00000001u)
00192 
00193 #define EDMA3_TCRL_TCSTAT_SRCACTV_MASK (0x00000002u)
00194 #define EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT (0x00000001u)
00195 #define EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL (0x00000000u)
00196 
00197 /*----SRCACTV Tokens----*/
00198 #define EDMA3_TCRL_TCSTAT_SRCACTV_IDLE (0x00000000u)
00199 #define EDMA3_TCRL_TCSTAT_SRCACTV_BUSY (0x00000001u)
00200 
00201 #define EDMA3_TCRL_TCSTAT_PROGBUSY_MASK (0x00000001u)
00202 #define EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT (0x00000000u)
00203 #define EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL (0x00000000u)
00204 
00205 /*----PROGBUSY Tokens----*/
00206 #define EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE (0x00000000u)
00207 #define EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY (0x00000001u)
00208 
00209 #define EDMA3_TCRL_TCSTAT_RESETVAL     (0x00000000u)
00210 
00211 /* INTSTAT */
00212 
00213 #define EDMA3_TCRL_INTSTAT_TRDONE_MASK   (0x00000002u)
00214 #define EDMA3_TCRL_INTSTAT_TRDONE_SHIFT  (0x00000001u)
00215 #define EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL (0x00000000u)
00216 
00217 /*----TRDONE Tokens----*/
00218 #define EDMA3_TCRL_INTSTAT_TRDONE_NONE   (0x00000000u)
00219 #define EDMA3_TCRL_INTSTAT_TRDONE_DONE   (0x00000001u)
00220 
00221 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK (0x00000001u)
00222 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT (0x00000000u)
00223 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL (0x00000000u)
00224 
00225 /*----PROGEMPTY Tokens----*/
00226 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE (0x00000000u)
00227 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY (0x00000001u)
00228 
00229 #define EDMA3_TCRL_INTSTAT_RESETVAL      (0x00000000u)
00230 
00231 /* INTEN */
00232 
00233 #define EDMA3_TCRL_INTEN_TRDONE_MASK     (0x00000002u)
00234 #define EDMA3_TCRL_INTEN_TRDONE_SHIFT    (0x00000001u)
00235 #define EDMA3_TCRL_INTEN_TRDONE_RESETVAL (0x00000000u)
00236 
00237 /*----TRDONE Tokens----*/
00238 #define EDMA3_TCRL_INTEN_TRDONE_DISABLE  (0x00000000u)
00239 #define EDMA3_TCRL_INTEN_TRDONE_ENABLE   (0x00000001u)
00240 
00241 #define EDMA3_TCRL_INTEN_PROGEMPTY_MASK  (0x00000001u)
00242 #define EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT (0x00000000u)
00243 #define EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL (0x00000000u)
00244 
00245 /*----PROGEMPTY Tokens----*/
00246 #define EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE (0x00000000u)
00247 #define EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE (0x00000001u)
00248 
00249 #define EDMA3_TCRL_INTEN_RESETVAL        (0x00000000u)
00250 
00251 /* INTCLR */
00252 
00253 #define EDMA3_TCRL_INTCLR_TRDONE_MASK    (0x00000002u)
00254 #define EDMA3_TCRL_INTCLR_TRDONE_SHIFT   (0x00000001u)
00255 #define EDMA3_TCRL_INTCLR_TRDONE_RESETVAL (0x00000000u)
00256 
00257 /*----TRDONE Tokens----*/
00258 #define EDMA3_TCRL_INTCLR_TRDONE_CLEAR   (0x00000001u)
00259 
00260 #define EDMA3_TCRL_INTCLR_PROGEMPTY_MASK (0x00000001u)
00261 #define EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT (0x00000000u)
00262 #define EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL (0x00000000u)
00263 
00264 /*----PROGEMPTY Tokens----*/
00265 #define EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR (0x00000001u)
00266 
00267 #define EDMA3_TCRL_INTCLR_RESETVAL       (0x00000000u)
00268 
00269 /* INTCMD */
00270 
00271 #define EDMA3_TCRL_INTCMD_SET_MASK       (0x00000002u)
00272 #define EDMA3_TCRL_INTCMD_SET_SHIFT      (0x00000001u)
00273 #define EDMA3_TCRL_INTCMD_SET_RESETVAL   (0x00000000u)
00274 
00275 /*----SET Tokens----*/
00276 #define EDMA3_TCRL_INTCMD_SET_SET        (0x00000001u)
00277 
00278 #define EDMA3_TCRL_INTCMD_EVAL_MASK      (0x00000001u)
00279 #define EDMA3_TCRL_INTCMD_EVAL_SHIFT     (0x00000000u)
00280 #define EDMA3_TCRL_INTCMD_EVAL_RESETVAL  (0x00000000u)
00281 
00282 /*----EVAL Tokens----*/
00283 #define EDMA3_TCRL_INTCMD_EVAL_EVAL      (0x00000001u)
00284 
00285 #define EDMA3_TCRL_INTCMD_RESETVAL       (0x00000000u)
00286 
00287 /* ERRSTAT */
00288 
00289 #define EDMA3_TCRL_ERRSTAT_MMRAERR_MASK  (0x00000008u)
00290 #define EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT (0x00000003u)
00291 #define EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL (0x00000000u)
00292 
00293 /*----MMRAERR Tokens----*/
00294 #define EDMA3_TCRL_ERRSTAT_MMRAERR_NONE  (0x00000000u)
00295 #define EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR (0x00000001u)
00296 
00297 #define EDMA3_TCRL_ERRSTAT_TRERR_MASK    (0x00000004u)
00298 #define EDMA3_TCRL_ERRSTAT_TRERR_SHIFT   (0x00000002u)
00299 #define EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL (0x00000000u)
00300 
00301 /*----TRERR Tokens----*/
00302 #define EDMA3_TCRL_ERRSTAT_TRERR_NONE    (0x00000000u)
00303 #define EDMA3_TCRL_ERRSTAT_TRERR_ERROR   (0x00000001u)
00304 
00305 #define EDMA3_TCRL_ERRSTAT_BUSERR_MASK   (0x00000001u)
00306 #define EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT  (0x00000000u)
00307 #define EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL (0x00000000u)
00308 
00309 /*----BUSERR Tokens----*/
00310 #define EDMA3_TCRL_ERRSTAT_BUSERR_NONE   (0x00000000u)
00311 #define EDMA3_TCRL_ERRSTAT_BUSERR_ERROR  (0x00000001u)
00312 
00313 #define EDMA3_TCRL_ERRSTAT_RESETVAL      (0x00000000u)
00314 
00315 /* ERREN */
00316 
00317 #define EDMA3_TCRL_ERREN_MMRAERR_MASK    (0x00000008u)
00318 #define EDMA3_TCRL_ERREN_MMRAERR_SHIFT   (0x00000003u)
00319 #define EDMA3_TCRL_ERREN_MMRAERR_RESETVAL (0x00000000u)
00320 
00321 /*----MMRAERR Tokens----*/
00322 #define EDMA3_TCRL_ERREN_MMRAERR_ENABLE  (0x00000001u)
00323 #define EDMA3_TCRL_ERREN_MMRAERR_DISABLE (0x00000000u)
00324 
00325 #define EDMA3_TCRL_ERREN_TRERR_MASK      (0x00000004u)
00326 #define EDMA3_TCRL_ERREN_TRERR_SHIFT     (0x00000002u)
00327 #define EDMA3_TCRL_ERREN_TRERR_RESETVAL  (0x00000000u)
00328 
00329 /*----TRERR Tokens----*/
00330 #define EDMA3_TCRL_ERREN_TRERR_ENABLE    (0x00000001u)
00331 #define EDMA3_TCRL_ERREN_TRERR_DISABLE   (0x00000000u)
00332 
00333 #define EDMA3_TCRL_ERREN_BUSERR_MASK     (0x00000001u)
00334 #define EDMA3_TCRL_ERREN_BUSERR_SHIFT    (0x00000000u)
00335 #define EDMA3_TCRL_ERREN_BUSERR_RESETVAL (0x00000000u)
00336 
00337 /*----BUSERR Tokens----*/
00338 #define EDMA3_TCRL_ERREN_BUSERR_ENABLE   (0x00000001u)
00339 #define EDMA3_TCRL_ERREN_BUSERR_DISABLE  (0x00000000u)
00340 
00341 #define EDMA3_TCRL_ERREN_RESETVAL        (0x00000000u)
00342 
00343 /* ERRCLR */
00344 
00345 #define EDMA3_TCRL_ERRCLR_MMRAERR_MASK   (0x00000008u)
00346 #define EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT  (0x00000003u)
00347 #define EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL (0x00000000u)
00348 
00349 /*----MMRAERR Tokens----*/
00350 #define EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR  (0x00000001u)
00351 
00352 #define EDMA3_TCRL_ERRCLR_TRERR_MASK     (0x00000004u)
00353 #define EDMA3_TCRL_ERRCLR_TRERR_SHIFT    (0x00000002u)
00354 #define EDMA3_TCRL_ERRCLR_TRERR_RESETVAL (0x00000000u)
00355 
00356 /*----TRERR Tokens----*/
00357 #define EDMA3_TCRL_ERRCLR_TRERR_CLEAR    (0x00000001u)
00358 
00359 #define EDMA3_TCRL_ERRCLR_BUSERR_MASK    (0x00000001u)
00360 #define EDMA3_TCRL_ERRCLR_BUSERR_SHIFT   (0x00000000u)
00361 #define EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL (0x00000000u)
00362 
00363 /*----BUSERR Tokens----*/
00364 #define EDMA3_TCRL_ERRCLR_BUSERR_CLEAR   (0x00000001u)
00365 
00366 #define EDMA3_TCRL_ERRCLR_RESETVAL       (0x00000000u)
00367 
00368 /* ERRDET */
00369 
00370 #define EDMA3_TCRL_ERRDET_TCCHEN_MASK    (0x00020000u)
00371 #define EDMA3_TCRL_ERRDET_TCCHEN_SHIFT   (0x00000011u)
00372 #define EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL (0x00000000u)
00373 
00374 #define EDMA3_TCRL_ERRDET_TCINTEN_MASK   (0x00010000u)
00375 #define EDMA3_TCRL_ERRDET_TCINTEN_SHIFT  (0x00000010u)
00376 #define EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL (0x00000000u)
00377 
00378 #define EDMA3_TCRL_ERRDET_TCC_MASK       (0x00003F00u)
00379 #define EDMA3_TCRL_ERRDET_TCC_SHIFT      (0x00000008u)
00380 #define EDMA3_TCRL_ERRDET_TCC_RESETVAL   (0x00000000u)
00381 
00382 #define EDMA3_TCRL_ERRDET_STAT_MASK      (0x0000000Fu)
00383 #define EDMA3_TCRL_ERRDET_STAT_SHIFT     (0x00000000u)
00384 #define EDMA3_TCRL_ERRDET_STAT_RESETVAL  (0x00000000u)
00385 
00386 /*----STAT Tokens----*/
00387 #define EDMA3_TCRL_ERRDET_STAT_NONE      (0x00000000u)
00388 #define EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS (0x00000001u)
00389 #define EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE (0x00000002u)
00390 #define EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT (0x00000003u)
00391 #define EDMA3_TCRL_ERRDET_STAT_READ_DATA (0x00000004u)
00392 #define EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE (0x00000007u)
00393 #define EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS (0x00000009u)
00394 #define EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE (0x0000000Au)
00395 #define EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT (0x0000000Bu)
00396 #define EDMA3_TCRL_ERRDET_STAT_WRITE_DATA (0x0000000Cu)
00397 #define EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE (0x0000000Fu)
00398 
00399 #define EDMA3_TCRL_ERRDET_RESETVAL       (0x00000000u)
00400 
00401 /* ERRCMD */
00402 
00403 #define EDMA3_TCRL_ERRCMD_SET_MASK       (0x00000002u)
00404 #define EDMA3_TCRL_ERRCMD_SET_SHIFT      (0x00000001u)
00405 #define EDMA3_TCRL_ERRCMD_SET_RESETVAL   (0x00000000u)
00406 
00407 /*----SET Tokens----*/
00408 #define EDMA3_TCRL_ERRCMD_SET_SET        (0x00000001u)
00409 
00410 #define EDMA3_TCRL_ERRCMD_EVAL_MASK      (0x00000001u)
00411 #define EDMA3_TCRL_ERRCMD_EVAL_SHIFT     (0x00000000u)
00412 #define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL  (0x00000000u)
00413 
00414 /*----EVAL Tokens----*/
00415 #define EDMA3_TCRL_ERRCMD_EVAL_EVAL      (0x00000001u)
00416 
00417 #define EDMA3_TCRL_ERRCMD_RESETVAL       (0x00000000u)
00418 
00419 /* RDRATE */
00420 
00421 #define EDMA3_TCRL_RDRATE_RDRATE_MASK    (0x00000007u)
00422 #define EDMA3_TCRL_RDRATE_RDRATE_SHIFT   (0x00000000u)
00423 #define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL (0x00000000u)
00424 
00425 /*----RDRATE Tokens----*/
00426 #define EDMA3_TCRL_RDRATE_RDRATE_AFAP    (0x00000000u)
00427 #define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE  (0x00000001u)
00428 #define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE  (0x00000002u)
00429 #define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE (0x00000003u)
00430 #define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE (0x00000004u)
00431 
00432 #define EDMA3_TCRL_RDRATE_RESETVAL       (0x00000000u)
00433 
00434 /* POPT */
00435 
00436 #define EDMA3_TCRL_POPT_TCCHEN_MASK      (0x00400000u)
00437 #define EDMA3_TCRL_POPT_TCCHEN_SHIFT     (0x00000016u)
00438 #define EDMA3_TCRL_POPT_TCCHEN_RESETVAL  (0x00000000u)
00439 
00440 /*----TCCHEN Tokens----*/
00441 #define EDMA3_TCRL_POPT_TCCHEN_DISABLE   (0x00000000u)
00442 #define EDMA3_TCRL_POPT_TCCHEN_ENABLE    (0x00000001u)
00443 
00444 #define EDMA3_TCRL_POPT_TCINTEN_MASK     (0x00100000u)
00445 #define EDMA3_TCRL_POPT_TCINTEN_SHIFT    (0x00000014u)
00446 #define EDMA3_TCRL_POPT_TCINTEN_RESETVAL (0x00000000u)
00447 
00448 /*----TCINTEN Tokens----*/
00449 #define EDMA3_TCRL_POPT_TCINTEN_DISABLE  (0x00000000u)
00450 #define EDMA3_TCRL_POPT_TCINTEN_ENABLE   (0x00000001u)
00451 
00452 #define EDMA3_TCRL_POPT_TCC_MASK         (0x0003F000u)
00453 #define EDMA3_TCRL_POPT_TCC_SHIFT        (0x0000000Cu)
00454 #define EDMA3_TCRL_POPT_TCC_RESETVAL     (0x00000000u)
00455 
00456 #define EDMA3_TCRL_POPT_FWID_MASK        (0x00000700u)
00457 #define EDMA3_TCRL_POPT_FWID_SHIFT       (0x00000008u)
00458 #define EDMA3_TCRL_POPT_FWID_RESETVAL    (0x00000000u)
00459 
00460 /*----FWID Tokens----*/
00461 #define EDMA3_TCRL_POPT_FWID_8BIT        (0x00000000u)
00462 #define EDMA3_TCRL_POPT_FWID_16BIT       (0x00000001u)
00463 #define EDMA3_TCRL_POPT_FWID_32BIT       (0x00000002u)
00464 #define EDMA3_TCRL_POPT_FWID_64BIT       (0x00000003u)
00465 #define EDMA3_TCRL_POPT_FWID_128BIT      (0x00000004u)
00466 #define EDMA3_TCRL_POPT_FWID_256BIT      (0x00000005u)
00467 
00468 #define EDMA3_TCRL_POPT_PRI_MASK         (0x00000070u)
00469 #define EDMA3_TCRL_POPT_PRI_SHIFT        (0x00000004u)
00470 #define EDMA3_TCRL_POPT_PRI_RESETVAL     (0x00000000u)
00471 
00472 #define EDMA3_TCRL_POPT_DAM_MASK         (0x00000002u)
00473 #define EDMA3_TCRL_POPT_DAM_SHIFT        (0x00000001u)
00474 #define EDMA3_TCRL_POPT_DAM_RESETVAL     (0x00000000u)
00475 
00476 /*----DAM Tokens----*/
00477 #define EDMA3_TCRL_POPT_DAM_INCR         (0x00000000u)
00478 #define EDMA3_TCRL_POPT_DAM_FIFO         (0x00000001u)
00479 
00480 #define EDMA3_TCRL_POPT_SAM_MASK         (0x00000001u)
00481 #define EDMA3_TCRL_POPT_SAM_SHIFT        (0x00000000u)
00482 #define EDMA3_TCRL_POPT_SAM_RESETVAL     (0x00000000u)
00483 
00484 /*----SAM Tokens----*/
00485 #define EDMA3_TCRL_POPT_SAM_INCR         (0x00000000u)
00486 #define EDMA3_TCRL_POPT_SAM_FIFO         (0x00000001u)
00487 
00488 #define EDMA3_TCRL_POPT_RESETVAL         (0x00000000u)
00489 
00490 /* PSRC */
00491 
00492 #define EDMA3_TCRL_PSRC_SADDR_MASK       (0xFFFFFFFFu)
00493 #define EDMA3_TCRL_PSRC_SADDR_SHIFT      (0x00000000u)
00494 #define EDMA3_TCRL_PSRC_SADDR_RESETVAL   (0x00000000u)
00495 
00496 #define EDMA3_TCRL_PSRC_RESETVAL         (0x00000000u)
00497 
00498 /* PCNT */
00499 
00500 #define EDMA3_TCRL_PCNT_BCNT_MASK        (0xFFFF0000u)
00501 #define EDMA3_TCRL_PCNT_BCNT_SHIFT       (0x00000010u)
00502 #define EDMA3_TCRL_PCNT_BCNT_RESETVAL    (0x00000000u)
00503 
00504 #define EDMA3_TCRL_PCNT_ACNT_MASK        (0x0000FFFFu)
00505 #define EDMA3_TCRL_PCNT_ACNT_SHIFT       (0x00000000u)
00506 #define EDMA3_TCRL_PCNT_ACNT_RESETVAL    (0x00000000u)
00507 
00508 #define EDMA3_TCRL_PCNT_RESETVAL         (0x00000000u)
00509 
00510 /* PDST */
00511 
00512 #define EDMA3_TCRL_PDST_DADDR_MASK       (0xFFFFFFFFu)
00513 #define EDMA3_TCRL_PDST_DADDR_SHIFT      (0x00000000u)
00514 #define EDMA3_TCRL_PDST_DADDR_RESETVAL   (0x00000000u)
00515 
00516 #define EDMA3_TCRL_PDST_RESETVAL         (0x00000000u)
00517 
00518 /* PBIDX */
00519 
00520 #define EDMA3_TCRL_PBIDX_DBIDX_MASK      (0xFFFF0000u)
00521 #define EDMA3_TCRL_PBIDX_DBIDX_SHIFT     (0x00000010u)
00522 #define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL  (0x00000000u)
00523 
00524 #define EDMA3_TCRL_PBIDX_SBIDX_MASK      (0x0000FFFFu)
00525 #define EDMA3_TCRL_PBIDX_SBIDX_SHIFT     (0x00000000u)
00526 #define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL  (0x00000000u)
00527 
00528 #define EDMA3_TCRL_PBIDX_RESETVAL        (0x00000000u)
00529 
00530 /* PMPPRXY */
00531 
00532 #define EDMA3_TCRL_PMPPRXY_PRIV_MASK     (0x00000100u)
00533 #define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT    (0x00000008u)
00534 #define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL (0x00000000u)
00535 
00536 /*----PRIV Tokens----*/
00537 #define EDMA3_TCRL_PMPPRXY_PRIV_USER     (0x00000000u)
00538 #define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00539 
00540 #define EDMA3_TCRL_PMPPRXY_PRIVID_MASK   (0x0000000Fu)
00541 #define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT  (0x00000000u)
00542 #define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL (0x00000000u)
00543 
00544 #define EDMA3_TCRL_PMPPRXY_RESETVAL      (0x00000000u)
00545 
00546 /* SAOPT */
00547 
00548 #define EDMA3_TCRL_SAOPT_TCCHEN_MASK     (0x00400000u)
00549 #define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT    (0x00000016u)
00550 #define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL (0x00000000u)
00551 
00552 /*----TCCHEN Tokens----*/
00553 #define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE  (0x00000000u)
00554 #define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE   (0x00000001u)
00555 
00556 #define EDMA3_TCRL_SAOPT_TCINTEN_MASK    (0x00100000u)
00557 #define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT   (0x00000014u)
00558 #define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL (0x00000000u)
00559 
00560 /*----TCINTEN Tokens----*/
00561 #define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE (0x00000000u)
00562 #define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE  (0x00000001u)
00563 
00564 #define EDMA3_TCRL_SAOPT_TCC_MASK        (0x0003F000u)
00565 #define EDMA3_TCRL_SAOPT_TCC_SHIFT       (0x0000000Cu)
00566 #define EDMA3_TCRL_SAOPT_TCC_RESETVAL    (0x00000000u)
00567 
00568 #define EDMA3_TCRL_SAOPT_FWID_MASK       (0x00000700u)
00569 #define EDMA3_TCRL_SAOPT_FWID_SHIFT      (0x00000008u)
00570 #define EDMA3_TCRL_SAOPT_FWID_RESETVAL   (0x00000000u)
00571 
00572 /*----FWID Tokens----*/
00573 #define EDMA3_TCRL_SAOPT_FWID_8BIT       (0x00000000u)
00574 #define EDMA3_TCRL_SAOPT_FWID_16BIT      (0x00000001u)
00575 #define EDMA3_TCRL_SAOPT_FWID_32BIT      (0x00000002u)
00576 #define EDMA3_TCRL_SAOPT_FWID_64BIT      (0x00000003u)
00577 #define EDMA3_TCRL_SAOPT_FWID_128BIT     (0x00000004u)
00578 #define EDMA3_TCRL_SAOPT_FWID_256BIT     (0x00000005u)
00579 
00580 #define EDMA3_TCRL_SAOPT_PRI_MASK        (0x00000070u)
00581 #define EDMA3_TCRL_SAOPT_PRI_SHIFT       (0x00000004u)
00582 #define EDMA3_TCRL_SAOPT_PRI_RESETVAL    (0x00000000u)
00583 
00584 #define EDMA3_TCRL_SAOPT_DAM_MASK        (0x00000002u)
00585 #define EDMA3_TCRL_SAOPT_DAM_SHIFT       (0x00000001u)
00586 #define EDMA3_TCRL_SAOPT_DAM_RESETVAL    (0x00000000u)
00587 
00588 /*----DAM Tokens----*/
00589 #define EDMA3_TCRL_SAOPT_DAM_INCR        (0x00000000u)
00590 #define EDMA3_TCRL_SAOPT_DAM_FIFO        (0x00000001u)
00591 
00592 #define EDMA3_TCRL_SAOPT_SAM_MASK        (0x00000001u)
00593 #define EDMA3_TCRL_SAOPT_SAM_SHIFT       (0x00000000u)
00594 #define EDMA3_TCRL_SAOPT_SAM_RESETVAL    (0x00000000u)
00595 
00596 /*----SAM Tokens----*/
00597 #define EDMA3_TCRL_SAOPT_SAM_INCR        (0x00000000u)
00598 #define EDMA3_TCRL_SAOPT_SAM_FIFO        (0x00000001u)
00599 
00600 #define EDMA3_TCRL_SAOPT_RESETVAL        (0x00000000u)
00601 
00602 /* SASRC */
00603 
00604 #define EDMA3_TCRL_SASRC_SADDR_MASK      (0xFFFFFFFFu)
00605 #define EDMA3_TCRL_SASRC_SADDR_SHIFT     (0x00000000u)
00606 #define EDMA3_TCRL_SASRC_SADDR_RESETVAL  (0x00000000u)
00607 
00608 #define EDMA3_TCRL_SASRC_RESETVAL        (0x00000000u)
00609 
00610 /* SACNT */
00611 
00612 #define EDMA3_TCRL_SACNT_BCNT_MASK       (0xFFFF0000u)
00613 #define EDMA3_TCRL_SACNT_BCNT_SHIFT      (0x00000010u)
00614 #define EDMA3_TCRL_SACNT_BCNT_RESETVAL   (0x00000000u)
00615 
00616 #define EDMA3_TCRL_SACNT_ACNT_MASK       (0x0000FFFFu)
00617 #define EDMA3_TCRL_SACNT_ACNT_SHIFT      (0x00000000u)
00618 #define EDMA3_TCRL_SACNT_ACNT_RESETVAL   (0x00000000u)
00619 
00620 #define EDMA3_TCRL_SACNT_RESETVAL        (0x00000000u)
00621 
00622 /* SADST */
00623 
00624 #define EDMA3_TCRL_SADST_RESETVAL        (0x00000000u)
00625 
00626 /* SABIDX */
00627 
00628 #define EDMA3_TCRL_SABIDX_DBIDX_MASK     (0xFFFF0000u)
00629 #define EDMA3_TCRL_SABIDX_DBIDX_SHIFT    (0x00000010u)
00630 #define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL (0x00000000u)
00631 
00632 #define EDMA3_TCRL_SABIDX_SBIDX_MASK     (0x0000FFFFu)
00633 #define EDMA3_TCRL_SABIDX_SBIDX_SHIFT    (0x00000000u)
00634 #define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL (0x00000000u)
00635 
00636 #define EDMA3_TCRL_SABIDX_RESETVAL       (0x00000000u)
00637 
00638 /* SAMPPRXY */
00639 
00640 #define EDMA3_TCRL_SAMPPRXY_PRIV_MASK    (0x00000100u)
00641 #define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT   (0x00000008u)
00642 #define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL (0x00000000u)
00643 
00644 /*----PRIV Tokens----*/
00645 #define EDMA3_TCRL_SAMPPRXY_PRIV_USER    (0x00000000u)
00646 #define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00647 
00648 #define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK  (0x0000000Fu)
00649 #define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT (0x00000000u)
00650 #define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL (0x00000000u)
00651 
00652 #define EDMA3_TCRL_SAMPPRXY_RESETVAL     (0x00000000u)
00653 
00654 /* SACNTRLD */
00655 
00656 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK (0x0000FFFFu)
00657 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT (0x00000000u)
00658 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL (0x00000000u)
00659 
00660 #define EDMA3_TCRL_SACNTRLD_RESETVAL     (0x00000000u)
00661 
00662 /* SASRCBREF */
00663 
00664 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK (0xFFFFFFFFu)
00665 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT (0x00000000u)
00666 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL (0x00000000u)
00667 
00668 #define EDMA3_TCRL_SASRCBREF_RESETVAL    (0x00000000u)
00669 
00670 /* SADSTBREF */
00671 
00672 #define EDMA3_TCRL_SADSTBREF_RESETVAL    (0x00000000u)
00673 
00674 /* DFCNTRLD */
00675 
00676 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFu)
00677 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT (0x00000000u)
00678 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000u)
00679 
00680 #define EDMA3_TCRL_DFCNTRLD_RESETVAL     (0x00000000u)
00681 
00682 /* DFSRCBREF */
00683 
00684 #define EDMA3_TCRL_DFSRCBREF_RESETVAL    (0x00000000u)
00685 
00686 /* DFDSTBREF */
00687 
00688 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFu)
00689 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT (0x00000000u)
00690 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000u)
00691 
00692 #define EDMA3_TCRL_DFDSTBREF_RESETVAL    (0x00000000u)
00693 
00694 /* DFOPT */
00695 
00696 #define EDMA3_TCRL_DFOPT_TCCHEN_MASK     (0x00400000u)
00697 #define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT    (0x00000016u)
00698 #define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL (0x00000000u)
00699 
00700 /*----TCCHEN Tokens----*/
00701 #define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE  (0x00000000u)
00702 #define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE   (0x00000001u)
00703 
00704 #define EDMA3_TCRL_DFOPT_TCINTEN_MASK    (0x00100000u)
00705 #define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT   (0x00000014u)
00706 #define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL (0x00000000u)
00707 
00708 /*----TCINTEN Tokens----*/
00709 #define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE (0x00000000u)
00710 #define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE  (0x00000001u)
00711 
00712 #define EDMA3_TCRL_DFOPT_TCC_MASK        (0x0003F000u)
00713 #define EDMA3_TCRL_DFOPT_TCC_SHIFT       (0x0000000Cu)
00714 #define EDMA3_TCRL_DFOPT_TCC_RESETVAL    (0x00000000u)
00715 
00716 #define EDMA3_TCRL_DFOPT_FWID_MASK       (0x00000700u)
00717 #define EDMA3_TCRL_DFOPT_FWID_SHIFT      (0x00000008u)
00718 #define EDMA3_TCRL_DFOPT_FWID_RESETVAL   (0x00000000u)
00719 
00720 /*----FWID Tokens----*/
00721 #define EDMA3_TCRL_DFOPT_FWID_8BIT       (0x00000000u)
00722 #define EDMA3_TCRL_DFOPT_FWID_16BIT      (0x00000001u)
00723 #define EDMA3_TCRL_DFOPT_FWID_32BIT      (0x00000002u)
00724 #define EDMA3_TCRL_DFOPT_FWID_64BIT      (0x00000003u)
00725 #define EDMA3_TCRL_DFOPT_FWID_128BIT     (0x00000004u)
00726 #define EDMA3_TCRL_DFOPT_FWID_256BIT     (0x00000005u)
00727 
00728 #define EDMA3_TCRL_DFOPT_PRI_MASK        (0x00000070u)
00729 #define EDMA3_TCRL_DFOPT_PRI_SHIFT       (0x00000004u)
00730 #define EDMA3_TCRL_DFOPT_PRI_RESETVAL    (0x00000000u)
00731 
00732 #define EDMA3_TCRL_DFOPT_DAM_MASK        (0x00000002u)
00733 #define EDMA3_TCRL_DFOPT_DAM_SHIFT       (0x00000001u)
00734 #define EDMA3_TCRL_DFOPT_DAM_RESETVAL    (0x00000000u)
00735 
00736 /*----DAM Tokens----*/
00737 #define EDMA3_TCRL_DFOPT_DAM_INCR        (0x00000000u)
00738 #define EDMA3_TCRL_DFOPT_DAM_FIFO        (0x00000001u)
00739 
00740 #define EDMA3_TCRL_DFOPT_SAM_MASK        (0x00000001u)
00741 #define EDMA3_TCRL_DFOPT_SAM_SHIFT       (0x00000000u)
00742 #define EDMA3_TCRL_DFOPT_SAM_RESETVAL    (0x00000000u)
00743 
00744 /*----SAM Tokens----*/
00745 #define EDMA3_TCRL_DFOPT_SAM_INCR        (0x00000000u)
00746 #define EDMA3_TCRL_DFOPT_SAM_FIFO        (0x00000001u)
00747 
00748 #define EDMA3_TCRL_DFOPT_RESETVAL        (0x00000000u)
00749 
00750 /* DFSRC */
00751 
00752 #define EDMA3_TCRL_DFSRC_RESETVAL        (0x00000000u)
00753 
00754 /* DFCNT */
00755 
00756 #define EDMA3_TCRL_DFCNT_BCNT_MASK       (0xFFFF0000u)
00757 #define EDMA3_TCRL_DFCNT_BCNT_SHIFT      (0x00000010u)
00758 #define EDMA3_TCRL_DFCNT_BCNT_RESETVAL   (0x00000000u)
00759 
00760 #define EDMA3_TCRL_DFCNT_ACNT_MASK       (0x0000FFFFu)
00761 #define EDMA3_TCRL_DFCNT_ACNT_SHIFT      (0x00000000u)
00762 #define EDMA3_TCRL_DFCNT_ACNT_RESETVAL   (0x00000000u)
00763 
00764 #define EDMA3_TCRL_DFCNT_RESETVAL        (0x00000000u)
00765 
00766 /* DFDST */
00767 
00768 #define EDMA3_TCRL_DFDST_DADDR_MASK      (0xFFFFFFFFu)
00769 #define EDMA3_TCRL_DFDST_DADDR_SHIFT     (0x00000000u)
00770 #define EDMA3_TCRL_DFDST_DADDR_RESETVAL  (0x00000000u)
00771 
00772 #define EDMA3_TCRL_DFDST_RESETVAL        (0x00000000u)
00773 
00774 /* DFBIDX */
00775 
00776 #define EDMA3_TCRL_DFBIDX_DBIDX_MASK     (0xFFFF0000u)
00777 #define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT    (0x00000010u)
00778 #define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL (0x00000000u)
00779 
00780 #define EDMA3_TCRL_DFBIDX_SBIDX_MASK     (0x0000FFFFu)
00781 #define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT    (0x00000000u)
00782 #define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL (0x00000000u)
00783 
00784 #define EDMA3_TCRL_DFBIDX_RESETVAL       (0x00000000u)
00785 
00786 /* DFMPPRXY */
00787 
00788 #define EDMA3_TCRL_DFMPPRXY_PRIV_MASK    (0x00000100u)
00789 #define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT   (0x00000008u)
00790 #define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL (0x00000000u)
00791 
00792 /*----PRIV Tokens----*/
00793 #define EDMA3_TCRL_DFMPPRXY_PRIV_USER    (0x00000000u)
00794 #define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00795 
00796 #define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK  (0x0000000Fu)
00797 #define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT (0x00000000u)
00798 #define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL (0x00000000u)
00799 
00800 #define EDMA3_TCRL_DFMPPRXY_RESETVAL     (0x00000000u)
00801 
00802 #ifdef __cplusplus
00803 }
00804 #endif /* extern "C" */
00805 
00806 #endif  /* _EDMA3_RL_TC_H_ */
edma3_rl_tc.h
