31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0 0000

11

OE

UART Overrun Error:
This bit is set to 1 if data is received and the receive **FIFO** is already full. The **FIFO** contents remain valid because no more data is written when the **FIFO** is full, , only the contents of the shift register are overwritten.
This is cleared to 0 once there is an empty space in the **FIFO** and a new character can be written to it.

RO

0

10

BE

UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the **FIFO**. The next character is enabled after the receive data input (**UARTRXD** input pin) goes to a 1 (marking state), and the next valid start bit is received.

RO

0

9

PE

UART Parity Error:
When set to 1, it indicates that the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.
In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read).

RO

0

8

FE

UART Framing Error:
When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read).

RO

0

7:0

DATA

Data transmitted or received:
On writes, the transmit data character is pushed into the **FIFO**.
On reads, the oldest received data character since the last read is returned.

RW

0x00

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

3

OE

UART Overrun Error:
This bit is set to 1 if data is received and the receive **FIFO** is already full. The **FIFO** contents remain valid because no more data is written when the **FIFO** is full, , only the contents of the shift register are overwritten.
This is cleared to 0 once there is an empty space in the **FIFO** and a new character can be written to it.

RW

0

2

BE

UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
When a break occurs, a 0 character is loaded into the **FIFO**. The next character is enabled after the receive data input (**UARTRXD** input pin) goes to a 1 (marking state), and the next valid start bit is received.

RW

0

1

PE

UART Parity Error:
When set to 1, it indicates that the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.

RW

0

0

FE

UART Framing Error:
When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).

RW

0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7

TXFE

UART Transmit **FIFO** Empty:
The meaning of this bit depends on the state of [LCRH.FEN] .
- If the **FIFO** is disabled, this bit is set when the transmit holding register is empty.
- If the **FIFO** is enabled, this bit is set when the transmit **FIFO** is empty.
This bit does not indicate if there is data in the transmit shift register.

RO

1

6

RXFF

UART Receive **FIFO** Full:
The meaning of this bit depends on the state of [LCRH.FEN].
- If the **FIFO** is disabled, this bit is set when the receive holding register is full.
- If the **FIFO** is enabled, this bit is set when the receive **FIFO** is full.

RO

0

5

TXFF

UART Transmit **FIFO** Full:
Transmit **FIFO** full. The meaning of this bit depends on the state of [LCRH.FEN].
- If the **FIFO** is disabled, this bit is set when the transmit holding register is full.
- If the **FIFO** is enabled, this bit is set when the transmit **FIFO** is full.

RO

0

4

RXFE

UART Receive **FIFO** Empty:
Receive **FIFO** empty. The meaning of this bit depends on the state of [LCRH.FEN].
- If the **FIFO** is disabled, this bit is set when the receive holding register is empty.
- If the **FIFO** is enabled, this bit is set when the receive **FIFO** is empty.

RO

1

3

BUSY

UART Busy:
If this bit is set to 1, the **UART** is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register.
This bit is set as soon as the transmit **FIFO** becomes non-empty, regardless of whether the **UART** is enabled or not.

RO

0

2:1

Reserved

Reserved

RO

0x0

0

CTS

Clear To Send:
This bit is the complement of the active-low **UART** **CTS** input pin.
That is, the bit is 1 when **CTS** input pin is LOW.

RO

0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00 0000

7:0

ILPDVSR

8 bit low-power divisor value

RW

0x00

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0000

15:0

DIVINT

The integer baud rate divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, [DIVINT]=0 does not give a valid baud rate.
Similarly, if [DIVINT]=0xFFFF, any non-zero values in [FBRD.DIVFRAC] will be illegal.
A valid value must be written to this field before the **UART** can be used for **RX** or **TX** operations.
INTERNAL_NOTE
The calculator below can be used to find the register values:
[Baud-rate calculator](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/UART_baudrate_calculator.xlsx)

RW

0x0000

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x000 0000

5:0

DIVFRAC

Fractional Baud-Rate Divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, [IBRD.DIVINT]=0 does not give a valid baud rate.
Similarly, if [IBRD.DIVINT]=0xFFFF, any non-zero values in [DIVFRAC] will be illegal.
A valid value must be written to this field before the **UART** can be used for **RX** or **TX** operations.
INTERNAL_NOTE
The calculator below can be used to find the register values:
[Baud-rate calculator](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/UART_baudrate_calculator.xlsx)

RW

0x00

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00 0000

10:9

DELIM

In UART LIN defines the length of DELIM field that has to be sent

RW

0x1

8

TXBRKSYNC

UART LIN mode TXBRKSYNC:
0: In LIN mode TXBRKSYNC will not be sent.
1: In LIN mode send TXBRKSYNC field and reset the LCRH.TXBRKSYNC bit.
This bit has no effect when [PEN] disables parity checking and generation.

RW

0

7

SPS

UART Stick Parity Select:
0: Stick parity is disabled
1: The parity bit is transmitted and checked as invert of [EPS] field (i.e. the parity bit is transmitted and checked as 1 when [EPS] = 0).
This bit has no effect when [PEN] disables parity checking and generation.

RW

0

6:5

WLEN

UART Word Length:
These bits indicate the number of data bits transmitted or received in a frame.

RW

0x0

4

FEN

UART Enable **FIFO**s

RW

0

3

STP2

UART Two Stop Bits Select:
If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

RW

0

2

EPS

UART Even Parity Select

RW

0

1

PEN

UART Parity Enable
This bit controls generation and checking of parity bit.
INTERNAL_NOTE
See [Parity truth table](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/parity.png) for details.

RW

0

0

BRK

UART Send Break
If this bit is set to 1, a low-level is continually output on the **UARTTXD** output pin, after completing transmission of the current character. For the proper execution of the break command, the
software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

RW

0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15

CTSEN

**CTS** hardware flow control enable

RW

0

14

RTSEN

**RTS** hardware flow control enable

RW

0

13:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0

11

RTS

Request to Send
This bit is the complement of the active-low **UART** **RTS** output. That is, when the bit is programmed to a 1 then **RTS** output on the pins is LOW.

RW

0

10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0

9

RXE

UART Receive Enable
If the **UART** is disabled in the middle of reception, it completes the current character before stopping.

RW

1

8

TXE

UART Transmit Enable
If the **UART** is disabled in the middle of transmission, it completes the current character before stopping.

RW

1

7

LBE

UART Loop Back Enable
Enabling the loop-back mode connects the **UARTTXD** output from the **UART** to **UARTRXD** input of the **UART**.

RW

0

6

FCEN

UART FIFO Concatenation Enable
Enabling the lFIFO concatenation in TX moderesulting in 16 TX buffers.

RW

0

5

DORMEN

DORMEN bit is only functionally makes sense for LIN mode of operation.
When dormant mode is disabled, break and sync data shall be loaded to RX FIFO and associated interrupt flags shall be set as in normal UART operation.
When dormant mode is enabled, break and sync data shall not be loaded to RX FIFO and RX FIFO shall be updated with actual data (PID) only after successful reception of break/sync fields.

RW

0

4

ABDEN

This configuration bit defines whether we want automatic baud rate detection enabled or not in the LIN mode of operation.

RW

0

3

LINEN

This is the LIN Mode of operation configuration bit.

RW

0

2

SIRLP

SIR low power IrDA mode
This bit selects the IrDA encoding mode

RW

0

1

SIREN

SIR Enable
This bit has no effect if UARTEN bit disables the UART.

RW

0

0

UARTEN

UART Enable

RW

0

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x000 0000

5:3

RXSEL

Receive interrupt **FIFO** level select:
This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved.

RW

0x2

2:0

TXSEL

Transmit interrupt **FIFO** level select:
This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved.

RW

0x2

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0000

16

LINSYNCTOE

LIN Sync Time out error interrupt mask. A read returns the current mask for UART's LINSYNCTOE interrupt. On a write of 1, the mask of the LINSYNCTOE interrupt is set which means the interrupt state will be reflected in MIS.LINSYNCTOE. A write of 0 clears the mask which means MIS.LINSYNCTOE will not reflect the interrupt.

RW

0

15

LINBRKTOE

LIN Break field Time out error interrupt mask. A read returns the current mask for UART's LINBRKTOE interrupt. On a write of 1, the mask of the LINBRKTOE interrupt is set which means the interrupt state will be reflected in MIS.LINBRKTOE. A write of 0 clears the mask which means MIS.LINBRKTOE will not reflect the interrupt.

RW

0

14

LINBRK

LIN Break field received/detected interrupt mask. A read returns the current mask for UART's LINBRK interrupt. On a write of 1, the mask of the LINBRK interrupt is set which means the interrupt state will be reflected in MIS.LINBRK. A write of 0 clears the mask which means MIS.LINBRK will not reflect the interrupt.

RW

0

13

RXDMADONE

Rx DMA done interrupt mask. A read returns the current mask for UART's RXDMADONE interrupt. On a write of 1, the mask of the RXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.RXDMADONE. A write of 0 clears the mask which means MIS.RXDMADONE will not reflect the interrupt.

RW

0

12

TXDMADONE

Tx DMA done interrupt mask. A read returns the current mask for UART's TXDMADONE interrupt. On a write of 1, the mask of the TXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.TXDMADONE. A write of 0 clears the mask which means MIS.TXDMADONE will not reflect the interrupt.

RW

0

11

EOT

End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOT. A write of 0 clears the mask which means MIS.EOT will not reflect the interrupt.

RW

0

10

OE

Overrun error interrupt mask. A read returns the current mask for **UART**'s overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.OE]. A write of 0 clears the mask which means [MIS.OE] will not reflect the interrupt.

RW

0

9

BE

Break error interrupt mask. A read returns the current mask for **UART**'s break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.BE]. A write of 0 clears the mask which means [MIS.BE] will not reflect the interrupt.

RW

0

8

PE

Parity error interrupt mask. A read returns the current mask for **UART**'s parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.PE]. A write of 0 clears the mask which means [MIS.PE] will not reflect the interrupt.

RW

0

7

FE

Framing error interrupt mask. A read returns the current mask for **UART**'s framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.FE]. A write of 0 clears the mask which means [MIS.FE] will not reflect the interrupt.

RW

0

6

RT

Receive timeout interrupt mask. A read returns the current mask for **UART**'s receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.RT]. A write of 0 clears the mask which means this bitfield will not reflect the interrupt.
The raw interrupt for receive timeout [RIS.RT] cannot be set unless the mask is set ([RT] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [MIS.RT] and [RIS.RT].

RW

0

5

TX

Transmit interrupt mask. A read returns the current mask for **UART**'s transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.TX]. A write of 0 clears the mask which means [MIS.TX] will not reflect the interrupt.

RW

0

4

RX

Receive interrupt mask. A read returns the current mask for **UART**'s receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.RX]. A write of 0 clears the mask which means [MIS.RX] will not reflect the interrupt.

RW

0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0

1

CTSM

Clear to Send (CTS) modem interrupt mask. A read returns the current mask for **UART**'s clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.CTSM]. A write of 0 clears the mask which means [MIS.CTSM] will not reflect the interrupt.

RW

0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

16

LINSYNCTOE

LIN SYNC field time out interrupt status:
This field returns the raw interrupt state of whether sync field is measurable in UART's LIN mode of operation. This is set when the timer measuring the SYNC field overflows.

RO

0

15

LINBRKTOE

LIN BRK field time out interrupt status:
This field returns the raw interrupt state of whether break field is measurable in UART's LIN mode of operation. This is set when the timer measuring the Break field overflows.

RO

0

14

LINBRK

LIN BRK detected interrupt status:
This field returns the raw interrupt state of whether break field is received/detected in UART's LIN mode of operation.

RO

0

13

RXDMADONE

Rx DMA done interrupt status:
This field returns the raw interrupt state of UART's rx dma done interrupt. RX DMA done flag is set when you receive rx dma done status from dma module.

RO

0

12

TXDMADONE

Tx DMA done interrupt status:
This field returns the raw interrupt state of UART's tx dma done interrupt. TX DMA done flag is set when you receive tx dma done status from dma module.

RO

0

11

EOT

End of Transmission interrupt status:
This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is transmitted.

RO

0

10

OE

Overrun error interrupt status:
This field returns the raw interrupt state of **UART**'s overrun error interrupt. Overrun error occurs if data is received and the receive **FIFO** is full.

RO

0

9

BE

Break error interrupt status:
This field returns the raw interrupt state of **UART**'s break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).

RO

0

8

PE

Parity error interrupt status:
This field returns the raw interrupt state of **UART**'s parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.

RO

0

7

FE

Framing error interrupt status:
This field returns the raw interrupt state of **UART**'s framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1).

RO

0

6

RT

Receive timeout interrupt status:
This field returns the raw interrupt state of **UART**'s receive timeout interrupt. The receive timeout interrupt is asserted when the receive **FIFO** is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the **FIFO** becomes empty through reading all the data, or when a 1 is written to [ICR.RT].
The raw interrupt for receive timeout cannot be set unless the mask is set ([IMSC.RT] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [MIS.RT] and [RT].

RO

0

5

TX

Transmit interrupt status:
This field returns the raw interrupt state of **UART**'s transmit interrupt.
When **FIFO**s are enabled ([LCRH.FEN] = 1), the transmit interrupt is asserted if the number of bytes in transmit **FIFO** is equal to or lower than the programmed trigger level ([IFLS.TXSEL]). The transmit interrupt is cleared by writing data to the transmit **FIFO** until it becomes greater than the trigger level, or by clearing the interrupt through [ICR.TX].
When **FIFO**s are disabled ([LCRH.FEN] = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit **FIFO**, or by clearing the interrupt through [ICR.TX].

RO

0

4

RX

Receive interrupt status:
This field returns the raw interrupt state of **UART**'s receive interrupt.
When **FIFO**s are enabled ([LCRH.FEN] = 1), the receive interrupt is asserted if the receive **FIFO** reaches the programmed trigger
level ([IFLS.RXSEL]). The receive interrupt is cleared by reading data from the receive **FIFO** until it becomes less than the trigger level, or by clearing the interrupt through [ICR.RX].
When **FIFO**s are disabled ([LCRH.FEN] = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by performing a single read of the receive **FIFO**, or by clearing the interrupt through [ICR.RX].

RO

0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x3

1

CTSM

Clear to Send (CTS) modem interrupt status:
This field returns the raw interrupt state of **UART**'s clear to send interrupt.

RO

0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

1

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read as zero, do not modify

RO

0x0000

16

LINSYNCTOE

LIN sync field time out error interrupt status:
This field returns the masked interrupt state of the LIN sync timeout error interrupt which is the AND product of raw interrupt state RIS.LINSYNCTOE and the mask setting IMSC.LINSYNCTOE.

RO

0

15

LINBRKTOE

LIN BRK field time out error interrupt status:
This field returns the masked interrupt state of the LIN BRK timeout error interrupt which is the AND product of raw interrupt state RIS.LINBRKTOE and the mask setting IMSC.LINBRKTOE.

RO

0

14

LINBRK

LIN BRK field detected interrupt status:
This field returns the masked interrupt state of the LIN BRK detected interrupt which is the AND product of raw interrupt state RIS.LINBRK and the mask setting IMSC.LINBRK.

RO

0

13

RXDMADONE

Rx DMA done interrupt status:
This field returns the masked interrupt state of the rx dma done interrupt which is the AND product of raw interrupt state RIS.RXDMADONE and the mask setting IMSC.RXDMADONE.

RO

0

12

TXDMADONE

Tx DMA done interrupt status:
This field returns the masked interrupt state of the tx dma done interrupt which is the AND product of raw interrupt state RIS.TXDMADONE and the mask setting IMSC.TXDMADONE.

RO

0

11

EOT

End of Transmission interrupt status:
This field returns the masked interrupt state of the End of transmission interrupt which is the AND product of raw interrupt state RIS.EOT and the mask setting IMSC.EOT.

RO

0

10

OE

Overrun error masked interrupt status:
This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state [RIS.OE] and the mask setting [IMSC.OE].

RO

0

9

BE

Break error masked interrupt status:
This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state [RIS.BE] and the mask setting [IMSC.BE].

RO

0

8

PE

Parity error masked interrupt status:
This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state [RIS.PE] and the mask setting [IMSC.PE].

RO

0

7

FE

Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state [RIS.FE] and the mask setting [IMSC.FE].

RO

0

6

RT

Receive timeout masked interrupt status:
Returns the masked interrupt state of the receive timeout interrupt.
The raw interrupt for receive timeout cannot be set unless the mask is set ([IMSC.RT] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [RT] and [RIS.RT].

RO

0

5

TX

Transmit masked interrupt status:
This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state [RIS.TX] and the mask setting [IMSC.TX].

RO

0

4

RX

Receive masked interrupt status:
This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state [RIS.RX] and the mask setting [IMSC.RX].

RO

0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

1

CTSM

Clear to Send (CTS) modem masked interrupt status:
This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state [RIS.CTSM] and the mask setting [IMSC.CTSM].

RO

0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0.

RO

0

31:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read as zero, do not modify

WO

0x0000

18:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read as zero, do not modify

WO

0x0

16

LINSYNCTOE

LIN SYNC timeout interrupt clear:
Writing 1 to this field clears the rxdma done interrupt (RIS.LINSYNCTOE). Writing 0 has no effect.

WO

0

15

LINBRKTOE

LIN BRK field timeout interrupt clear:
Writing 1 to this field clears the rxdma done interrupt (RIS.LINBRKTOE). Writing 0 has no effect.

WO

0

14

LINBRK

LIN BRK field detected interrupt clear:
Writing 1 to this field clears the rxdma done interrupt (RIS.LINBRK). Writing 0 has no effect.

WO

0

13

RXDMADONE

Rx DMA Done interrupt clear:
Writing 1 to this field clears the rxdma done interrupt (RIS.RXDMADONE). Writing 0 has no effect.

WO

0

12

TXDMADONE

Tx DMA Done interrupt clear:
Writing 1 to this field clears the txdma done interrupt (RIS.TXDMADONE). Writing 0 has no effect.

WO

0

11

EOT

End of Transmission interrupt clear:
Writing 1 to this field clears the End of Transmission interrupt (RIS.EOT). Writing 0 has no effect.

WO

0

10

OE

Overrun error interrupt clear:
Writing 1 to this field clears the overrun error interrupt ([RIS.OE]). Writing 0 has no effect.

WO

0

9

BE

Break error interrupt clear:
Writing 1 to this field clears the break error interrupt ([RIS.BE]). Writing 0 has no effect.

WO

0

8

PE

Parity error interrupt clear:
Writing 1 to this field clears the parity error interrupt ([RIS.PE]). Writing 0 has no effect.

WO

0

7

FE

Framing error interrupt clear:
Writing 1 to this field clears the framing error interrupt ([RIS.FE]). Writing 0 has no effect.

WO

0

6

RT

Receive timeout interrupt clear:
Writing 1 to this field clears the receive timeout interrupt ([RIS.RT]). Writing 0 has no effect.

WO

0

5

TX

Transmit interrupt clear:
Writing 1 to this field clears the transmit interrupt ([RIS.TX]). Writing 0 has no effect.

WO

0

4

RX

Receive interrupt clear:
Writing 1 to this field clears the receive interrupt ([RIS.RX]). Writing 0 has no effect.

WO

0

3:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0

WO

0x0

1

CTSM

Clear to Send (CTS) modem interrupt clear:
Writing 1 to this field clears the clear to send interrupt ([RIS.CTSM]). Writing 0 has no effect.

WO

0

0

RESERVED0

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0.

WO

0

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read as zero, do not modify.

RW

0x0000 0000

2

DMAONERR

DMA on error. If this bit is set to 1, the **DMA** receive request outputs (for single and burst requests) are disabled when the **UART** error interrupt is asserted (more specifically if any of the error interrupts [RIS.PE], [RIS.BE], [RIS.FE] or [RIS.OE] are asserted).

RW

0

1

TXDMAE

Transmit **DMA** enable. If this bit is set to 1, **DMA** for the transmit **FIFO** is enabled.

RW

0

0

RXDMAE

Receive **DMA** enable. If this bit is set to 1, **DMA** for the receive **FIFO** is enabled.

RW

0

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read as zero, do not modify.

RO

0x0000 0000

2

Reserved

SIR test enable. Setting this bit to 1 enables the receive data path during IrDA transmission (SIR
full-duplex operation is only available when testing). This bit must be set to 1 to enable SIR system
loopback testing, and you must also set the LBE bit to 1 in the Control Register, CTL

RW

0

1

Reserved

Test **FIFO** enable. When this bit it 1, a write to the Test Data Register, [TDR.DATA] writes data into the receive **FIFO**, and a read from the [TDR.DATA] reads data out of the transmit **FIFO**. When this bit is 0, data cannot be read directly from the transmit **FIFO** or written directly to the receive **FIFO** (normal operation).

RW

0

0

Reserved

Integration test enable. When this bit is 1, the **UART** is placed in integration test mode, otherwise it is in normal operation.

RW

0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7

TXDMACLR

Writes to this bit specify the value to be driven on the intra-chip input at PrimeCell PL011 level,
TXDMACLR, in the integration test mode.
Reads return the value of TXDMACLR at the output of the test multiplexor.

RW

0

6

RXDMACLR

Writes to this bit specify the value to be driven on the intra-chip input at PrimeCell PL011 level,
RXDMACLR, in the integration test mode.
Reads return the value of RXDMACLR at the output of the test multiplexor.

RW

0

5:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x3

3

NUARTCTS

Reads return the value of the nUARTCTS primary input at PrimeCell PL011 level.

RO

0

2:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x3

0

UARTRXD

Reads return the value of the **UARTRXD** primary input at PrimeCell PL011 level.

RO

0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15

TXDMASREQ

Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on TXDMASREQ.
Reads return the value of TXDMASREQ at the output of the test multiplexor.

RW

0

14

TXDMABREQ

Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on TXDMABREQ.
Reads return the value of TXDMABREQ at the output of the test multiplexor.

RW

0

13

RXDMASREQ

Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on RXDMASREQ.
Reads return the value of RXDMASREQ at the output of the test multiplexor.

RW

0

12

RXDMABREQ

Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on RXDMABREQ.
Reads return the value of RXDMABREQ at the output of the test multiplexor.

RW

0

11:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00

6

UARTINTR

Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTINTR.
Reads return the value of UARTINTR at the output of the test multiplexor.

RW

0

5:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0

3

NUARTRTS

Writes specify the value to be driven on nUARTRTS, primary output of PrimeCell PL011 IP.

RW

0

2:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0

0

UARTTXD

Writes specify the value to be driven on UARTTXD, primary output of PrimeCell PL011 IP.

RW

0

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

10:0

Reserved

When the [TCR.TESTFIFO] bit is set to 1, data is written into the receive **FIFO** and read out of the transmit **FIFO**.

RW

0x000

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

PARTNUM0

Identifies the peripheral

RO

0x11

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:4

DESIGNER0

Identifies the designer (ARM)

RO

0x1

3:0

PARTNUM1

Identifies the peripheral

RO

0x0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:4

REVISION

UART revision

RO

0x3

3:0

DESIGNER1

Identifies the designer (ARM)

RO

0x4

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

CNF

The configuration option of the UART.

RO

0x00

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

Reserved

This field is hard coded and reads back as 0x0D

RO

0x0D

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

Reserved

This field is hard coded and reads back as 0xF0

RO

0xF0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

Reserved

This field is hard coded and reads back as 0x05

RO

0x05

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

Reserved

This field is hard coded and reads back as 0xB1

RO

0xB1

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

0

EN

This bit enable or disables the bus clock *Uartlin*

RW

0