SYSTIM

This section provides information on the SYSTIM Module Instance within this product. Each of the registers within the Module Instance is described separately below.

This component control the SYSTIM residing in **SVT** Note: This module is only supporting 32 bit ReadWrite access.

SYSTIM Registers Mapping Summary

:SYSTIM Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DESC	RO	32	0x9443 1010	0x0000 0000
IBM	RW	32	0x0000 0000	0x0000 0044
RIS	RO	32	0x0000 0000	0x0000 0048
MIS	RO	32	0x0000 0000	0x0000 004C
ISET	RW	32	0x0000 0000	0x0000 0050
ICLR	RW	32	0x0000 0000	0x0000 0054
IMSET	RW	32	0x0000 0000	0x0000 0058
IMCLR	RW	32	0x0000 0000	0x0000 005C
EMU	RW	32	0x0000 0000	0x0000 0060
DTB	RW	32	0x0000 0000	0x0000 0064
TIME250N	RO	32	0x0000 0000	0x0000 0100
TIME1U	RO	32	0x0000 0000	0x0000 0104
OUT	RO	32	0x0000 0000	0x0000 0108
CH0CFG	RW	32	0x0000 0000	0x0000 010C
CH1CFG	RW	32	0x0000 0000	0x0000 0110
CH0CC	RW	32	0x0000 0000	0x0000 0120
CH1CC	RW	32	0x0000 0000	0x0000 0124
TIMEBIT	RW	32	0x0000 0000	0x0000 0134
KP	RW	32	0x0000 0004	0x0000 0138
KI	RW	32	0x0000 0001	0x0000 013C
STA	RW	32	0x0000 0010	0x0000 0140
ARMSET	RW	32	0x0000 0000	0x0000 0144
ARMCLR	RW	32	0x0000 0000	0x0000 0148
CH0CCSR	RW	32	0x0000 0000	0x0000 014C
CH1CCSR	RW	32	0x0000 0000	0x0000 0150
CLKCFG	RW	32	0x0000 0000	0x0000 1000

SYSTIM Instances Register Mapping Summary

SYSTIM Register Descriptions

:SYSTIM Common Register Descriptions

:SYSTIM:DESC

Address offset	0x0000 0000
Description	This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODID	Module identifier MODID[15:0]. Used to uniquely identify this IP. See comment about derivation below		RO	0x9443
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	STDIPOFF	64 B standard IP MMR block (beginning with aggregated IRQ registers) 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTIDX	If multiple instances of IP exists in SOC, this field can identify the instance number 0-15		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
7:4	MAJREV	Major revision of IP 0-15		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor revision of IP 0-15.		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:SYSTIM:IBM

Address offset	0x0000 0044
Description	INTERRUPT BIT MASK Interrupt Mask. If a bit is cleared, then corresponding interrupt is masked.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Mask Timer Overflow Event in MIS register.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
5:2	Reserved			RO	0x0
1	EVT1	Mask EVENT1 in MIS register.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
0	EVT0	Mask EVENT0 in MIS register.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrupt Mask

:SYSTIM:RIS

Address offset	0x0000 0048
Description	Raw interrupt status reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IBM bit is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Raw interrupt status for Timer Overflow EVENT. This bit is set to 1 when an event is received on Timer Ovreflow EVENT channel.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
5:2	Reserved			RO	0x0
1	EVT1	Raw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
0	EVT0	Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured

:SYSTIM:MIS

Address offset	0x0000 004C
Description	Masked interrupt status. This is an AND of the IBM and RIS registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Mask Interrupt Status Timer Overflow Event in MIS register.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
5:2	Reserved			RO	0x0
1	EVT1	Mask interrupt status for EVENT1		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
0	EVT0	Mask interrupt status for EVENT0		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured

:SYSTIM:ISET

Address offset	0x0000 0050
Description	Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Sets Timer Overflow EVENT in RIS		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
5:2	Reserved			RO	0x0
1	EVT1	Sets channel1 EVENT in RIS		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
0	EVT0	Sets channel0 EVENT in RIS		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt

:SYSTIM:ICLR

Address offset	0x0000 0054
Description	Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Overflow		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
5:2	Reserved			RO	0x0
1	EVT1	Clears EVENT1 in RIS		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
0	EVT0	Clears EVENT0 in RIS		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt

:SYSTIM:IMSET

Address offset	0x0000 0058
Description	Interrupt mask set. Writing a 1 to a bit in IMSET will set the related IBM bit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Sets Timer Overflow Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
5:2	Reserved			RO	0x0
1	EVT1	Sets channel1 Event		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
0	EVT0	Sets channel0 Event		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask

:SYSTIM:IMCLR

Address offset	0x0000 005C
Description	Interrupt mask clear. Writing a 1 to a bit in IMCLR will clear the related IBM bit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	Reserved			RO	0x000 0000
6	OVFL	Clears Timer Overflow Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
5:2	Reserved			RO	0x0
1	EVT1	Clears channel1 Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
0	EVT0	Clears channel0 Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask

:SYSTIM:EMU

Address offset	0x0000 0060
Description	This register can be used by the software developer to control the behavior of the peripheral relative to the CPU Halted input.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved			RO	0x0000 0000
0	HALT	This bit controls peripheral behavior at CPU halt condition.		RW	0
		0	RUN Peripheral ignores the state of the CPU Halted input
		1	STOP Peripheral freezes functionality immediately or at appropriate time when the CPU Halted input is asserted and resumes when it is deasserted

:SYSTIM:DTB

Address offset	0x0000 0064
Description	Digital Test Bus. This register is used to bring out some internal signals of the peripheral on digital test bus (DTB).
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:0	SEL	This bit field is used to select DTB mux digital output signals.		RW	0x0
		0x0	DISABLE DTB output from peripheral is 0x0.
		0x1	GRP1 Selects test group 1
		0x2	GRP2 Selects test group 2
		0x3	GRP3 Selects test group 3
		0x4	GRP4 Selects test group 4
		0x5	GRP5 Selects test group 5
		0x6	GRP6 Selects test group 6
		0x7	GRP7 Selects test group 7
		0x8	GRP8 Selects test group 7
		0x9	GRP9 Selects test group 7
		0xA	GRP10 Selects test group 7
		0xB	GRP11 Selects test group 7
		0xC	GRP12 Selects test group 7
		0xD	GRP13 Selects test group 7
		0xE	GRP14 Selects test group 7
		0xF	GRP15 Selects test group 7

:SYSTIM:TIME250N

Address offset	0x0000 0100
Description	Systimer Counter Value[31:0]. Time with 250ns resolution from systimer
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VAL	Counter Value. This is not writable while the systimer counter is enabled		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest possible value
		Read 0x0000 0000	MINIMUM Smallest value

:SYSTIM:TIME1U

Address offset	0x0000 0104
Description	Systimer Counter Value[33:2]. Time with 1us resolution from systimer
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VAL	Counter Value. This is not writable while the systimer counter is enabled		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest possible value
		Read 0x0000 0000	MINIMUM Smallest value

:SYSTIM:OUT

Address offset	0x0000 0108
Description	SYSTIMER'S Channel Output Event Values
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	Reserved			RO	0x0000 0000
1	OUT1	Output Value of channel 1.		RO	0
		Read 0	CLR Event did not occur.
		Read 1	SET Event occured
0	OUT0	Output Value of channel 0.		RO	0
		Read 0	CLR Event did not occur.
		Read 1	SET Event occured

:SYSTIM:CH0CFG

Address offset	0x0000 010C
Description	SYSTIMER channel 0 configuration
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	Reserved			RO	0x000 0000
4	RES	This bit decides the RESOLUTION of the channel that will be used.		RW	0
		0	US Channel Works in Timer's 1us Resolution.
		1	NS Channel Works in Timer's 250ns resolution
3	REARM	When Rearm is enabled the channel remains in continuous capture mode. Otherwise it'll be in One shot capture mode. Rearm is only valid for capture mode.		RW	0
		0	NS Re Arm is disabled
		1	EN Re arm is enabled
2:1	INP	Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function.		RW	0x0
		0x0	RISE Capture on rising edge
		0x1	FALL Capture on Falling Edge
		0x2	BOTH Capture on both Edge
0	MODE	Decides the channel mode.		RW	0
		0	DIS Channel is disabled
		1	CAPT Channel is in capture mode

:SYSTIM:CH1CFG

Address offset	0x0000 0110
Description	SYSTIMER channel 1 configuration
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3	REARM	When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in One shot capture mode. Rearm is only valid for capture mode.		RW	0
		0	NS Re Arm is disabled
		1	EN Re arm is enabled
2:1	INP	Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function		RW	0x0
		0x0	RISE Capture on rising edge
		0x1	FALL Capture on Falling Edge
		0x2	BOTH Capture on both Edge
0	MODE	Decides the channel mode.		RW	0
		0	DIS Channel is disabled
		1	CAPT Channel is in capture mode

:SYSTIM:CH0CC

Address offset	0x0000 0120
Description	System Timer Channel 0 Capture/Compare Register. This Register when written with any compare value will arm the channel to work in compare mode.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Capture/compare value		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Highest possible value
		0x0000 0000	MINIMUM Smallest value

:SYSTIM:CH1CC

Address offset	0x0000 0124
Description	System Timer Channel 1 Capture/Compare Register. This Register when written with any compare value will arm the channel to work in compare mode.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Capture/compare value		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Highest possible value
		0x0000 0000	MINIMUM Smallest value

:SYSTIM:TIMEBIT

Address offset	0x0000 0134
Description	This Register will be used to specify which TIME bit is required by LGPT to be forwarded from SYSTIMER.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved			RO	0x0000
15:0	VAL	The corresponding bit will have value '1' rest should be '0'. If more than one bit is asserted, output is "or" of all the bits.		RW	0x0000
		0x0000	NOBIT No bit is forwarded to the event fabric.
		0x0001	BIT2 Bit2 is forwarded to the event fabric.
		0x0002	BIT3 Bit3 is forwarded to the event fabric.
		0x0004	BIT4 Bit4 is forwarded to the event fabric.
		0x0008	BIT5 Bit5 is forwarded to the event fabric.
		0x0010	BIT6 Bit6 is forwarded to the event fabric.
		0x0020	BIT7 Bit7 is forwarded to the event fabric.
		0x0040	BIT8 Bit8 is forwarded to the event fabric.
		0x0080	BIT9 Bit9 is forwarded to the event fabric.
		0x0100	BIT10 Bit10 is forwarded to the event fabric.
		0x0200	BIT11 Bit11 is forwarded to the event fabric.
		0x0400	BIT12 Bit12 is forwarded to the event fabric.
		0x0800	BIT13 Bit13 is forwarded to the event fabric.
		0x1000	BIT14 Bit14 is forwarded to the event fabric.
		0x2000	BIT15 Bit15 is forwarded to the event fabric.
		0x4000	BIT16 Bit16 is forwarded to the event fabric.
		0x8000	BIT17 Bit17 is forwarded to the event fabric.

:SYSTIM:KP

Address offset	0x0000 0138
Description	PI filter's Proportional Gain Value
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:0	VAL	Proportional Error is left shifted by this value.		RW	0x4
		0x0	MINIMUM Smallest value
		0xF	MAXIMUM Highest possible value

:SYSTIM:KI

Address offset	0x0000 013C
Description	PI filter's Accumulator's Gain Value
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved			RO	0x000 0000
3:0	VAL	Accumulated Error is left shifted by this value.		RW	0x1
		0x0	MINIMUM Smallest value
		0xF	MAXIMUM Highest possible value

:SYSTIM:STA

Address offset	0x0000 0140
Description	STA This is the system timer status register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	Reserved			RO	0x000 0000
4	SYNCUP	This bit indicates the status of resyncup of systimer with RTC. The bitfield has a reset value of '1' , as out of reset the systimer syncs up with RTC, after the first_synced_lftick occurs the SYNCUP bit goes to zero.		RO	1
		Read 0	CLR SYNC UP with RTC is not happening
		Read 1	SET Any write to STA register, triggers the SYNCUP with RTC and this bit is set.
3:1	Reserved			RO	0x0
0	VAL	This bit indicates if the system time is initialized and running.		RO	0
		Read 0	STOP system timer is not running.
		Read 1	RUN system timer is running

:SYSTIM:ARMSET

Address offset	0x0000 0144
Description	ARMSET on read gives out the status of the 2 channels 1. Channel state UNARMED returns 0 2. Channel state CAPTURE or COMPARE returns 1 A write to ARMSET has for each channel the following effect: 1. If ARMSTA[x]==0 -> no effect 2. If ARMSTA[x]==1 and channel x is in CAPTURE state then no effect on the channel 3. Else Set channel in COMPARE mode using existing CHxVAL value
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved			RO	0x0000 0000
1	CH1	Arming Channel 1 for either compare or capture operation.		RW	0
		0	NOEFFECT No effect on the channel
		1	SET if channel 1 is in CAPTURE state then no effect on the channel Else ; Set channel in COMPARE mode using existing CH1CC value
0	CH0	Arming Channel 0 for either compare or capture operation.		RW	0
		0	NOEFFECT No effect on the channel
		1	SET if channel 0 is in CAPTURE state then no effect on the channel 3. Else ; Set channel in COMPARE mode using existing CH0CC value

:SYSTIM:ARMCLR

Address offset	0x0000 0148
Description	ARMCLR on read gives out the status of the 2 channels 1. Channel state UNARMED returns 0 2. Channel state CAPTURE or COMPARE returns 1 A write to ARMCLR has for each channel the following effect: 1. If ARMCLR[x]==0 no effect 2. Else Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved			RO	0x0000 0000
1	CH1	Disarming Channel 1		RW	0
		0	NOEFFECT No effect on the channel
		1	CLR Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
0	CH0	Disarming Channel 0		RW	0
		0	NOEFFECT No effect on the channel
		1	CLR Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle

:SYSTIM:CH0CCSR

Address offset	0x0000 014C
Description	Save/restore alias registers Channel 0. i. A read to CH0CCSR behaves exactly as a read to CH0CC. A write to CH0CCSR sets CH0CC value of register without affecting channel state or configuration
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Capture/compare value		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Highest possible value
		0x0000 0000	MINIMUM Smallest value

:SYSTIM:CH1CCSR

Address offset	0x0000 0150
Description	Save/restore alias registers Channel 1. i. A read to CH1CCSR behaves exactly as a read to CH1CC. A write to CH1CCSR sets CH1CC value of register without affecting channel state or configuration.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Capture/compare value		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Highest possible value
		0x0000 0000	MINIMUM Smallest value

:SYSTIM:CLKCFG

Address offset	0x0000 1000
Description	CLOCK CONFIG
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved			RO	0x0000 0000
0	CLKCFG_STA	ENABLE '1' - enable systimer clk '0' - disable systimer clk		RW	0
		4294967295	MAXIMUM Highest possible value
		0	MINIMUM Smallest value