This section provides information on the SYSRESOURCES Module Instance within this product. Each of the registers within the Module Instance is described separately below.
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
|
Address offset |
0x0000 0008 |
||
|
Description |
|||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
||
|
31:1 |
Reserved |
|
RO |
0x0000 0000 |
||
|
0 |
MEM_SYSTIM_ENCLK |
'1' - enable the reqeusets for the systim clk |
RW |
0 |
||
|
Address offset |
0x0000 0400 |
||
|
Description |
|||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
||
|
31:7 |
Reserved |
|
RO |
0x000 0000 |
||
|
6:4 |
MEMSS_BUS_FAULT_STATUS_MASKED |
'1' - Mask |
RO |
0x0 |
||
|
3 |
MEM_MEMSS_BUS_FAULT_MASK |
'1' - Mask |
RW |
0 |
||
|
2:0 |
MEM_STRV_CNTR_VAL |
HOST to config how long writing to mailbox can be delayed |
RW |
0x0 |
||
|
Address offset |
0x0000 0404 |
||
|
Description |
|||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
||
|
31:3 |
Reserved |
|
RO |
0x0000 0000 |
||
|
2:0 |
MEMSS_BUS_FAULT_STATUS_RAW_RDCL |
HOST to config how long writing to mailbox can be delayed |
RO |
0x0 |
||