SPI

This section provides information on the SPI Module Instance within this product. Each of the registers within the Module Instance is described separately below.

Serial Peripheral Interface (SPI) module with peripheral and controller capabilities. INTERNAL_NOTE: Implementation spec: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=LPRF&title=LOKI+SPI+-+Implementation+Specification Functional spec: https://confluence.itg.ti.com/display/LPRF/Loki+-+SPI+Functional+Specification?src=contextnavpagetreemode

SPI Registers Mapping Summary

:SPI Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DESC	RO	32	0x604D 1010	0x0000 0000
IMASK	RW	32	0x0000 0000	0x0000 0044
RIS	RO	32	0x0000 0000	0x0000 0048
MIS	RO	32	0x0000 0000	0x0000 004C
ISET	WO	32	0x0000 0000	0x0000 0050
ICLR	WO	32	0x0000 0000	0x0000 0054
IMSET	WO	32	0x0000 0000	0x0000 0058
IMCLR	WO	32	0x0000 0000	0x0000 005C
EMU	RW	32	0x0000 0000	0x0000 0060
CTL0	RW	32	0x0000 0000	0x0000 0100
CTL1	RW	32	0x0000 0004	0x0000 0104
CLKCFG0	RW	32	0x0000 0000	0x0000 0108
CLKCFG1	RW	32	0x0000 0000	0x0000 010C
IFLS	RW	32	0x0000 0202	0x0000 0110
DMACR	RW	32	0x0000 0000	0x0000 0114
RXCRC	RW	32	0x0000 0000	0x0000 0118
TXCRC	RW	32	0x0000 0000	0x0000 011C
MMR_TXFHDR32	WO	32	0x0000 0000	0x0000 0120
MMR_TXFHDR24	WO	32	0x0000 0000	0x0000 0124
MMR_TXFHDR16	WO	32	0x0000 0000	0x0000 0128
MMR_TXFHDR8	WO	32	0x0000 0000	0x0000 012C
MMR_TXFHDRC	RW	32	0x0000 0000	0x0000 0130
RXDATA	RO	32	0x0000 0000	0x0000 0140
TXDATA	RW	32	0x0000 0000	0x0000 0150
STAT	RW	32	0x0000 000F	0x0000 0160
CLK_EN_REG	RW	32	0x0000 0000	0x0000 1000

SPI Instances Register Mapping Summary

SPI Register Descriptions

:SPI Common Register Descriptions

:SPI:DESC

Address offset	0x0000 0000
Description	Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	MODID	Module identifier used to uniquely identify this IP.	RO	0x604D
15:12	STDIPOFF	Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)	RO	0x1
11:8	INSTIDX	IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).	RO	0x0
7:4	MAJREV	Major revision of IP (0-15).	RO	0x1
3:0	MINREV	Minor revision of IP (0-15).	RO	0x0

:SPI:IMASK

Address offset	0x0000 0044
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.] to [MIS.] when the corresponding bit-fields are set to 1.
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	DMA Done TX event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
7	DMARX	DMA Done RX event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
6	IDLE	SPI Idle event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
5	TXEMPTY	Transmit FIFO Empty event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
4	TX	Transmit FIFO event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
3	RX	Receive FIFO event.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrupt Mask
2	RTOUT	SPI Receive Time-Out event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
1	PER	Parity error event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask
0	RXOVF	RXFIFO overflow event mask.		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Set Interrrupt Mask

:SPI:RIS

Address offset	0x0000 0048
Description	Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	DMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
7	DMARX	DMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
6	IDLE	SPI has completed transfers and moved to IDLE mode. This bit is set when [STA.BUSY] goes low.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
5	TXEMPTY	Transmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
4	TX	Transmit FIFO event.This interrupt is set if the selected Transmit FIFO level has been reached.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
3	RX	Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
2	RTOUT	SPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by [CTL1.RTOUT] value. This is applicable only in peripheral mode.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
1	PER	Parity error event. This bit is set if a Parity error has been detected		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
0	RXOVF	RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred

:SPI:MIS

Address offset	0x0000 004C
Description	Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.] and [RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	Masked DMA Done event for TX.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
7	DMARX	Masked DMA Done event for RX.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
6	IDLE	Masked SPI IDLE event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
5	TXEMPTY	Masked Transmit FIFO Empty event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
4	TX	Masked Transmit FIFO event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
3	RX	Masked receive FIFO event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
2	RTOUT	Masked SPI Receive Time-Out event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
1	PER	Masked Parity error event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred
0	RXOVF	Masked RXFIFO overflow event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occurred

:SPI:ISET

Address offset	0x0000 0050
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	Set DMA Done event for TX.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
7	DMARX	Set DMA Done event for RX.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
6	IDLE	Set SPI IDLE event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
5	TXEMPTY	Set Transmit FIFO Empty event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
4	TX	Set Transmit FIFO event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
3	RX	Set Receive FIFO event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
2	RTOUT	Set SPI Receive Time-Out Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrrupt Mask
1	PER	Set Parity error event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt
0	RXOVF	Set RXFIFO overflow event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set Interrupt

:SPI:ICLR

Address offset	0x0000 0054
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	Clear DMA Done event for TX.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
7	DMARX	Clear DMA Done event for RX.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
6	IDLE	Clear SPI IDLE event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
5	TXEMPTY	Clear Transmit FIFO Empty event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
4	TX	Clear Transmit FIFO event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
3	RX	Clear Receive FIFO event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
2	RTOUT	Clear SPI Receive Time-Out Event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Set Interrrupt Mask
1	PER	Clear Parity error event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt
0	RXOVF	Clear RXFIFO overflow event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear Interrupt

:SPI:IMSET

Address offset	0x0000 0058
Description	Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	Set DMA Done for TX event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
7	DMARX	Set DMA Done for RX event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
6	IDLE	Set SPI IDLE event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
5	TXEMPTY	Set Transmit FIFO Empty event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
4	TX	Set Transmit FIFO event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
3	RX	Set Receive FIFO event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
2	RTOUT	Set SPI Receive Time-Out event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
1	PER	Set Parity error event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask
0	RXOVF	Set RXFIFO overflow event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt mask

:SPI:IMCLR

Address offset	0x0000 005C
Description	Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
Type	WO

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	DMATX	Clear DMA Done for TX event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
7	DMARX	Clear DMA Done for RX event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
6	IDLE	Clear SPI IDLE event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
5	TXEMPTY	Clear Transmit FIFO Empty event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
4	TX	Clear Transmit FIFO event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
3	RX	Clear Receive FIFO event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
2	RTOUT	Clear SPI Receive Time-Out event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
1	PER	Clear Parity error event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask
0	RXOVF	Clear RXFIFO overflow event mask		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Clear interrupt mask

:SPI:EMU

Address offset	0x0000 0060
Description	Emulation control register. This register controls the behavior of the IP related to core halted input.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	HALT	Halt control		RW	0
		0	RUN Free run option. The IP ignores the state of the core halted input.
		1	STOP Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary (end of word boundary, based on DSS configuration) from where it can resume without corruption.

:SPI:CTL0

Address offset	0x0000 0100
Description	SPI control register 0
Type	RW

Bits	Field Name	Description		Type	Reset
31:20	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
19:18	CSSEL	CS select for Multi SPI support 00 - CS0 01 - CS1 10 - CS2 11 - CS3		RW	0x0
		0x0	CS0 Select CS0
		0x1	CS1 Select CS1
		0x2	CS2 Select CS2
		0x3	CS3 Select CS3
17	MISO_IDLEVAL	The Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.		RW	0
		0	IDLE_ZERO POCI output idle value of '0'
		1	IDLE_ONE POCI outputs idle value of '1'
16	GPCRCEN	General purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled ([CTL1.EN] = 0). This bit must be 0 when SPI is enabled.		RW	0
		0	DISABLE Transmit side CRC unit is not available for general purpose software use
		1	ENABLE Transmit side CRC unit is available for general purpose software use
15	CRCPOLY	CRC polynomial selection.		RW	0
		0	_8BIT Selects 8-bit CCITT CRC polynomial
		1	_16BIT Selects 16-bit CCITT CRC polynomial
14	AUTO_CRC	Auto insert CRC		RW	0
		0	DISABLE Do not insert CRC into TXFIFO upon TXFIFO underflow
		1	ENABLE Insert CRC into TXFIFO upon TXFIFO underflow
13	CRC_END	CRC16 Endianness		RW	0
		0	CRC_END_MSB Auto-insertion of CRC16 is most-significant byte first
		1	CRC_END_LSB Auto-insertion of CRC16 is least-significant byte first
12	CSCLR	Clear shift register counter on CS inactive. This bit is relevant only in the peripheral mode, when [CTL1.MS]=0.		RW	0
		0	DISABLE Disable automatic clear of shift register when CS goes inactive.
		1	ENABLE Enable automatic clear of shift register when CS goes inactive.
11	FIFORST	This bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.		RW	0
		0	RST_DONE FIFO pointers reset completed when 0 is read
		1	RST_TRIG Trigger FIFO pointers reset when written to 1.
10	HWCSN	Hardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in - a. CS is de-asserted b. All data bytes are transmitted c. CS is asserted		RW	0
		0	DISABLE HWCS Disable
		1	ENABLE HWCS Enable
9	SPH	CLKOUT phase (Motorola SPI frame format only). This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.		RW	0
		0	FIRST Data is captured on the first clock edge transition.
		1	SECOND Data is captured on the second clock edge transition.
8	SPO	CLKOUT polarity (Motorola SPI frame format only).		RW	0
		0	LOW SPI produces a steady state LOW value on the CLKOUT
		1	HIGH SPI produces a steady state HIGH value on the CLKOUT
7	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6:5	FRF	Frame format select		RW	0x0
		0x0	MOTOROLA_3WIRE Motorola SPI frame format (3 wire mode)
		0x1	MOTOROLA_4WIRE Motorola SPI frame format (4 wire mode)
		0x2	TI_SYNC TI synchronous serial frame format
		0x3	MICROWIRE National Microwire frame format
4	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
3:0	DSS	Data size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.		RW	0x0
		0x3	BITS_4 4-bits data size
		0x4	BITS_5 5-bits data size
		0x5	BITS_6 6-bits data size
		0x6	BITS_7 7-bits data size
		0x7	BITS_8 8-bits data size
		0x8	BITS_9 9-bits data size
		0x9	BITS_10 10-bits data size
		0xA	BITS_11 11-bits data size
		0xB	BITS_12 12-bits data size
		0xC	BITS_13 13-bits data size
		0xD	BITS_14 14-bits data size
		0xE	BITS_15 15-bits data size
		0xF	BITS_16 16-bits data size

:SPI:CTL1

Address offset	0x0000 0104
Description	SPI control register 1
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29:24	RTOUT	Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag [RIS.RTOUT] is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function.		RW	0x00
23:16	REPTX	Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the provided value. The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated provided value number of times, so the data will be transferred x+1 times in total. The behavior would be as if the data were be written into the TX FIFO as many times as defined by the value here additionally. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.		RW	0x00
		0x00	DISABLE REPTX disable
15:12	CDMODE	Command Data Mode. This bit field value determines the behavior of C/D or CS signal when [CDEN] = 1. CS pin held low indicates command phase and CS pin held high indicates data phase. When [CDMODE] = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode). When [CDMODE] = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode). When [CDMODE] = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by [CDMODE] value for the command phase and held high for the remaining transfers in the data phase (automatic mode). When [CDMODE] is set to value 0x1 to 0xE, reading [CDMODE] during operation indicates the remaining bytes to be transferred in the command phase.		RW	0x0
		0x0	DATA Manual mode: Data
		0xF	COMMAND Manual mode: Command
11	CDEN	Command/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers ([CTL0.DSS] = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.		RW	0
		0	DISABLE C/D Mode Disable
		1	ENABLE C/D Mode Enable
10:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	PBS	Parity bit select		RW	0
		0	BIT0 Bit 0 is used for Parity
		1	BIT1 Bit 1 is used for Parity, Bit 0 is ignored
6	PES	Even parity select.		RW	0
		0	ODD Odd Parity mode
		1	EVEN Even Parity mode
5	PEN	Parity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits. In case of parity mismatch the parity error flag [RIS.PER] will be set. This feature is available only in SPI controller mode.		RW	0
		0	DISABLE Disable Parity function
		1	ENABLE Enable Parity function
4	MSB	MSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.		RW	0
		0	LSB LSB first
		1	MSB MSB first
3	SOD	Peripheral data output disable. This bit is relevant only in the peripheral mode, [MS]=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.		RW	0
		0	DISABLE SPI can drive the POCI output in peripheral mode.
		1	ENABLE SPI cannot drive the POCI output in peripheral mode.
2	MS	Controller or peripheral mode select. This bit can be modified only when SPI is disabled, [CTL1.EN]=0.		RW	1
		0	PERIPHERAL Select Peripheral mode
		1	CONTROLLER Select Controller mode
1	LBM	Loop back mode control		RW	0
		0	DISABLE Disable loopback mode. Normal serial port operation enabled.
		1	ENABLE Enable loopback mode. Output of transmit serial shifter is connected to input of receive serial shifter internally.
0	ENABLE	SPI enable.		RW	0
		0	DISABLE SPI is disabled
		1	ENABLE SPI Enabled and released for operation.

:SPI:CLKCFG0

Address offset	0x0000 0108
Description	Clock configuration register 0. This register is used to configure the clock prescaler.
Type	RW

Bits	Field Name	Description		Type	Reset
31:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
2:0	PRESC	Prescaler configuration		RW	0x0
		0x0	DIV_BY_1 Do not divide clock source
		0x1	DIV_BY_2 Divide clock source by 2
		0x2	DIV_BY_3 Divide clock source by 3
		0x3	DIV_BY_4 Divide clock source by 4
		0x4	DIV_BY_5 Divide clock source by 5
		0x5	DIV_BY_6 Divide clock source by 6
		0x6	DIV_BY_7 Divide clock source by 7
		0x7	DIV_BY_8 Divide clock source by 8

:SPI:CLKCFG1

Address offset	0x0000 010C
Description	Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode.
Type	RW

Bits	Field Name	Description	Type	Reset
31:20	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x000
19:16	DSAMPLE	Delayed sampling. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice.	RW	0x0
15:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00
9:0	SCR	Serial clock divider. This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value can be from 0 to 1023.	RW	0x000

:SPI:IFLS

Address offset	0x0000 0110
Description	Interrupt FIFO level select register. This register can be used to define the levels at which the [RIS.TX], [RIS.RX] flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the [IFLS.TXSEL] and [IFLS.RXSEL] bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
Type	RW

Bits	Field Name	Description		Type	Reset
31:11	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
10:8	RXSEL	Receive FIFO Level Select. The trigger points for the receive interrupt are as follows:		RW	0x2
		0x0	LVL_OFF Reserved
		0x1	LVL_1_4 RX FIFO >= 1/4 full
		0x2	LVL_1_2 RX FIFO >= 1/2 full (default)
		0x3	LVL_3_4 RX FIFO >= 3/4 full
		0x4	LVL_RES4 Reserved
		0x5	LVL_FULL RX FIFO is full
		0x6	LVL_RES6 Reserved
		0x7	LEVEL_1 Trigger when RX FIFO contains >= 1 byte
7:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
2:0	TXSEL	Transmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:		RW	0x2
		0x0	LVL_OFF Reserved
		0x1	LVL_3_4 TX FIFO <= 3/4 empty
		0x2	LVL_1_2 TX FIFO <= 1/2 empty (default)
		0x3	LVL_1_4 TX FIFO <= 1/4 empty
		0x4	LVL_RES4 Reserved
		0x5	LVL_EMPTY TX FIFO is empty
		0x6	LVL_RES6 Reserved
		0x7	LEVEL_1 Trigger when TX FIFO has >= 1 byte free

:SPI:DMACR

Address offset	0x0000 0114
Description	DMA Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
8	TXEN	Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.		RW	0
		0	DISABLE Disable TX DMA
		1	ENABLE Enable TX DMA
7:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	RXEN	Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.		RW	0
		0	DISABLE Disable RX DMA
		1	ENABLE Enable RX DMA

:SPI:RXCRC

Address offset	0x0000 0118
Description	Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when [CTL0.CRCPOLY] = 0 and 0xFFFF when [CTL0.CRCPOLY] = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when [CTL0.CRCPOLY] = 0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	DATA	CRC value	RW	0x0000

:SPI:TXCRC

Address offset	0x0000 011C
Description	Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when [CTL0.CRCPOLY] = 0 and 0xFFFF when [CTL0.CRCPOLY] = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when [CTL0.CRCPOLY] = 0.
Type	RW

Bits	Field Name	Description		Type	Reset
31	AUTO_CRC_INSERTED_STAT	Status to indicate if Auto CRC has been inserted into TXFIFO. This is applicable only if [CTL0.AUTOCRC] enable bit is set		RO	0
		Read 0	NOT_INSERTED Auto CRC not yet inserted
		Read 1	INSERTED Auto CRC inserted
30:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	DATA	CRC value		RW	0x0000

:SPI:MMR_TXFHDR32

Address offset	0x0000 0120
Description	Header update reigster for 32 bits of header data.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	TXFHDR32	This field can be used to write four bytes of header data			WO	0x0000 0000

:SPI:MMR_TXFHDR24

Address offset	0x0000 0124
Description	Header update reigster for 24 bits of header data.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	TXFHDR24	This field can be used to write three bytes of header data			WO	0x0000 0000

:SPI:MMR_TXFHDR16

Address offset	0x0000 0128
Description	Header update reigster for 16 bits of data.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	TXFHDR16	This field can be used to write two bytes of header data			WO	0x0000 0000

:SPI:MMR_TXFHDR8

Address offset	0x0000 012C
Description	Header update reigster for 8 bits of header data.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	TXFHDR8	This field can be used to write one byte of header data			WO	0x0000 0000

:SPI:MMR_TXFHDRC

Address offset	0x0000 0130
Description	Atomic Header control register
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	CS_GATE	Chip Select Gating control register. If this bit is set header update register writes are blocked when chip select (CS) is active low, and [HDRIGN] bit is set. This bit resets to 0.		RW	0
		0	UNBLOCKED The first header update register write is not blocked based on CS active status (low). If no header update occurred when CS was high (inactive), the first header update is allowed when CS is low (active), and the HDRCMT bit is set. The use case is for the external controller to ensure that the SCLK is not driven during this header update. If the header is already updated when CS is high and inactive, HDRCMT is set immediately when CS drops to active low state, and header writes when CS is low are ignored even if this UNBLK bit is set.
		1	BLOCKED Header update register writes are blocked when CS is active (low)
2	HEADER_COMMITTED	Header Committed field. This bit is set when the [HDREN] bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.		RW	0
		0	CLEAR Header update is not committed
		1	SET Header update is committed
1	HEADER_IGNORED	Header Ignored field. When [CSGATE] is set to BLK, this bit is set when the last Header update register [TXFHDRn.*] is written when CS is low or [HDRCMT] is already set. When [CSGATE] is set to UNBLK, this bit is set only when the header update register is written when [HDRCMT] is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.		RW	0
		1	CLEAR Header update is not ignored
		1	SET Header update is ignored
0	HEADER_ENABLE	Header enable field. When [CSGATE] is set to BLK, this bit has to be set by software to enable this feature. When [CSGATE] is set to UNBLK, this field is set automatically whenever a write to header update registers occurs [TXFHDRn.*]		RW	0
		0	DISABLE Atomic header update feature disable
		1	ENABLE Atomic header update feature enable

:SPI:RXDATA

Address offset	0x0000 0140
Description	RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	DATA	Received Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer. Received data less than 16 bits is automatically right-justified in the receive buffer.	RO	0x0000

:SPI:TXDATA

Address offset	0x0000 0150
Description	TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last written value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	DATA	Transmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed. When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.	RW	0x0000

:SPI:STAT

Address offset	0x0000 0160
Description	Status Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:14	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
13:8	TXFIFO_FILL_LEVEL	Indicates how many locations of TXFIFO are currently filled with data		RO	0x00
7	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	SLV_TRANS_DONE	Transmit done. Indicates whether the last bit left the Shift register after a transmission		RW	0
		0	TRANSMIT_INPROGRESS Last bit has not yet left the Shift register, and the transmission is ongoing.
		1	TRANSMIT_DONE Last bit has been shifted out, and the transmission is done
5	CSD	Detection of CS deassertion in the middle of a word transmission results in this error being set. This feature is only available in the peripheral mode.		RW	0
		0	NO_ERROR No CS posedge is detected before the entire word has been transmitted.
		1	ERROR An error is generated when CS posedge (deassertion) is detected before the entire word is transmitted.
4	BUSY	SPI Busy status		RO	0
		Read 0	IDLE SPI is in idle mode.
		Read 1	ACTIVE SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3	RNF	Receive FIFO not full status.		RO	1
		Read 0	FULL Receive FIFO is full.
		Read 1	NOT_FULL Receive FIFO is not full.
2	RFE	Receive FIFO empty status.		RO	1
		Read 0	NOT_EMPTY Receive FIFO is not empty.
		Read 1	EMPTY Receive FIFO is empty.
1	TNF	Transmit FIFO not full status.		RO	1
		Read 0	FULL Transmit FIFO is full.
		Read 1	NOT_FULL Transmit FIFO is not full.
0	TFE	Transmit FIFO empty status.		RO	1
		Read 0	NOT_EMPTY Transmit FIFO is not empty.
		Read 1	EMPTY Transmit FIFO is empty.

:SPI:CLK_EN_REG

Address offset	0x0000 1000
Description	Clock Enable Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	MEM_CLK_EN	SPI main clock Enable	RW	0