SDMMC

This section provides information on the SDMMC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SDMMC Registers Mapping Summary

:SDMMC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
SYSCFG	RW	32	0x0000 2015	0x0000 0110
SYSSTA	RO	32	0x0000 0000	0x0000 0114
STA	RW	32	0x0000 0000	0x0000 0124
SYSTEST	RW	32	0x0000 0000	0x0000 0128
CON	RW	32	0x0000 0600	0x0000 012C
NUMDEL	RW	32	0x0000 0000	0x0000 0130
SDMASA	RW	32	0x0000 0000	0x0000 0200
BLK	RW	32	0x0000 0000	0x0000 0204
ARG	RW	32	0x0000 0000	0x0000 0208
CMD	RW	32	0x0000 0000	0x0000 020C
RSP10	RO	32	0x0000 0000	0x0000 0210
RSP32	RO	32	0x0000 0000	0x0000 0214
RSP54	RO	32	0x0000 0000	0x0000 0218
RSP76	RO	32	0x0000 0000	0x0000 021C
VAL	RW	32	0x0000 0000	0x0000 0220
PSTATE	RO	32	0x0000 0000	0x0000 0224
HCTL	RW	32	0x0000 0000	0x0000 0228
SYSCTL	RW	32	0x0000 0000	0x0000 022C
STAT	RW	32	0x0000 0000	0x0000 0230
IE	RW	32	0x0000 0000	0x0000 0234
ISE	RW	32	0x0000 0000	0x0000 0238
AC12	RW	32	0x0000 0000	0x0000 023C
CAPA	RW	32	0x20E1 0080	0x0000 0240
CURCAPA	RW	32	0x0000 0000	0x0000 0248
FE	RW	32	0x0000 0000	0x0000 0250
REV	RO	32	0x3302 0000	0x0000 02FC
TPSEL	RW	32	0x0000 0000	0x0000 1040
DMAMODE	RW	32	0x0000 0001	0x0000 1048
DMAIND	RW	32	0x0000 0001	0x0000 1050
CLKSEL	RW	32	0x0000 0000	0x0000 1054
EVTMODE	RW	32	0x0000 0001	0x0000 10E0
DESC	RO	32	0x2111 0000	0x0000 10FC
SDMMCSTAT	RO	32	0xXXXX XXXX	0x0000 1100
BUFIF	RW	32	0x0000 0000	0x0000 1110
CLKCFG	RW	32	0x0000 0000	0x0000 4000

SDMMC Instances Register Mapping Summary

SDMMC Register Descriptions

:SDMMC Common Register Descriptions

:SDMMC:SYSCFG

Address offset	0x0000 0110
Description	This register allows controlling various parameters of the OCP interface.
Type	RW

Bits	Field Name	Description		Type	Reset
31:14	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
13:12	RESERVED	Host interface power Management, standby/wait control. Note: these bit fields are not used, since the IP not support MDMA.		RW	0x2
11:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
9:8	CLKIDLECFG	Clock idle policy register, Clocks activity during wake up mode period. Bit8: OCP interface clock Bit9: Functional clock		RW	0x0
		0x0	OFF Interface and Functional clock may be switched off
		0x1	INT Interface clock is maintained. Functional clock may be switched-off.
		0x2	FUNC Functional clock is maintained. Interface clock may be switched-off.
		0x3	ALL Interface and Functional clocks are maintained.
7:5	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
4:3	SIDLEMODE	Power management We are using this register only to change CON.DVAL, else these bit fields are not used, since Idle request is not supported.		RW	0x2
2	WUEN	This field controls the wakeup capability of the module.		RW	1
		0	OFF Wakeup capability is disabled
		1	EN Wakeup capability is enabled
1	SOFTRST	Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0.		RW	0
0	AUTOIDLE	Internal Clock gating strategy 0: Clocks are free-running 1: Automatic clock gating strategy is applied, based on the OCP and MMC interface activity		RW	1
		0	OFF Clocks are free-running
		1	ON Automatic clock gating strategy is applied

:SDMMC:SYSSTA

Address offset	0x0000 0114
Description	This register provides status information about the module excluding the interrupt status information.
Type	RO

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	RSTDONE	Internal Reset Monitoring Note: The debounce clock , the interface clock and the functional clock must be provided to the SDMMC host controller to allow the internal reset monitoring.		RO	0
		Read 0	ONGOING Internal module reset is on-going
		Read 1	COMPLETE Reset completed

:SDMMC:STA

Address offset	0x0000 0124
Description	Card Status Response Error Detection This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit SD_STA[i] is set to 1, if the corresponding bit at the same position in the response RSP10[i] is set to 1, the host controller indicates a card error (STAT.CERR bit) interrupt status to avoid the host driver reading the response register (RSP10). No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (RSP76) for possible card errors.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	STA	Card status response error		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Maximum value
		0x0000 0000	MINIMUM Minimum value

:SDMMC:SYSTEST

Address offset	0x0000 0128
Description	SDMMC System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. In SYSTEST mode, a write into CMD register will not start a transfer.
Type	RW

Bits	Field Name	Description		Type	Reset
31:17	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
16	OBI	Out-Of-Band Interrupt (OBI) data value Note: Out-Of-Band Interrupt (OBI) is not supported.		RO	0
15	SDCD	Card detect input signal (SDCD) data value		RO	0
		Read 0	LOW The card detect pin is driven low
		Read 1	HIGH The card detect pin is driven high
14	SDWP	Write protect input signal (SDWP) data value		RO	0
		Read 0	LOW The write protect pin SDWP is driven low
		Read 1	HIGH The write protect pin SDWP is driven high
13	WAKD	Wake request output signal data value		RW	0
		0	LOW The pin SWAKEUP is driven low
		1	HIGH The pin SWAKEUP is driven high
12	SSB	Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (STAT).		RW	0
		0	LOW Clears this SSB bit field. Writing 0 does not clear already set status bits
		1	HIGH Force to 1 all status bits of the interrupt status register (STAT) only if the corresponding bit field in the Interrupt signal enable register (ISE) is set.
11	D7D	DAT7 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT7 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT7 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
10	D6D	DAT6 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT6 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT6 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
9	D5D	DAT5 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT5 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT5 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
8	D4D	DAT4 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT4 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT4 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
7	D3D	DAT3 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT3 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT3 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
6	D2D	DAT2 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT2 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT2 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
5	D1D	DAT1 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT1 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT1 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
4	D0D	DAT0 input/output signal data value		RW	0
		0	LOW If SYSTEST.DDIR bit = 0 (output mode direction), the DAT0 line is driven low. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.DDIR bit = 0 (output mode direction), the DAT0 line is driven high. If SYSTEST.DDIR bit = 1 (input mode direction), no effect.
3	DDIR	Control of the DAT[7:0] pins direction		RW	0
		0	OUT The DAT lines are outputs (host to card)
		1	IN The DAT lines are inputs (card to host)
2	CDAT	CMD input/output signal data value		RW	0
		0	LOW If SYSTEST.CDIR bit = 0 (output mode direction), the CMD line is driven low. If SYSTEST.CDIR bit = 1 (input mode direction), no effect.
		1	HIGH If SYSTEST.CDIR bit = 0 (output mode direction), the CMD line is driven high. If SYSTEST.CDIR bit = 1 (input mode direction), no effect.
1	CDIR	Control of the CMD pin direction		RW	0
		0	OUT The CMD line is an output (host to card)
		1	IN The CMD line is an input (card to host)
0	MCKD	MMC clock output signal data value		RW	0
		0	LOW The output clock is driven low
		1	HIGH The output clock is driven high

:SDMMC:CON

Address offset	0x0000 012C
Description	SDMMC Configuration Register. This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals.
Type	RW

Bits	Field Name	Description		Type	Reset
31:22	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
21	SDMA_LNE	Peripheral DMA Level/Edge Request The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to VAL register or late de-assertion, request remains active until last allowed data written into VAL.		RW	0
		0	EDGE peripheral DMA edge sensitive
		1	LEVEL peripheral DMA level sensitive
20	REVERVED	DMA Master or Slave selection Note: these bit fields are not used, since the IP not support MDMA.		RW	0
19	RESERVED	Dual Data Rate mode Note: these bit fields are not used, Only Standard mode is supported.		RW	0
18:17	RESERVED	Note: these bit fields are not used.		RW	0x0
16	CLKEXTFREE	External clock free running This register is used to maintain card clock out of transfer transaction to enable peripheral module (for example to generate a synchronous interrupt on mmc_dat[1] ). The Clock will be maintained only if SYSCTL.CEN bit is set.		RW	0
		0	OFF External card clock is cut off outside active transaction period
		1	ON External card clock is maintained even out of active transaction period only if SYSCTL.CEN bit is set.
15	PADEN	Control Power for MMC Lines. Note: Power control is not supported using this bit.		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
14	OBIE	Out-of-Band Interrupt Enable. Note: The Out-of-Band (OBI) interrupt is not supported.		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
13	OBIP	Out-of-Band Interrupt Polarity Note: The Out-of-Band (OBI) interrupt is not supported.		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
12	CEATA	CE-ATA control mode (MMC cards compliant with CE-ATA) This bit is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features.		RW	0
		0	STANDARD Standard MMC/SD/SDIO mode
		1	CEATA CE-ATA mode. Next commands are considered as CE-ATA commands.
11	CTPL	Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers.		RW	0
		0	ALL Disable all the input buffers outside of a transaction
		1	NOTDAT1 Disable all the input buffers except the buffer of DAT[1] outside of a transaction
10:9	DVAL	Debounce filter value (all cards) This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card.		RW	0x3
		0x0	DEB0 33 us debounce period
		0x1	DEB1 231 us debounce period
		0x2	DEB2 1 ms debounce period
		0x3	DEB3 8.4 ms debounce period
8	WPP	Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the type of the connector housing that accommodates the card.		RW	0
		0	LOW Active low level
		1	HIGH Active high level
7	CDP	Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card.		RW	0
		0	LOW Active low level
		1	HIGH Active high level
6	MIT	MMC interrupt command (MMC cards only). This bit must be set to 1, when the next write access to the command register (CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response.		RW	0
		0	OFF MMC interrupt command not possible, command timeout enabled
		1	ON MMC interrupt command possible, Command timeout disabled
5	DW8	8-bit mode MMC select (MMC cards only) For SD/SDIO cards, this bit must be cleared to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification.		RW	0
		0	_1OR4BIT 1-bit or 4-bit data width
		1	_8BIT Open drain or broadcast host response
4	MODE	Mode select (all cards) This bit selects the functional mode.		RW	0
		0	FUNC Functional mode. Transfers to the MMC/SD/SDIO cards follow the card protocol. The MMC clock is enabled. MMC/SD transfers are operated under the control of the CMD register.
		1	SYSTST SYSTEST mode. The signal pins are configured as general-purpose input/output and the 1024-byte buffer is configured as a stack memory accessible only by the local host or system DMA. The pins retain their default type (input, output or inout). SYSTEST mode is operated under the control of the SYSTEST register.
3	STR	Stream command (MMC cards only) This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20WRITE_DAT_UNTIL_STOP).		RW	0
		0	BLOCK Block oriented data transfer
		1	STREAM Stream oriented data transfer
2	HR	Broadcast host response (MMC cards only) This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core. In order to have the host response to be generated in open drain mode, the IO must be configured accordingly in EXT_IOMUX. When CON.CEATA bit is set to 1 and ARG cleared to 0, when writing the value of 0 into CMD register, the host controller performs a 'command completion signal disable' token (i.e., mmc_cmd line held to 0 during 47 cycles followed by a 1).		RW	0
		0	OFF The host does not generate a 48-bit response instead of a command
		1	ON The host generates a 48-bit response instead of a command or a command completion signal disable token
1	INIT	Send initialization stream (all cards) When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the mmc_cmd line to 1 during 80 clock cycles. The initialization sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider should be set to ensure that 80 clock periods are greater than 1ms. Note: In this mode, there is no command sent to the card and no response is expected. A command complete interrupt will be generated once the initialization sequence is completed.		RW	0
		0	OFF The host does not send an initialization sequence
		1	ON The host sends an initialization sequence
0	OD	Card open drain mode This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register CON.HR).		RW	0
		0	OFF No Open Drain
		1	ON Open Drain or Broadcast host response

:SDMMC:NUMDEL

Address offset	0x0000 0130
Description	SDMMC Power counter register This register is used to program a MMC counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	NUMDEL	Power counter This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. 0h = No additional delay added 1h = TCF delay (card clock period) 2h = TCF x 2 delay (card clock period) FFFEh = TCF x 65534 delay (card clock period) FFFFh = TCF x 65535 delay (card clock period)		RW	0x0000
		0x0000	MINIMUM Minimum value of NUMDEL
		0xFFFF	MAXIMUM Maximum value of NUMDEL

:SDMMC:SDMASA

Address offset	0x0000 0200
Description	DMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	SDMA_SYSARESERVED	SDMA System Address register		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Maximum value
		0x0000 0000	MINIMUM Minimum value

:SDMMC:BLK

Address offset	0x0000 0204
Description	Transfer Length Configuration Register BLEN is the block size register. NBLK is the block count register. This register shall be used for any card.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	NBLK	Block count for current transfer This register is enabled when Block count Enable (CMD.BCE bit) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. 0h = Stop count 1h = 1 block 2h = 2 blocks FFFFh = 65535 blocks		RW	0x0000
		0x0000	MINIMUM Minimum value
		0xFFFF	MAXIMUM Maximum value
15:11	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
10:0	BLEN	Transfer block size This register is enabled when Block Count Enable (CMD.BCE) is set to 1 and is valid only for multiple block transfers. It specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. 0h = No data transfer 1h = 1 byte block length 2h = 2 bytes block length 3h = 3 bytes block length 1FFh = 511 bytes block length 200h = 512 bytes block length 3FFh = 1023 bytes block length 400h = 1024 bytes block length		RW	0x000
		0x000	MINIMUM Minimum value
		0x7FF	MAXIMUM Maximum value

:SDMMC:ARG

Address offset	0x0000 0208
Description	Command argument register This register contains command argument specified as bit 39-8 of Command-Format. These registers must be initialized prior to sending the command itself to the card (write action into the register CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	CMDARG	Command argument		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Maximum value
		0x0000 0000	MINIMUM Minimum value

:SDMMC:CMD

Address offset	0x0000 020C
Description	Command and data transfer register This register configures the data and command transfers. A write into the most significant byte send the command. A write into CMD[15:0] during data transfer has no effect. This register can be used for any card. In SYSTEST mode, a write to the CMD register will not start a transfer.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29:24	IDX	Command index Binary encoded value from 0 to 63 specifying the command number to send to card. Examples: - IDX = 7h, sends CMD7 to the card - IDX = 29h, sends CMD41 to the card		RW	0x00
		0x00	MINIMUM Minimum value
		0x3F	MAXIMUM Maximum value
23:22	CMDTYP	Command type This bitfield specifies three types of special commands: - Suspend - Resume - Abort The bitfield is cleared to 0 for all other commands.		RW	0x0
		0x0	OTHER Others commands
		0x1	SUSPEND Upon CMD52 "Bus Suspend" operation
		0x2	RESUME Upon CMD52 "Function Select" operation
		0x3	ABORT Upon CMD12 or CMD52 "I/O Abort" command
21	DP	Data present select This register indicates that data is present and DAT line(s) shall be used. It must be cleared to 0 in the following conditions: - Command using only CMD line - Command with no data transfer but using busy signal on DAT[0] line - Resume command		RW	0
		0	NODAT Command with no data transfer
		1	DAT Command with data transfer
20	CICE	Command Index check enable If this bit is set to 1, the host checks the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.		RW	0
		0	DISABLE Index check disable
		1	ENABLE Index check enable
19	CCCE	Command CRC check enable If this bit is set to 1, the host checks the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.		RW	0
		0	DISABLE CRC field check disable
		1	ENABLE CRC field check enable
18	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
17:16	RSPTYPE	Response type This bits defines the response type of the command.		RW	0x0
		0x0	NORESP No response
		0x1	LEN136 Response Length 136 bits
		0x2	LEN48 Response Length 48 bits
		0x3	LEN48BUSY Response Length 48 bits with busy after response
15:6	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
5	MSBS	Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit must be cleared to 0.		RW	0
		0	SINGLE Single block
		1	BLOCK Multiple block
4	DDIR	Data transfer Direction Select This bit defines the data transfer direction		RW	0
		0	WRITE Data Write (host to card)
		1	READ Data Read (card to host)
3:2	ACEN	Auto CMD Enable This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation (1) Auto CMD12 Enable When this field is set to 01b, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status register. The Host Driver shall not set this bit if the command does not require CMD12. In particular, secure commands defined in the Part 3 File Security specification do not require CMD12. (2) Auto CMD23 Enable When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register. The Host Controller Version 3.00 and later shall support this function. The following conditions are required to use the Auto CMD23. - Auto CMD23 Supported (Host Controller Version is 3.00 or later) - A memory card that supports CMD23 (SCR[33]=1) - If DMA is used, it shall be ADMA. - Only when CMD18 or CMD25 is issued (Note, the Host Controller does not check command index.) Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register. 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register.		RW	0x0
		0x0	DISABLE Auto CMD12 disable
		0x1	ENA12 Auto CMD12 enable or CCS detection enabled
		0x2	ENA23 Auto CMD23 enable
1	BCE	Block Count Enable This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.		RW	0
		0	DISABLE Block count disabled for infinite transfer
		1	ENABLE Block count enabled for multiple block transfer with known number of blocks
0	DE	DMA enable DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation starts when the host writes to the upper byte of Command register (00Fh).		RW	0
		0	DISABLE DMA mode disable
		1	ENABLE DMA mode enable

:SDMMC:RSP10

Address offset	0x0000 0210
Description	Response register 10 This 32-bit register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b or R6.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	RSP1	Command Response [31:16]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value
15:0	RSP0	Command Response [15:0]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value

:SDMMC:RSP32

Address offset	0x0000 0214
Description	Response register 32 This 32-bit register holds bits positions [63:32] of command response type R2.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	RSP3	Command Response [63:48]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value
15:0	RSP2	Command Response [47:32]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value

:SDMMC:RSP54

Address offset	0x0000 0218
Description	Response register 54 This 32-bit register holds bits positions [95:64] of command response type R2.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	RSP5	Command Response [95:80]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value
15:0	RSP4	Command Response [79:64]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value

:SDMMC:RSP76

Address offset	0x0000 021C
Description	Response register 76 This 32-bit register holds bits positions [127:96] of command response type R2.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	RSP7	Command Response [127:112]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value
15:0	RSP6	Command Response [111:96]		RO	0x0000
		Read 0x0000	MINIMUM Minimum value
		Read 0xFFFF	MAXIMUM Maximum value

:SDMMC:VAL

Address offset	0x0000 0220
Description	Data register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x 256 (1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. If the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Buffer data register In functional mode (CON.MODE = FUNC): - a read access to this register is allowed only when the buffer read enable status is set to 1 (PSTATE.BREN), otherwise a bad access (STAT.BADA) is signaled. - a write access to this register is allowed only when the buffer write enable status is set to 1 (PSTATE.BWEN), otherwise a bad access (STAT.BADA) is signaled and the data is not written.		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Maximum value
		0x0000 0000	MINIMUM Minimum value

:SDMMC:PSTATE

Address offset	0x0000 0224
Description	SDMMC controller status register The host can get the status of the SDMMC controller from this 32-bit read only register.
Type	RO

Bits	Field Name	Description		Type	Reset
31:25	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
24	CLEV	Command line signal level This status is used to check the CMD line level to recover from errors, and for debugging.		RO	0
		Read 0	LOW The mmc_cmd line level is 0
		Read 1	HIGH The mmc_cmd line level is 1
23:20	DLEV	VAL line 0 to 3 signal level Bit 3 reflects VAL[3] signal level. Bit 2 reflects VAL[2] signal level. Bit 1 reflects VAL[1] signal level. Bit 0 reflects VAL[0] signal level. This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].		RO	0x0
		Read 0x0	MINIMUM Minimum value
		Read 0xF	MAXIMUM Maximum value
19	WP	Write Protect This bit reflects the write protect input pin (SDWP) level.		RO	0
		Read 0	PROTECT The card is write protected. Note: CON.WPP need to reflect the correct active setting of the write protect input signal (SDWP).
		Read 1	NOPROTECT The card is not write protected Note: CON.WPP need to reflect the correct active setting of the write protect input signal (SDWP).
18	CDPL	Card Detect Pin Level This bit reflects the inverse value of the card detect input pin (SDCD).		RO	0
		Read 0	HIGH The value of the card detect input pin (SDCD) is 1
		Read 1	LOW The value of the card detect input pin (SDCD) is 0
17	CSS	Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (PSTATE.CPDL). Debouncing is performed on the card detect input pin (SDCD) to detect card stability. This bit is not affected by software reset.		RO	0
		Read 0	DEBOUNCE Card detect pin level is debouncing
		Read 1	STABLE Card detect pin level is stable
16	CINS	Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (STAT.CINS). An active to inactive transition of the card detect input pin (SDCD) will generate a card removal interrupt (STAT.REM). This bit is not affected by a software reset.		RO	0
		Read 0	NOCARD No card is detected Note: CON.CDP need to reflect the correct active level of the write protect input signal (SDCD).
		Read 1	CARD Card is detected Note: CON.CDP need to reflect the correct active level of the write protect input signal (SDCD).
15:12	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
11	BRE	Buffer read enable This bit is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.		RO	0
		Read 0	DISABLE Read BLEN bytes disable
		Read 1	ENABLE Read BLEN bytes enable. Readable data exists in the buffer.
10	BWE	Buffer write enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.		RO	0
		Read 0	NOSPACE There is no room left in the buffer to write BLEN bytes of data.
		Read 1	SPACE There is enough space in the buffer to write BLEN bytes of data
9	RTA	Read transfer active (SD mode only) This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: - After the end bit of the read command - When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: - When the last data block as specified by block length is transferred to the system. - When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.		RO	0
		Read 0	NOVAL No valid data
		Read 1	ACTIVE Read data transfer on going
8	WTA	Write transfer active This status indicates a write transfer active. If this bit is 0, it means no valid write data exists. This bit is set in either of the following cases: - After the end bit of the write command. - When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: - After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) - After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the host to determine when to issue commands during write busy.		RO	0
		Read 0	NOVAL No valid data
		Read 1	ACTIVE Write data transfer on going
7:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
2	DLA	VAL Line Active (SD Mode only) This bit indicates whether one of the VAL lines on SD bus is in use.		RO	0
		Read 0	INACTIVE mmc_data line inactive
		Read 1	ACTIVE mmc_data line active
1	DATI	Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the host can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0.		RO	0
		Read 0	ALLOWED Issuing of command using the DAT lines is allowed
		Read 1	NOTALLOWED Issuing of command using DAT lines is not allowed
0	CMDI	Command Inhibit (CMD) (SD Mode Only) If this bit is 0, it indicates the CMD line is not in use and the host can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt. If the host cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register.		RO	0
		Read 0	ALLOWED Issuing of command using mmc_cmd line is allowed
		Read 1	NOTALLOWED Issuing of command using mmc_cmd line is not allowed

:SDMMC:HCTL

Address offset	0x0000 0228
Description	Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. HCTL[31:24] = Wakeup control HCTL[23:16] = Block gap control HCTL[15:8] = Power control HCTL[7:0] = Host control
Type	RW

Bits	Field Name	Description		Type	Reset
31:28	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	OBWE	Wakeup event enable for 'Out-of-Band' Interrupt Note: This bit has no effect since the wakeup output is unconnected Note: Out-of-Band Interrupt (OBI) is not supported		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
26	REM	Wakeup event enable on SD card removal Note: This bit has no effect since the wakeup output is unconnected		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
25	INS	Wakeup event enable on SD card insertion Note: This bit has no effect since the wakeup output is unconnected		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
24	IWE	Wakeup event enable on SD card interrupt Note: This bit has no effect since the wakeup output is unconnected		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
23:20	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
19	IBG	Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be cleared to 0.		RW	0
		0	DISABLE Disable interrupt detection at the block gap in 4-bit mode
		1	ENABLE Enable interrupt detection at the block gap in 4-bit mode
18	RWC	Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (HCTL.SBGR) generates a read wait period after the current end of block. Note: If read wait is not supported it may cause a conflict on mmc_dat line.		RW	0
		0	DISABLE Disable read wait control. Suspend/resume cannot be supported
		1	ENABLE Enable read wait control
17	CR	Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (HCTL[16] SBGR bit). Set this bit to 1 restarts the transfer. The bit is automatically cleared to 0 by the host controller when transfer has restarted, that is, mmc_dat line is active (PSTATE.DLA) or transferring data (PSTATE.WTA). The Stop at block gap request must be disabled (HCTL[16] SBGR bit =0) before setting this bit.		RW	0
		0	NOEFFECT No effect
		1	RESTART Transfer restart
16	SBGR	Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (HCTL.CR) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver must set this bit after all block data written. Until the transfer completion (STAT.TC bit set to 1), the host driver must leave this bit set to 1. If this bit is set, the local host may not write to the data register (VAL).		RW	0
		0	TRANS Transfer mode
		1	STOP Stop at block gap
15:12	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
11:9	SDVS	SD bus voltage select (All cards). The host driver should set these bits to select the voltage level for the card according to the voltage supported by the system (CAPA[26] VS18 bit, CAPA[25] VS30 bit, CAPA[24] VS33 bit) before starting a transfer.		RW	0x0
		0x5	LOW 1.8V (Typical)
		0x6	MID 3.0V (Typical)
		0x7	HIGH 3.3V (Typical)
8	SDBP	SD bus power. Before setting this bit, the host driver shall select the SD bus voltage (HCTL[11:9] SDVS bits). If the host controller detects the No card state, this bit is automatically cleared to 0. If the module is power off, a write in the command register (CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage is not supported according to capability register (CAPA[26] VS18 bit, CAPA[25] VS30 bit or CAPA[24] VS33 bit).		RW	0
		0	OFF Power off
		1	ON Power on
7	CDSS	Card Detect Signal Selection This bit selects the source for the card detection. When the source for the card detection is switched, the Card insertion and removal interrupts should be disabled to avoid unexpected interrupts. In Card Detect Test Level mode, the card insertion and removal signal can be controlled by HCTL.CDTL.		RW	0
		0	SDCD SDCD signal is selected (for normal use)
		1	TEST The Card Detect Test Level is selected (for test purposes)
6	CDTL	Card Detect Test Level This bit is only functional when the Card Detect Signal Selection selects the Card Detect Test Level mode (HCTL.CDSS = 1).		RW	0
		0	NOCARD No card
		1	CARD Card inserted
5	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
4:3	DMAS	DMA Select Mode Note: This functionality is not is not supported, since MADMA_EN = 0 by design.		RW	0x0
		0x0	MINIMUM Minimum value
		0x3	MAX Maximum value
2	HSPE	High Speed Enable Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is cleared to 0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock.		RW	0
		0	NOMAL Normal speed mode
		1	HIGH High speed mode
1	DTW	Data transfer width This bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card.		RW	0
		0	WIDTH_1 1-bit Data width (mmc_dat0 used)
		1	WIDTH_4 4-bit Data width (mmc_dat[3:0] used)
0	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0

:SDMMC:SYSCTL

Address offset	0x0000 022C
Description	SD System Control Register This register defines the system controls clock frequency management and data timeout. SYSCTL[23:16] = Timeout control SYSCTL[15:0] = Clock control
Type	RW

Bits	Field Name	Description		Type	Reset
31:27	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
26	SRD	Software reset for mmc_dat line This bit is set to 1 for reset and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT		RW	0
		0	COMPL Reset completed
		1	ASSERT Reset asserted
25	SRC	Software reset for mmc_cmd line This bit is set to 1 for reset and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT		RW	0
		0	COMPL Reset completed
		1	ASSERT Reset asserted
24	SRA	Software reset for all This bit is set to 1 for reset, and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT		RW	0
		0	COMPL Reset completed
		1	ASSERT Reset asserted
23:20	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
19:16	DTO	Data timeout counter value and busy timeout This value determines the interval to detect mmc_dat lines timeouts. The host driver needs to set this bitfield based on: - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer) - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card - the timeout clock base frequency (CAPA.TCF) If the card does not respond within the specified number of cycles, a data timeout error occurs (STAT.DTO). The Data timeout counter can also be used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write. 0h = TCF x 2^13 1h = TCF x 2^14 Eh = TCF x 2^27 Fh = Reserved		RW	0x0
		0x0	MINIMUM Minimum value
		0xE	MAXIMUM Maximum value
15:6	CLKD	Clock frequency select This bitfield defines the ratio between a reference clock frequency (system dependent) and the output clock frequency on the mmc_clk pin of the memory card (MMC, SD, or SDIO). 0h = Clock Ref bypass 1h = Clock Ref bypass 2h = Clock Ref / 2 3h = Clock Ref / 3 3FFh = Clock Ref / 1023		RW	0x000
		0x000	MINIMUM Minimum value
		0x3FF	MAXIMUM Maximum value
5:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
2	CEN	Card clock enable This bit controls the clock to the card.		RW	0
		0	OFF The clock is not provided to the card . Clock frequency can be changed.
		1	ON The clock is provided to the card and can be automatically gated when SYSCFG.AUTOIDLE bit is set to 1 (default value). The host driver must wait to set this bit to 1 until the internal clock is stable (SYSSTAT.ICS).
1	ICS	Internal clock stable (status) This bit indicates that the internal clock is stable		RO	0
		Read 0	NOSTAB The internal clock is not stable
		Read 1	STAB The internal clock is stable after enabling the clock (SYSCTL.ICEN) or after changing the clock ratio (SYSCTL.CLKD).
0	ICE	Internal clock enable This bit controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wake-up events) and the interface clock (used for reads and writes to the module register map) are not affected by this register.		RW	0
		0	STOP The internal clock is stopped (very low power state).
		1	RUN The internal clock oscillates and can be automatically gated when SYSCFG.AUTOIDLE bit is set to 1 (default value).

:SDMMC:STAT

Address offset	0x0000 0230
Description	The interrupt status regroups all the status of the module internal events that can generate an interrupt. STAT[31:16] = Error Interrupt Status STAT[15:0] = Normal Interrupt Status The error bits are located in the upper 16 bits of the STAT register. All bits are cleared by writing a 1 to them. Additionally, bits 15 and 8 serve as special error bits. These cannot be cleared by writing a 1 to them. Bit 15 (ERRI) is automatically cleared when the error causing to ERRI to be set is handled. (that is, when bits 31:16 are cleared, bit 15 will be automatically cleared). Bit 8 (CIRQ) is cleared by writing a 0 to IE[8] (masking the interrupt) and servicing the interrupt.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29	BADA	Bad access to data space. This bit is set automatically to indicate a bad access to buffer when not allowed: During a read access to the data register (VAL) while buffer reads are not allowed (PSTATE[11] BRE bit =0). During a write access to the data register (VAL) while buffer writes are not allowed (PSTATE[10] BWE bit=0). 0h (W) = Status bit unchanged 0h (R) = No interrupt 1h (W) = Status is cleared. 1h (R) = Bad access		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
28	CERR	Card error. This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E (error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error STA in set. There is no card error detection for autoCMD12 command. The host driver shall read RSP76 register to detect error bits in the command response. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Card error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
27:25	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
24	ACE	Auto CMD12 error. This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = AutoCMD12 error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
23	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
22	DEB	Data End Bit error. This bit is set automatically when detecting a 0 at the end bit position of read data on mmc_dat line or at the end position of the CRC status in write mode. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Data end bit error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
21	DCRC	Data CRC Error. This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position "010" token during a block write command. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Data CRC error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
20	DTO	Data timeout error. This bit is set automatically according to the following conditions: Busy timeout for R1b, R5b response type. Busy timeout after write CRC status. Write CRC status timeout. Read data timeout. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Time out		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
19	CIE	Command index error. This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable bit (CMD[20] CICE). 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command index error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
18	CEB	Command end bit error. This bit is set automatically when detecting a 0 at the end bit position of a command response. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command end bit error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
17	CCRC	Command CRC error. This bit is set automatically when there is a CRC7 error in the command response depending on the enable bit (CMD[19] CCCE). 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command CRC error		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
16	CTO	Command timeout error. This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Time Out		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
15	ERRI	Error interrupt. If any of the bits in the Error Interrupt Status register (STAT [31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored. 0h (R) = No interrupt 1h (R) = Error interrupt event(s) occurred		RO	0
		Read 0	NOINT No interrupt occured
		Read 1	INT Interrupt occured
14:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	OBI	Out-of-band interrupt (This interrupt is only useful for MMC card). Note: Out-of-band interrupt (OBI) is not supported.		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
8	CIRQ	Card interrupt. This bit is only used for SD and SDIO cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wake-up). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives mmc_cmd line to zero during one cycle after data transmission end. All modes above are fully exclusive. The controller interrupt must be clear by setting IE[8] CIRQEN to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as IE[8] CIRQEN is set to 1. Writes to this bit are ignored. 0h (R) = No card interrupt 1h (R) = Generate card interrupt		RO	0
		Read 0	NOINT No interrupt occured
		Read 1	INT Interrupt occured
7	CREM	Card Removal. This bit is set automatically when PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (PSTATE[CINS]). 0h (W) = Status bit unchanged 0h (R) = Card State stable or debouncing 1h (W) = Status is cleared 1h (R) = Card Removed		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
6	CINS	Card Insertion. This bit is set automatically when PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (PSTATE[CINS]). 0h (W) = Status bit unchanged 0h (R) = Card State stable or debouncing 1h (W) = Status is cleared. 1h (R) = Card inserted		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
5	BRR	Buffer read ready. This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by the BLK [10:0] BLEN bit field is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set instead a DMA receive request to the main DMA controller of the system is generated. 0h (W) = Status bit unchanged 0h (R) = Not ready to read buffer 1h (W) = Status is cleared. 1h (R) = Ready to read buffer		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
4	BWR	Buffer write ready. This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by BLK [10:0] BLEN. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set instead, a DMA transmit request to the main DMA controller of the system is generated. 0h (W) = Status bit unchanged 0h (R) = Not ready to write buffer 1h (W) = Status is cleared. 1h (R) = Ready to write buffer		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
3	DMA	DMA Interrupt This status is set when an interrupt is required after the data transfer is complete.		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
2	BGE	Block gap event. When a stop at block gap is requested (HCTL[16] SBGR bit), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. 0h (W) = Status bit unchanged 0h (R) = No block gap event 1h (W) = Status is cleared 1h (R) = Transaction stopped at block gap		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
1	TC	Transfer completed. This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (HCTL[16] SBGR bit). 0h (W) = Status bit unchanged 0h (R) = No transfer complete 1h (W) = Status is cleared 1h (R) = Data transfer complete		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured
0	CC	Command complete. This bit is set when a 1-to-0 transition occurs in the register command inhibit (PSTATE[0] CMDI bit) 0h (W) = Status bit unchanged 0h (R) = No command complete 1h (W) = Status is cleared 1h (R) = Command complete		RW	0
		0	NOINT No interrupt occured
		1	INT Interrupt occured

:SDMMC:IE

Address offset	0x0000 0234
Description	This register allows to enable/disable the module to set status bits on an event-by-event basis. IE[31:16] = Error Interrupt Status Enable IE[15:0] = Normal Interrupt Status Enable
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29	BADAEN	Bad access to data space interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
28	CERREN	Card error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
27	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
26	RESERVED1	No use Note: Writing values other than 0 might produce undesired results. Always set this bits to 0.		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
25	ADMAEEN	ADMA Error Status Enable Note: This functionality is not supported, since MADMA_EN is set to 0 in the design.		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
24	ACEEN	Auto CMD12 error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
23	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
22	DEBEN	Data end bit error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
21	DCRCEN	Data CRC error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
20	DTOEN	Data timeout error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
19	CIEEN	Command index error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
18	CEBEN	Command end bit error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
17	CCRCEN	Command CRC error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
16	CTOEN	Command timeout error interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
15	NULL	Fixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored.		RO	0
		Read 0	MSK Interrupt masked
		Read 1	ENABLE Interrupt enabled
14:11	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
10	RESERVED0	No use Note: Writing values other than 0 might produce undesired results. Always set this bits to 0.		RW	0
		0	MIN Minimum value
		1	MAX Maximum value
9	OBIEN	Out-of-band interrupt enable A write to this register when CON[14] OBIE is cleared to 0 is ignored. Note: The OBI functionallity is not supported!		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
8	CIRQEN	Card interrupt enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1.		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
7	CREMEN	Card Removal interrupt Enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
6	CINSEN	Card Insertion interrupt Enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
5	BRREN	Buffer read ready interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
4	BWREN	Buffer write ready interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
3	DMAEN	DMA interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
2	BGEEN	Block gap event interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
1	TCEN	Transfer completed interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled
0	CCEN	Command completed interrupt enable		RW	0
		0	MSK Interrupt masked
		1	ENABLE Interrupt enabled

:SDMMC:ISE

Address offset	0x0000 0238
Description	This register allows to enable/disable the module internal interrupt signaling on an event-by-event basis. ISE[31:16] = Error Interrupt Signal Enable ISE[15:0] = Normal Interrupt Signal Enable
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29	BADASEN	Bad access to data space interrupt enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
28	CERRSEN	Card error interrupt signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
27	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
26	RESERVED1	No use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.		RW	0
		0	LOW Always set this bit to 0
		1	HIGH Do not set this bit
25	ADMAESEN	ADMA Error Signal Enable Note: This functionality is not supported, since MADMA_EN is set to 0 in the design.		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
24	ACESEN	Auto CMD12 error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
23	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
22	DEBSEN	Data end bit error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
21	DCRCSEN	Data CRC error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
20	DTOSEN	Data timeout error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
19	CIESEN	Command index error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
18	CEBSEN	Command end bit error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
17	CCRCSEN	Command CRC error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
16	CTOSEN	Command timeout error signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
15	NULL	Fixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored.		RO	0
		Read 0	MSK Interrupt masked
		Read 1	ENABLE Interrupt enabled
14:11	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
10	RESERVED0	No use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.		RW	0
		0	LOW Always set this bit to 0
		1	HIGH Do not set this bit
9	OBISEN	Out-of-band interrupt signal status enable. A write to this register when CON[14] OBIE is cleared to 0 is ignored. Note: The OBI functionallity is not supported!		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
8	CIRQSEN	Card interrupt signal status enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1.		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
7	CREMSEN	Card Removal signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
6	CINSSEN	Card Insertion signal status enable.		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
5	BRRSEN	Buffer read ready signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
4	BWRSEN	Buffer write ready signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
3	DMASEN	DMA signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
2	BGESEN	Block gap event signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
1	TCSEN	Transfer completed signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled
0	CCSEN	Command completed signal status enable		RW	0
		0	DISABLE Status Interrupt signaling disabled
		1	ENABLE Status Interrupt signaling enabled

:SDMMC:AC12

Address offset	0x0000 023C
Description	AC12 Error register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this AC12 register when an auto CMD12 error interrupt occurs. This register is valid only when auto CMD12 is enabled (CMD.ACEN) and auto CMD12Error (STAT.ACE) is set to 1. These bits are automatically reset when starting a new adtc command with data.
Type	RW

Bits	Field Name	Description		Type	Reset
31	RESERVED1	No use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.		RW	0
		0	LOW Always set this bit to 0
		1	HIGH Do not set this bit
30	AIEN	Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card.		RW	0
		0	DISABLE Asynchronous Interrupt disabled
		1	ENABLE Asynchronous Interrupt enabled
29:24	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
23:22	RESERVED0	No use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.		RW	0x0
		0x0	LOW Always set this bit to 0
		0x1	HIGH Do not set this bit
21:20	DSSEL	Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the Capabilities register.		RW	0x0
		0x0	TYPE_B Driver Type B is selected
		0x1	TYPE_A Driver Type A is selected
		0x2	TYPE_C Driver Type C is selected
		0x3	TYPE_D Driver Type D is selected
19	V1P8SEN	1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or RESERVED50 in the Capabilities register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x). Note: Dragon supports only 3.3V. Always set this bit to 0.		RW	0
		0	DISABLE 3.3V Signaling
		1	ENABLE 1.8V Signaling
18:16	UHSMS	UHS Mode Select This field is used to select one of UHS-I modes or e.MMC HS200 mode and effective when 1.8V Signaling Enable is set to 1. Note: Dragon does not support 1.8V signaling and UHS modes. Always set this bitfield to 0.		RW	0x0
		0x0	SDR12 SDR12
		0x1	SDR25 SDR25
		0x2	SDR50 SDR50
		0x3	SDR104 SDR104 / HS200
		0x4	RESERVED50 RESERVED50
15:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
7	CNI	Command not issue by auto CMD12 error If this bit is set to 1, a pending command is not executed due to auto CMD12 error ACEB, ACCE, ACTO, or ACNE.		RO	0
		Read 0	NOERR No error
		Read 1	ERR Error occurred
6:5	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
4	ACIE	Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (CMD.CICEN).		RO	0
		Read 0	NOERR No error
		Read 1	ERR Error occurred
3	ACEB	Auto CMD12 end bit error. This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response.		RO	0
		Read 0	NOERR No error
		Read 1	ERR Error occurred
2	ACCE	Auto CMD12 CRC error. This bit is set to 1 when a CRC7 error is detected in the auto CMD12 command response.		RO	0
		Read 0	NOERR No error
		Read 1	ERR Error occurred
1	ACTO	Auto CMD12 timeout error. This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command.		RO	0
		Read 0	NOERR No error
		Read 1	ERR Error occurred
0	ACNE	Auto CMD12 not executed. This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before auto CMD12 starts.		RO	0
		Read 0	NOERR Auto CMD12 executed
		Read 1	ERR Auto CMD12 not executed

:SDMMC:CAPA

Address offset	0x0000 0240
Description	Capability register This register lists the capabilities of the MMC/SD/SDIO host controller.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29	AIS	Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt.		RO	1
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
28	BUS64BIT	64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. 0h (R) = 32-bit System bus address 1h (R) = 64-bit System bus address		RO	0
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
27	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
26	VS18	Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 1.8 V not supported 0h (R) = 1.8 V not supported 1h (W) = 1.8 V supported 1h (R) = 1.8 V supported		RW	0
		0	NOSUPPORT Not supported
		1	SUPPORT Supported
25	VS30	Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 3.0 V not supported 0h (R) = 3.0 V not supported 1h (W) = 3.0 V supported 1h (R) = 3.0 V supported		RW	0
		0	NOSUPPORT Not supported
		1	SUPPORT Supported
24	VS33	Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 3.3 V not supported 0h (R) = 3.3 V not supported 1h (W) = 3.3 V supported 1h (R) = 3.3 V supported		RW	0
		0	NOSUPPORT Not supported
		1	SUPPORT Supported
23	SRS	Suspend/resume support (SDIO cards only). This bit indicates whether the host controller supports suspend/resume functionality.		RO	1
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
22	DS	DMA support This bit indicates that the Host controller is able to use DMA to transfer data between system memory and the Host controller directly.		RO	1
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
21	HSS	High-speed support This bit indicates that the host controller supports high speed operations and can supply an up-to-52 MHz clock to the card.		RO	1
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
20	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
19	AD2S	This bit indicates whether the Host Controller is capable of using ADMA2.		RO	0
		Read 0	NOSUPPORT Not supported
		Read 1	SUPPORT Supported
18	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
17:16	MBL	Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. The host controller supports 512 bytes and 1024 bytes block transfers. 0h = 512 bytes 1h = 1024 bytes 2h = 2048 bytes		RO	0x1
		Read 0x0	MINIMUM Minimum value
		Read 0x3	MAXIMUM Maximum value
15:14	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
13:8	BCF	Base clock frequency for clock provided to the card. ARRAY(0x1bfe1b0)		RO	0x00
		Read 0x00	MINIMUM Minimum value
		Read 0x3F	MAXIMUM Maximum value
7	TCU	Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error.		RO	1
		Read 0	KHZ kHz
		Read 1	MHZ MHz
6	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
5:0	TCF	Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (DTO interrupt). The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock frequency is not available in this register.		RO	0x00
		Read 0x00	MINIMUM Minimum value
		Read 0x3F	MAXIMUM Maximum value

:SDMMC:CURCAPA

Address offset	0x0000 0248
Description	Current capability register This register indicates the maximum current capability for each voltage.
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
23:16	CUR18	Maximum current for 1.8V The maximum current capability for this voltage is not available. Feature not implemented.		RW	0x00
		0x00	MINIMUM Minimum value
		0xFF	MAXIMUM Maximum value
15:8	CUR30	Maximum current for 3.0V The maximum current capability for this voltage is not available. Feature not implemented.		RW	0x00
		0x00	MINIMUM Minimum value
		0xFF	MAXIMUM Maximum value
7:0	CUR33	Maximum current for 3.3V The maximum current capability for this voltage is not available. Feature not implemented.		RW	0x00
		0x00	MINIMUM Minimum value
		0xFF	MAXIMUM Maximum value

:SDMMC:FE

Address offset	0x0000 0250
Description	The Force Event register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29	BADA	Force Event Bad access to data space		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
28	CERR	Force Event Card error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
27:25	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
24	ACE	Force Event Auto CMD12 error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
23	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
22	DEB	Force Event Data End Bit error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
21	DCRC	Force Event Data CRC error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
20	DTO	Force Event Data timeout error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
19	CIE	Force Event Command index error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
18	CEB	Force Event Command end bit error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
17	CCRC	Force Event Comemand CRC error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
16	CTO	Force Event Command Timeout error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
15:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
7	CNI	Force Event Command not issue by Auto CMD12 error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
6:5	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
4	ACIE	Force Event Auto CMD12 index error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
3	ACEB	Force Event Auto CMD12 end bit error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
2	ACCE	Force Event Auto CMD12 CRC error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
1	ACTO	Force Event Auto CMD12 timeout error		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced
0	ACNE	Force Event Auto CMD12 not executed.		WO	0
		Write 0	NOINT No interrupt
		Write 1	INT Interrupt forced

:SDMMC:REV

Address offset	0x0000 02FC
Description	Revision register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy.
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	VREV	Vendor Version Number Bits 7 to 4 are the major revision, bits 3 to 0 are the minor revision. Examples: 0x10 for 1.0 and 0x21 for 2.1. Reset value is 0x31.		RO	0x33
		Read 0x00	MINIMUM Minimum value
		Read 0xFF	MAXIMUM Maximum value
23:16	SREV	Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4 bits indicate the version. 0h: SD Host Specification Version 1.00. 1h: SD Host Specification Version 2.00. 2h: SD Host Specification Version 3.00. 3h: Reserved		RO	0x02
		Read 0x00	MINIMUM Minimum value
		Read 0xFF	MAXIMUM Maximum value
15:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
0	SIS	Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all, the interrupt signal shall be deasserted and this status shall read 0.		RO	0
		Read 0	NOINT No interrupt is asserted
		Read 1	INT Interrupt is asserted

:SDMMC:TPSEL

Address offset	0x0000 1040
Description	Test-Port select.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	VAL	Test port 0 or 1		RW	0
		0	TEST_PORT1 Magillem Info : Information not available in the IP-XACT file
		1	TEST_PORT2 Magillem Info : Information not available in the IP-XACT file

:SDMMC:DMAMODE

Address offset	0x0000 1048
Description	DMA mode select: This register define the behavior of DMA request signal that allow tranmission of data.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	VAL	0h = In this case, DMA required to read/write data from VAL register, the value of DMAIND register is d'ont care and the trigger to transmit data from the internal FIFO defined by BLK.BLEN register as a threshold. 1h = DMA required to read/write data from BUFIF register the value of DMAIND define the trigger of the internal FIFO.		RW	1
		0	DISABLE Disable to trig the internal FIFO with threshold, using DMA indication instead
		1	ENABLE Enable to trig the internal FIFO with threshold

:SDMMC:DMAIND

Address offset	0x0000 1050
Description	DMA indication select: This register define the behavior of transmitting data from/to the card using DMA If DMAMODE =1, then the value of of this register is d'ont care, else it define the trigger of the internal FIFO
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	VAL	0h = IP transmit the data to/from the card after each DMA 'BLOCK' transmitted. In this case SDMMC.BLK.BLEN shoud be equal to HOST_DMA.JOB_CTRL_CH7.MEM_JOB_CTRL_CHAN_7_BLOCK_SIZE 1h = IP transmit the data to the card after each DMA 'JOB' transmitted. In this case SDMMC.BLK.BLEN shoud be equal to HOST_DMA.TRANS_CTRL_CH7.MEM_TRANS_CTRL_CHAN_7_TRANS_NUM_B		RW	1
		0	DMA_BLK The IP transmit the data to/from the card, after each DMA transmitted block.
		1	DMA_JOB The IP transmit the data to/from the card, only in the end of the DMA job.

:SDMMC:CLKSEL

Address offset	0x0000 1054
Description	This register define the functional clock frequency, and whether the clock is synchronized to main clock.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	VAL	0h = 40MHz post-swallowing 1h = 80MHz pro-swallowing		RW	0
		0	SYNC post-swallowing 40MHz clock to main clock
		1	ASYNC pre-swallowing 80MHz clock

:SDMMC:EVTMODE

Address offset	0x0000 10E0
Description	Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1:0	INT0CFG	Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]		RW	0x1
		0x0	DISABLE The interrupt or event line is disabled.
		0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

:SDMMC:DESC

Address offset	0x0000 10FC
Description	This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODULEID	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.		RO	0x2111
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	FEATURST	Feature Set for the module instance		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTNUM	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
7:4	MAJREV	Major rev of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor rev of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:SDMMC:SDMMCSTAT

Address offset	0x0000 1100
Description	SDMMC Status register
Type	RO

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0bxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0	STATE	SDMMC state indication		RO	X
		Read 0	NORMAL IP is active but is not transmitting
		Read 1	ACTIVE IP is active and transmitting

:SDMMC:BUFIF

Address offset	0x0000 1110
Description	SRAM Data Access Registers These registers are the 32-bit entry point of the SRAM buffer for read or write data transfers to and from the SDMMC card. Data[1] register is an alias for the SD_BUFIF register and needs to be used for normal (non safety, non burst) buffer accesses. Data[1..4] registers need to be used for non safety, incremental VBUSP burst accesses. For safety accesses (write with readback and double read), DataS[1..4] registers need to be used. The SRAM buffer size is 32bits x 256 (1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. If the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write.
Type	RW

Bits	Field Name	Description		Type	Reset
31:0	VAL	Buffer data register In functional mode (CON.MODE = FUNC): - a read access to this register is allowed only when the buffer read enable status is set to 1 (PSTATE.BREN), otherwise a bad access (STAT.BADA) is signaled. - a write access to this register is allowed only when the buffer write enable status is set to 1 (PSTATE.BWEN), otherwise a bad access (STAT.BADA) is signaled and the data is not written.		RW	0x0000 0000
		0xFFFF FFFF	MAXIMUM Maximum value
		0x0000 0000	MINIMUM Minimum value

:SDMMC:CLKCFG

Address offset	0x0000 4000
Description	Clock Enable Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	EN	Clock Disable / Enable for: * bus_clk (main clock) - 80MHz ; * card_clk (pll_clk) - 40MHz ; * lf_clk (slow_clk) - 32KHz ;	RW	0