RTC

This section provides information on the RTC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

**ULL** Real Time Clock module RTC includes 2 channels. - Channel 0 is a compare channel - Channel 1 is a capture channel INTERNAL_NOTE: [Functional Specification](https://confluence.itg.ti.com/display/LPRF/Loki+-+RTC+Functional+Spec) [Implementation Specification](https://confluence.itg.ti.com/display/LPRF/Loki+RTC-+Implementation+Spec)

RTC Registers Mapping Summary

:RTC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DESC	RO	32	0x6442 1010	0x0000 0000
CTL	RW	32	0x0000 0000	0x0000 0004
ARMSET	RW	32	0x0000 0000	0x0000 0008
ARMCLR	RW	32	0x0000 0000	0x0000 000C
TIME250N	RO	32	0x0000 0000	0x0000 0010
TIME1U	RO	32	0x0000 0000	0x0000 0014
TIME8U	RO	32	0x0000 0000	0x0000 0018
TIME524M	RO	32	0x0000 0000	0x0000 001C
CH0CC250N	RW	32	0x0000 0000	0x0000 0020
CH0CC1U	RW	32	0x0000 0000	0x0000 0024
CH0CC8U	RW	32	0x0000 0000	0x0000 0028
CH1CC8U	RO	32	0x0000 0000	0x0000 0038
CH1CFG	RW	32	0x0000 0000	0x0000 003C
IMASK	RW	32	0x0000 0000	0x0000 0044
RIS	RO	32	0x0000 0000	0x0000 0048
MIS	RO	32	0x0000 0000	0x0000 004C
ISET	RW	32	0x0000 0000	0x0000 0050
ICLR	RW	32	0x0000 0000	0x0000 0054
IMSET	RW	32	0x0000 0000	0x0000 0058
IMCLR	RW	32	0x0000 0000	0x0000 005C
EMU	RW	32	0x0000 0000	0x0000 0060
DTB	RW	32	0x0000 0000	0x0000 0064
DTIME	RW	32	0x0000 0000	0x0000 0068

RTC Instances Register Mapping Summary

RTC Register Descriptions

:RTC Common Register Descriptions

:RTC:DESC

Address offset	0x0000 0000
Description	Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	MODID	Module identifier used to uniquely identify this IP.	RO	0x6442
15:12	STDIPOFF	Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)	RO	0x1
11:8	INSTIDX	IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).	RO	0x0
7:4	MAJREV	Major revision of IP (0-15).	RO	0x1
3:0	MINREV	Minor revision of IP (0-15).	RO	0x0

:RTC:CTL

Address offset	0x0000 0004
Description	RTC Control register. This register controls resetting the of RTC counter
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	spare		RO	0x0000 0000
0	RST	RTC counter reset. Writing 1 to this bit will reset the RTC counter, and cause it to resume counting from 0x0		WO	0
		Write 0	NOEFF No effect
		Write 1	CLR Reset the timer.

:RTC:ARMSET

Address offset	0x0000 0008
Description	RTC channel mode set register. Read to each bit field of this register provides the current channel mode. - Read of 1'b0 indicates the channel is unarmed. - Read of 1'b1 indicates the channel is either in capture or compare mode. A write to each bitfield of this register the following effect: - Write of 1'b0 has no effect on channel mode. - Write of 1'b1 has no effect on the compare channel. While write of 1'b1 for capture channel will arm it in capture mode if it is disabled.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	CH1	Arming Channel 1 for capture operation.		RW	0
		0	NOEFF No effect on the channel
		1	SET Enable the Channel 1 for capture operation
0	CH0	No effect on arming the channel. Read will give the status of the Channel 0.		RW	0
		0	NOEFF No effect on the channel
		1	SET No effect on the compare channel

:RTC:ARMCLR

Address offset	0x0000 000C
Description	RTC channel mode clear register. Read to each bit field of this register provides the current channel mode. - Read of 1'b0 indicates the channel is unarmed. - Read of 1'b1 indicates the channel is either in capture or compare mode. A write to each bitfield of this register the following effect: - Write of 1'b0 has no effect on channel mode. - Write of 1'b1 for capture/compare channel will disarm it without triggering event unless a compare/capture event happens in the same cycle.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	CH1	Disarming Channel 1		RW	0
		0	NOEFF No effect on the channel
		1	CLR Set channel in UNARMED state without triggering event unless a capture event happens in the same cycle
0	CH0	Disarming Channel 0		RW	0
		0	NOEFF No effect on the channel
		1	CLR Set channel in UNARMED state without triggering event unless a compare event happens in the same cycle

:RTC:TIME250N

Address offset	0x0000 0010
Description	RTC Time value register. 32-bit unsigned integer representing [29:-2] time slice of the real time clock counter. The counter runs on LFCLK. This field has a resolution of 250ns, and range of about 17.8 minutes.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing [34:3]slice of real time counter.			RO	0x0000 0000

:RTC:TIME1U

Address offset	0x0000 0014
Description	RTC Time value register. 32-bit unsigned integer representing [31:0] time slice of the real time clock counter. The counter runs on LFCLK. This field has a resolution of 1us, and range of about 1.19 hours.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing [34:3]slice of real time counter.			RO	0x0000 0000

:RTC:TIME8U

Address offset	0x0000 0018
Description	RTC Time value register. 32-bit unsigned integer representing [34:3] time slice of the real time clock counter. The counter runs on LFCLK. This field has a resolution of 8us, and range of about 9.5 hours.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing [34:3]slice of real time counter.			RO	0x0000 0000

:RTC:TIME524M

Address offset	0x0000 001C
Description	RTC time value register. 32-bit unsigned integer representing [50:19] time slice of the real time clock counter. This field has a resolution of about 0.5s and a range of about 71.4 years.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing. [50:19]slice of real time counter.			RO	0x0000 0000

:RTC:CH0CC250N

Address offset	0x0000 0020
Description	Channel 0 compare value with 250ns resolution. A read to this register returns the value {CH0CC8U[29:3], 5b'0} A write to this register arms the channel in compare mode. Event would occur at the same time +/ Tlfclk/2 on the RTC as if it was written to SYSTIM.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.			RW	0x0000 0000

:RTC:CH0CC1U

Address offset	0x0000 0024
Description	Channel 0 compare value with 1us resolution. A read to this register returns the value {CH0CC8U[31:3], 3b'0} A write to this register arms the channel in compare mode. Event would occur at the same time +/ Tlfclk/2 on the RTC as if it was written to SYSTIM.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.			RW	0x0000 0000

:RTC:CH0CC8U

Address offset	0x0000 0028
Description	Channel 0 compare value. A write to this register automatically enables the channel to trigger an event when RTC timer reaches the programmed value or if the programmed value is 1 sec in the past.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.			RW	0x0000 0000

:RTC:CH1CC8U

Address offset	0x0000 0038
Description	Channel 1 capture value. This register captures the RTC time slice [34:3] on each selected edge of the capture event when the [ARMSET.CH1] = 1.
Type	RO

Bits	Field Name	Description	Type	Reset
31:21	Reserved	spare	RO	0x000
20:0	VAL	[TIME8U.VAL] captured value at the last selected edge of capture event.	RO	0x00 0000

:RTC:CH1CFG

Address offset	0x0000 003C
Description	Channel 1 configuration register. This register can be used to select the capture edge for generating the capture event.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	spare		RO	0x0000 0000
0	EDGE	Edge detect configuration for capture source		RW	0
		0	RISE Rising Edge.
		1	FALL Falling Edge.

:RTC:IMASK

Address offset	0x0000 0044
Description	Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Channel 1 Event Interrupt Mask.		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Enable Interrrupt Mask
0	EV0	Channel 0 Event Interrupt Mask.		RW	0
		0	DIS Disable Interrupt Mask
		1	EN Enable Interrupt Mask

:RTC:RIS

Address offset	0x0000 0048
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.] to [MIS.] when the corresponding bit-fields are set to 1.
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Raw interrupt status for Channel 1 event. This bit is set to 1 when a capture event is received on Channel 1. This bit will be cleared when the bit in [ICLR.EV1] is set to 1 or when the captured time value is read from the [CH1CC8U.*] register.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
0	EV0	Raw interrupt status for Channel 0 event. This bit is set to 1 when a compare event occurs on Channel 0. This bit will be cleared. When the corresponding bit in [ICLR.EV0] is set to 1. Or when a new compare value is written in [CH0CC8U.*] register		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured

:RTC:MIS

Address offset	0x0000 004C
Description	Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.] and RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Masked interrupt status for channel 1 event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
0	EV0	Masked interrupt status for channel 0 event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured

:RTC:ISET

Address offset	0x0000 0050
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Set Channel 1 event Interrupt.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt
0	EV0	Set Channel 0 event Interrupt.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Set interrupt

:RTC:ICLR

Address offset	0x0000 0054
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Clears channel 1 event interrupt.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	CLR Clear Interrupt
0	EV0	Clears channel 0 event interrupt.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	CLR Clear Interrupt.

:RTC:IMSET

Address offset	0x0000 0058
Description	Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Set channel 1 event interrupt mask.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	SET Set interrupt mask
0	EV0	Set channel 0 event interrupt mask.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	SET Set interrupt mask

:RTC:IMCLR

Address offset	0x0000 005C
Description	Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	spare		RO	0x0000 0000
1	EV1	Clears Channel 1 event interrupt mask.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	CLR Clear Interrupt Mask
0	EV0	Clears Channel 0 event interrupt mask.		WO	0
		Write 0	NO_EFF Writing 0 has no effect
		Write 1	CLR Clear Interrupt Mask

:RTC:EMU

Address offset	0x0000 0060
Description	Emulation control register. This register controls the behavior of the IP related to core halted input.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	spare		RO	0x0000 0000
0	HALT	Halt control.		RW	0
		0	RUN Free run option. The IP ignores the state of the core halted input.
		1	STOP Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption.

:RTC:DTB

Address offset	0x0000 0064
Description	Digital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	Reserved	spare		RO	0x000 0000
3:0	SEL	Digital test bus selection mux control. Non-zero select values output a 16 bit selected group of signals per value.		RW	0x0
		0x0	DIS All 16 observation signals are set to zero.

:RTC:DTIME

Address offset	0x0000 0068
Description	A delta time mechanism is implemented for RTC that allows the TIME value to be adjusted under software control. This is used by boot code to perform the compensation for reset duration (accomplished by adding MMR write to FCFG.generalTrims copylist to avoid ROM changes) DTIME format is: [31]: E (exponent) [30:0] M (mantissa) TIME[50:-2] is adjusted by TIME += sxt(M[30:0], 53) * 2^(22E). In other words: (E==0): TIME is adjusted by M 250 ns (range +/-134 s) (E==1): TIME is adjusted by M * 1.049 s (range +/- 35.7 yr)
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	Reserved	spare			RO	0x0000 0000