PDM

This section provides information on the PDM Module Instance within this product. Each of the registers within the Module Instance is described separately below.

Pulse Density Modulation. The IP takes in PDM samples and converts them to PCM samples.

PDM Registers Mapping Summary

:PDM Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DESC	RO	32	0x3342 1010	0x0000 0000
DESCEX	RO	32	0x0000 0001	0x0000 0004
IMASK	RW	32	0x0000 0000	0x0000 0044
RIS	RO	32	0x0000 0000	0x0000 0048
MIS	RO	32	0x0000 0000	0x0000 004C
ISET	WO	32	0x0000 0000	0x0000 0050
ICLR	WO	32	0x0000 0000	0x0000 0054
EMU	RW	32	0x0000 0000	0x0000 0060
CTL	RW	32	0x0000 0000	0x0000 0100
ICLKCTL	RW	32	0x0000 0000	0x0000 0104
FIFOCTL1	RW	32	0x0000 0000	0x0000 0108
FIFODATA	RO	32	0x0000 0000	0x0000 010C
CCTL	RW	32	0x0070 0000	0x0000 0110
OSR	RW	32	0x0000 003F	0x0000 0114
STA	RO	32	0x0000 0001	0x0000 0118
FIFOCTL2	RW	32	0x0000 0000	0x0000 0120
FIFOSR	RO	32	0x0000 4040	0x0000 0124
AVGVAL0	RO	32	0x0000 0000	0x0000 0200
PKVAL0	RO	32	0x0000 0000	0x0000 0204
AVGPOW0	RO	32	0x0000 0000	0x0000 0208
AVGVAL1	RO	32	0x0000 0000	0x0000 020C
PKVAL1	RO	32	0x0000 0000	0x0000 0210
AVGPOW1	RO	32	0x0000 0000	0x0000 0214
STPCTL	RW	32	0x0000 0000	0x0000 0300
STPXCAPT	RO	32	0x0000 0000	0x0000 0304
STPXPER	RO	32	0x0000 0000	0x0000 0308
STPSCAPT	RO	32	0x0000 0000	0x0000 030C
STPSPER	RW	32	0x0000 0000	0x0000 0310
STPINTRG	RW	32	0x0000 0000	0x0000 0314
STPSSET	RW	32	0x0000 0000	0x0000 0318
STPSADD	RW	32	0x0000 0000	0x0000 031C
STPXMIN	RW	32	0x0000 FFFF	0x0000 0320
STPWCNT	RO	32	0x0000 0000	0x0000 0324
STPXCNT	RO	32	0x0000 0000	0x0000 0328
STPSTAT	RO	32	0x0000 0000	0x0000 032C
CLKCFG	RW	32	0x0000 0000	0x0000 1000
ADFSCTL1	RW	32	0x0000 0000	0x0000 1004
ADFSCTL2	RW	32	0x0000 0000	0x0000 1008

PDM Instances Register Mapping Summary

PDM Register Descriptions

:PDM Common Register Descriptions

:PDM:DESC

Address offset	0x0000 0000
Description	Description Register This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODID	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.		RO	0x3342
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	STDIPOFF	Standard IP offset 64 Bit standard IP MMR block (beginning with aggregated IRQ registers) 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTIDX	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
7:4	MAJREV	Major revision of the IP		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor revision of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:PDM:DESCEX

Address offset	0x0000 0004
Description	This register reflects the configuration of this peripheral instance
Type	RO

Bits	Field Name	Description		Type	Reset
31:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
2:0	NUMCHAN	Number of available PDM Channels. Value 1 indicates two channels that can be used for stereo or dual mono microphone connections.		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0x7	MAXIMUM Highest possible value

:PDM:IMASK

Address offset	0x0000 0044
Description	Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in MIS.
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	DMADONE	DMA Done event mask.		RW	0
		0	CLR Interrupt disable
		1	SET Interrrupt Enable
8	STPTRIG	Samplestamp Trigger event mask		RW	0
		0	CLR Clear Interrupt Mask
		1	SET Interrrupt Enable
7	UNFL	Data Underflow event mask.		RW	0
		0	CLR Interrupt disable
		1	SET Interrrupt Enable
6	OVFL	Data Overflow event mask.		RW	0
		0	CLR Interrupt disable
		1	SET Interrrupt Enable
5:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	PDMDATA	PDM data event mask		RW	0
		0	CLR Interrupt disable
		1	SET Interrupt Enable

:PDM:RIS

Address offset	0x0000 0048
Description	Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	DMADONE	DMA Done event.		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
8	STPTRIG	Samplestamp Trigger event		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrrupt Enable
7	UNFL	Data Underflow event. Data has been read from an emty FIFO. This flag gets set if one of the channel UNDERFLOW flags gets set.		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
6	OVFL	Data Overflow event. Data has been written to the buffer before the previous values was read. This flag gets set if one of the channel OVERFLOW flags gets set		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
5:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	PDMDATA	PDM DATA event		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable

:PDM:MIS

Address offset	0x0000 004C
Description	Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	DMADONE	Masked DMA Done event.		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
8	STPTRIG	Masked Samplestamp Trigger event.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrrupt Enable
7	UNFL	Masked Data Underflow event.		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
6	OVFL	Masked Data Overflow event.		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable
5:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	PDMDATA	Masked PDMDATA event		RO	0
		Read 0	CLR Interrupt disable
		Read 1	SET Interrrupt Enable

:PDM:ISET

Address offset	0x0000 0050
Description	Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	DMADONE	Set DMA Done event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	SET Interrrupt Enable
8	STPTRIG	Set Samplestamp Trigger event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	SET Interrrupt Enable
7	UNFL	Set Data Underflow event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	SET Interrrupt Enable
6	OVFL	Set Data Overflow event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	SET Interrrupt Enable
5:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	PDMDATA	Set PDMDATA event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	SET Interrrupt Enable

:PDM:ICLR

Address offset	0x0000 0054
Description	Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	WO

Bits	Field Name	Description		Type	Reset
31:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	DMADONE	Clear DMA Done event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	CLR Interrrupt Enable
8	STPTRIG	Clear Samplestamp Trigger event.		WO	0
		Write 0	NO_EFFECT Writing 0 has no effect
		Write 1	CLR Interrrupt Enable
7	UNFL	Clear Data Underflow event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	CLR Interrrupt Enable
6	OVFL	Clear Data Overflow event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	CLR Interrrupt Enable
5:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
0	PDMDATA	Clear PDMDATA event.		WO	0
		Write 0	NO_EFFECT Interrupt disable
		Write 1	CLR Interrrupt Enable

:PDM:EMU

Address offset	0x0000 0060
Description	This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	HALT	Free run control		RW	0
		0	RUN The peripheral ignores the state of the Core Halted input
		1	STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.

:PDM:CTL

Address offset	0x0000 0100
Description	PDM control register
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	ENPDM	Enable conversion on PDM		RW	0
		0	DIS Disable Channel
		1	EN Enable Channel

:PDM:ICLKCTL

Address offset	0x0000 0104
Description	Input clock Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:17	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
16	BCLKEN	This bit is used to enable BCLK to Sigma-Delta Modulator on-chip.		RW	0
		0	DIS BCLK is disabled
		1	EN BCLK is enabled
15:10	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9:0	IDIV	Divider for ICLK iclk = PLLCLK/(ICLK +1)		RW	0x000
		0x000	MIN Minimum value of BDIV
		0x3FF	MAX Maximum value of BDIV

:PDM:FIFOCTL1

Address offset	0x0000 0108
Description	PDM FIFO control register
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	ENFIFO1	Enable FIFO1 for DMA access through the [FIFODATA] Register		RW	0
		0	DIS Disable Channel
		1	EN Enable Channel
0	ENFIFO0	Enable FIFO0 for DMA access through the [FIFODATA] Register		RW	0
		0	DIS Disable Channel
		1	EN Enable Channel

:PDM:FIFODATA

Address offset	0x0000 010C
Description	FIFO Data Register (FIFO read) This register provides the Data of the FIFO based on [FIFOCTL.ENFIFO0] and [FIFOCTL.ENFIFO1] This allows the DMA to just have single address to read all the FIFO content when triggered.
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VALUE	FIFO Read Register		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest possible value
		Read 0x0000 0000	MINIMUM Smallest value

:PDM:CCTL

Address offset	0x0000 0110
Description	PDM Channel control register
Type	RW

Bits	Field Name	Description		Type	Reset
31	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
30:29	CH1IPSEL	Channel 1 Data Input Select		RW	0x0
		0x0	DATA0 Data pin 0 selected as source for channel 1.
		0x1	DATA1 Data pin 1 selected as source for channel 1.
		0x2	SDM SDM output selected as source for channel 1.
		0x3	RESERVED1821101616161616161611616124241418321011111113 Data pin 0 selected as source for channel 1.
28	CH1CLKEG	Select the clock edge for data channel 1		RW	0
		0	RISING Rising edge is selected
		1	FALLING Failing edge is selected
27	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
26:25	CH0IPSEL	Channel 0 Data Input Select		RW	0x0
		0x0	DATA0 Data pin 0 selected as source for channel 0.
		0x1	DATA1 Data pin 1 selected as source for channel 0.
		0x2	SDM SDM output selected as source for channel 0.
		0x3	RESERVED1821101616161616161611616124241418321011111113 Data pin 0 selected as source for channel 0.
24	CH0CLKEG	Select the clock edge for data channel 0		RW	0
		0	RISING Rising edge is selected
		1	FALLING Failing edge is selected
23	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
22:20	SELSCALE	Select scaling factor for the averaging blocks. Selscale value used internally is 1/(2^(3+VALUE)) Ex: When value is 0, selscale is 1/8, and when value is 7, selscale is 1/1024		RW	0x7
		0x0	VAL0 Scaling factor is 1/8
		0x1	VAL1 Scaling factor is 1/16
		0x2	VAL2 Scaling factor is 1/32
		0x3	VAL3 Scaling factor is 1/64
		0x4	VAL4 Scaling factor is 1/128
		0x5	VAL5 Scaling factor is 1/256
		0x6	VAL6 Scaling factor is 1/512
		0x7	VAL7 Scaling factor is 1/1024
19	ENPOWCH1	Enables average power calculation for channel-1		RW	0
		0	DIS Enables average power calculation for channel-1
		1	EN Enables average power calculation for channel-1
18	ENPOWCH0	Enables average power calculation for channel-0		RW	0
		0	DIS Disables average power calculation for channel-0
		1	EN Enables average power calculation for channel-0
17	ENPKCH1	Enables peak value detection for channel-0		RW	0
		0	DIS Enables peak value detection for channel-1
		1	EN Enables peak value detection for channel-1
16	ENPKCH0	Enables peak value detection for channel-0		RW	0
		0	DIS Disables peak value detection for channel-0
		1	EN Enables peak value detection for channel-0
15:12	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
11	DATAFMT	Data Format		RW	0
		0	OFFSET Offset binary
		1	TWOSCOMP Twos complement
10	ALIGN	Data alignment		RW	0
		0	RIGHT Right-aligned. LSB of filter output is bit 0.
		1	LEFT Left-aligned. MSB of filter output (depending on OSR) is bit 31.
9:8	DFS	Digital Filter Select		RW	0x0
		0x0	SINC1 SINC1 filter
		0x1	SINC2 SINC2 filter
		0x2	SINC3 SINC3 filter
		0x3	SINC4 SINC4 filter
7:3	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
2:0	CHEN	Data Input Configuration		RW	0x0
		0x0	DISABLE Both Channels are disabled.
		0x1	CH0ENABLE Input channel 0 is enabled.
		0x2	CH0_1ENABLE Input channel 1 is enabled.
		0x4	MANC Input from Manchester Decoder, also enables Manchester Coding of bitstream. CH0 is enabled by default as the operation and CH1 enable bit is discarded.

:PDM:OSR

Address offset	0x0000 0114
Description	Oversampling Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
7:0	VALUE	Oversampling rate. The oversampling rate is defined as OSRx + 1. Applicable oversampling rates are 2 to 256. Default is 64.		RW	0x3F
		0x01	MINIMUM Smallest value
		0xFF	MAXIMUM Highest possible value

:PDM:STA

Address offset	0x0000 0118
Description	PDM control register
Type	RO

Bits	Field Name	Description		Type	Reset
31:18	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
17	MANCLK	Manchester Clock status. Indicates that Manchester mode is in locked mode or not.		RO	0
		Read 0	UNLOCKED Manchester clock not locked.
		Read 1	LOCKED Manchester clock locked.
16:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
0	AGCRDY	AGC accelerator ready status. Software must read AGCVALx, PKVALx and AVGPOWx registers only when AGCRDY is '1'. Reading these registers while AGCRDY is 0 may provide incorrect values.		RO	1
		Read 0	NOT_RDY Not ready
		Read 1	RDY Ready

:PDM:FIFOCTL2

Address offset	0x0000 0120
Description	FIFO Control
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
7	FIFOFLSH	FIFO Flush Setting this bit will Flush the FIFO. This bit will self-clear when the flush has completed.		RW	0
		0	NOFLUSH Do not Flush FIFO
		1	FLUSH Flush FIFO
6:4	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
3:0	TRGLVL	FIFO Trigger Level Select Sets the trigger points for the FIFO events. Note: FIFO depth is only 2 the level 1/4 and 3/4 default to 1/2.		RW	0x0
		0x0	LEVEL_1 Trigger when RX FIFO contains >= 1 byte
		0x1	LEVEL_2 Trigger when RX FIFO contains >= 2 byte
		0x2	LEVEL_3 Trigger when RX FIFO contains >= 3 byte
		0x3	LEVEL_4 Trigger when RX FIFO contains >= 4 byte
		0x4	LEVEL_5 Trigger when RX FIFO contains >= 5 byte
		0x5	LEVEL_6 Trigger when RX FIFO contains >= 6 byte
		0x6	LEVEL_7 Trigger when RX FIFO contains >= 7 byte
		0x7	LEVEL_8 Trigger when RX FIFO contains >= 8 byte
		0x8	LEVEL_9 Trigger when RX FIFO contains >= 9 byte
		0x9	LEVEL_10 Trigger when RX FIFO contains >= 10 byte
		0xA	LEVEL_11 Trigger when RX FIFO contains >= 11 byte
		0xB	LEVEL_12 Trigger when RX FIFO contains >= 12 byte

:PDM:FIFOSR

Address offset	0x0000 0124
Description	FIFO Status Register.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15	CH1FFULL	CH1 FIFO Full		RO	0
		Read 0	CLEARED The transmitter is not full.
		Read 1	SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
14	CH1FEMP	CH1 FIFO Empty		RO	1
		Read 0	CLEARED The transmitter has data to transmit.
		Read 1	SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
13:12	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
11:8	CH1FCNT	Number of Bytes which could be read from the CH1 FIFO		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
7	CH0FFULL	CH0 FIFO Full		RO	0
		Read 0	CLEARED The receiver can receive data.
		Read 1	SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full.
6	CH0FEMP	CH0 FIFO Empty		RO	1
		Read 0	CLEARED The receiver is not empty.
		Read 1	SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
5:4	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
3:0	CH0FCNT	Number of Bytes which could be read from the CH0 FIFO		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:PDM:AVGVAL0

Address offset	0x0000 0200
Description	Average sample value for channel-0, 32-bit register.
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VALUE	Average sample value for channel-0		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest value
		Read 0x0000 0000	MINIMUM Minimum value of register

:PDM:PKVAL0

Address offset	0x0000 0204
Description	Peak sample value for channel-0
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
23:0	VALUE	Peak sample value for channel-0. Bits [22:0] applicable for operation in 2's complement format and bits [23:0] applicable for operation in offset binary format.		RO	0x00 0000
		Read 0x00 0000	MINIMUM Smallest value
		Read 0x7F FFFF	MAXIMUM Largest value

:PDM:AVGPOW0

Address offset	0x0000 0208
Description	Average sample power for channel-0
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VALUE	Average sample power for channel-0		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest value
		Read 0x0000 0000	MINIMUM Smallest value

:PDM:AVGVAL1

Address offset	0x0000 020C
Description	Average sample value for channel-1, 32-bit register.
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VALUE	Average sample value for channel-1		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest value
		Read 0x0000 0000	MINIMUM Minimum value of register

:PDM:PKVAL1

Address offset	0x0000 0210
Description	Peak sample value for channel-1
Type	RO

Bits	Field Name	Description		Type	Reset
31:24	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
23:0	VALUE	Peak sample value for channel-1. Bits [22:0] applicable for operation in 2's complement format and bits [23:0] applicable for operation in offset binary format.		RO	0x00 0000
		Read 0x00 0000	MINIMUM Smallest value
		Read 0x7F FFFF	MAXIMUM Largest value

:PDM:AVGPOW1

Address offset	0x0000 0214
Description	Average sample power for channel-1
Type	RO

Bits	Field Name	Description		Type	Reset
31:0	VALUE	Average sample power for channel-1		RO	0x0000 0000
		Read 0xFFFF FFFF	MAXIMUM Highest value
		Read 0x0000 0000	MINIMUM Smallest value

:PDM:STPCTL

Address offset	0x0000 0300
Description	Samplestamp Generator Control Register
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	STPEN	Enables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.;When cleared, all samplestamp generator counters and capture values are cleared.		RW	0
		0	DIS Disable the samplestamp generator
		1	EN Enable the samplestamp generator

:PDM:STPXCAPT

Address offset	0x0000 0304
Description	Captured REFCLK Counter Value, Capture Channel 0
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	CAPTVAL	The value of the samplestamp XOSC counter [STMPXCNT.CURR_VALUE] last time an event was pulsed. The value is cleared when [STMPCTL.STMP_EN] = 0. Note: When calculating the fractional part of the sample stamp, [STMPXPER] may be less than this bit field.		RO	0x0000
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value

:PDM:STPXPER

Address offset	0x0000 0308
Description	REFCLK Period Value
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	VALUE	The number of REFCLK clock cycles in the previous Sample Clock period (that is - the next value of the REFCLK counter at the positive Sample Clock edge, had it not been reset to 0).;The value is cleared when [STMPCTL.STMP_EN] = 0.		RO	0x0000
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value

:PDM:STPSCAPT

Address offset	0x0000 030C
Description	Captured Sample Clock Counter Value, Capture Channel 0
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	CAPTVAL	The value of the samplestamp Sample Clock counter [STMPWCNT.CURR_VALUE] last time an event was pulsed. This number corresponds to the number of positive Sample Clock edges since the samplestamp generator was enabled;The value is cleared when [STMPCTL.STPEN] = 0.		RO	0x0000
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value

:PDM:STPSPER

Address offset	0x0000 0310
Description	Sample Clock Counter Period Value
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	VALUE	Used to define when [STMPWCNT] is to be reset so number of Sample Clock edges are found for the size of the sample buffer. This is thus a modulo value for the Sample Clock counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).		RW	0x0000
		0x0000	MINIMUM Smallest value
		0xFFFF	MAXIMUM Highest possible value

:PDM:STPINTRG

Address offset	0x0000 0314
Description	WS Counter Trigger Value for Input Pins
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	INSTRWCT	In Start W Count Compare value used to start the incoming audio streams.;This bit field must equal the Sample Clock counter value during the Sample Clock period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer).;The value of this register takes effect when at least 32 PDMxCLK cycle ticks have happened.;Note: To avoid false triggers, this bit field must be set higher than [STPSPER.VALUE].		RW	0x0000
		0x0000	MINIMUM Smallest value
		0xFFFF	MAXIMUM Highest possible value

:PDM:STPSSET

Address offset	0x0000 0318
Description	Sample Clock Counter Set Operation
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	VALUE	Sample Clock counter modification: Sets the running Sample Clock counter equal to the written value.		RW	0x0000
		0x0000	MINIMUM Smallest value
		0xFFFF	MAXIMUM Highest possible value

:PDM:STPSADD

Address offset	0x0000 031C
Description	Sample Clock Counter Add Operation
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	VALINC	Sample Clock counter modification: Adds the written value to the running Sample Clock counter. If a positive edge of Sample Clock occurs at the same time as the operation, this will be taken into account.;To add a negative value, write "[STMPWPER.VALUE] - value".;		RW	0x0000
		0x0000	MINIMUM Smallest value
		0xFFFF	MAXIMUM Highest possible value

:PDM:STPXMIN

Address offset	0x0000 0320
Description	REFCLK Minimum Period Value;Minimum Value of [STPXPER]
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	VALUE	Each time [STMPXPER] is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.;When written, the register is reset to 0xFFFF (65535), regardless of the value written.;The minimum value can be used to detect extra Sample Clock pulses (this registers value will be significantly smaller than [STMPXPER.VALUE]).		RW	0xFFFF
		0x0000	MINIMUM Smallest value
		0xFFFF	MAXIMUM Highest possible value

:PDM:STPWCNT

Address offset	0x0000 0324
Description	Current Value of sample clock count This register is reset when [STPCTL.STPEN] = 0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	CURRVAL	Current value of the Sample Clock counter		RO	0x0000
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value

:PDM:STPXCNT

Address offset	0x0000 0328
Description	Current Value of XCNT This register is reset when [STPCTL.STPEN] = 0.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:0	CURRVAL	Current value of the REFCLK counter, latched when reading [STMPWCNT].		RO	0x0000
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value

:PDM:STPSTAT

Address offset	0x0000 032C
Description	Samplestamp Generator Status Register
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	INRDY	Low until the input pins are ready to be started by the samplestamp generator. When started (that is [STMPINTRIG] equals the WCLK counter) the bit goes back low.		RO	0
		Read 0	CLR Clear
		Read 1	SET Set
0	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0

:PDM:CLKCFG

Address offset	0x0000 1000
Description	Clock configuration register Note: Disable the [CLKCFG.MEM_CLK_EN] and [CLKCFG.ADFS_EN] to change [CLK_CFG.MEM_CLK_SEL] or [ADFS_CTRL1]/[ADFS_CTRL2] After changing [CLK_CFG.MEM_CLK_SEL] or [ADFS_CTRL1]/[ADFS_CTRL2], enable [CLKCFG.ADFS_EN] followed by [CLKCFG.MEM_CLK_EN]
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
7	ADFSEN	ADFS Enable bit		RW	0
		0	DIS Disable ADFS
		1	EN Enable ADFS
6:4	CLKSEL	Clock Select		RW	0x0
		0x0	SEL_0 No Clock
		0x1	SEL_1 SOC Clock(80MHz)
		0x2	SEL_2 SOC PLL Clock(un-swallowed 80MHz)
		0x3	SEL_3 HFXT
3:1	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
0	CLKEN	Clock enable		RW	0
		0	DIS Disable Clock
		1	EN Enable Clock

:PDM:ADFSCTL1

Address offset	0x0000 1004
Description	ADFS control register
Type	RW

Bits	Field Name	Description	Type	Reset
31:21	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x000
20:0	TREF	Reference clock time period	RW	0x00 0000

:PDM:ADFSCTL2

Address offset	0x0000 1008
Description	ADFS control register 2
Type	RW

Bits	Field Name	Description		Type	Reset
31:30	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
29:20	DIV	Value of divider to be used for ADFS		RW	0x000
19:18	Reserved	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
17	DLTASIGN	Sign of delta value to be used.		RW	0
		0	POS Positive Sign
		1	NEG Negative sign
16:0	DELTA	Difference in time periods of (reference clk/divisor) and required clock		RW	0x0 0000