31

IDLE

Serial interface and low level SPI pipeline is IDLE: This is a STAUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal.

RO

1

30

DUAL_BYTE_OPCODE_EN

Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device is configured to work in another SPI Mode. If enabled, the supplementing bytes are taken from Opcode Extension Register (Lower) and from Opcode Extension Register (Upper).

RW

0

29

CRC_EN

CRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode.

RW

0

28:26

RESERVED

RO

0x0

25

PIPELINE_PHY

Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise.

RW

1

24

EN_DTR_PROTOCOL

Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol.

RW

0

23

EN_AHB_DECODER

Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active slave is selected based on actual AHB address (the partition for each device is calculated with respect to bits [28:21] of Device Size Configuration Register)

RW

0

22:19

MSTR_BAUD_DIV

Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor. The baud rate is the clock rate divided by 2 multiplied by (Divisor + 1). Meaning, when Divisor Value is set to 0,1,2,..15 it sets the baud rate is the clock rate divided by 2, 4, 6,..32 respectively

RW

0x1

18

ENTER_XIP_MODE_IMM

Enter XIP Mode immediately: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the external device wakes up in XIP mode (as per the contents of its non- volatile configuration register). The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited.

RW

0

17

ENTER_XIP_MODE

Enter XIP Mode on next READ: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then setting to ?1? will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited.

RW

0

16

ENB_AHB_ADDR_REMAP

Enable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1, the incoming AHB address will be adapted and sent to the FLASH device as (address + N), where N is the value stored in the remap address register.

RW

0

15

ENB_DMA_IF

Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable

RW

0

14

WR_PROT_FLASH

Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary.

RW

0

13:10

PERIPH_CS_LINES

Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]

RW

0x0

9

PERIPH_SEL_DEC

Peripheral select decode:

RW

0

8

ENB_LEGACY_IP_MODE

Legacy IP Mode Enable:

RW

0

7

ENB_DIR_ACC_CTLR

Enable Direct Access Controller:

RW

1

6

RESET_CFG

RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)

RW

0

5

RESET_PIN

Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature

RW

0

4

HOLD_PIN

Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature

RW

0

3

PHY_MODE_EN

PHY mode enable: When enabled, the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module.

RW

0

2

SEL_CLK_PHASE

Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word.

RW

0

1

SEL_CLK_POL

Clock polarity outside SPI word:

RW

0

0

ENB_SPI

Octal-SPI Enable:

RW

1

31:29

RESERVED_4

RO

0x0

28:24

DUMMY_RD_CLK_CYCLES

Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction.

RW

0x00

23:21

RESERVED_3

RO

0x0

20

MODE_BIT_EN

Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.

RW

0

19:18

RESERVED_2

RO

0x0

17:16

DATA_XFER_TYPE_EXT_MODE

Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs.

RW

0x0

15:14

RESERVED

RO

0x0

13:12

ADDR_XFER_TYPE_STD_MODE

Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0]

RW

0x0

11

PRED_DIS

Predicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode

RW

0

10

DDR_EN

DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands

RW

0

9:8

INSTR_TYPE

Instruction Type:
0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only)
1 : Use DIO-SPI mode (Instructions always sent on DQ0 and DQ1)
2 : Use QIO-SPI mode (Instructions always sent on DQ0, DQ1, DQ2 and DQ3)
3 : Use Octal-IO-SPI mode (Instructions always sent on DQ[7:0])

RW

0x0

7:0

RD_OPCODE_NON_XIP

Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode

RW

0x03

31:29

RESERVED_4

RO

0x0

28:24

DUMMY_WR_CLK_CYCLES

Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction.

RW

0x00

23:18

RESERVED_3

RO

0x00

17:16

DATA_XFER_TYPE_EXT_MODE

Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs.

RW

0x0

15:14

RESERVED_2

RO

0x0

13:12

ADDR_XFER_TYPE_STD_MODE

Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0]

RW

0x0

11:9

RESERVED

RO

0x0

8

WEL_DIS

WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC

RW

0

7:0

WR_OPCODE

Write Opcode

RW

0x02

31:24

D_NSS

Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period.

RW

0x00

23:16

D_BTWN

Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty.

RW

0x00

15:8

D_AFTER

Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default, the chip select will be deasserted on the cycle following the completion of the current transaction.

RW

0x00

7:0

D_INIT

Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer.

RW

0x00

31:20

RESERVED_3

RO

0x000

19:16

DDR_READ_DELAY

DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored.

RW

0x0

15:9

RESERVED_2

RO

0x00

8

DQS_EN

DQS enable bit: If enabled, signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk..

RW

0

7:6

RESERVED

RO

0x0

5

SAMPLE_EDGE_SEL

Sample edge selection: Choose edge on which data outputs from flash memory will be sampled

RW

0

4:1

DELAY

Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles

RW

0x0

0

BYPASS

Bypass the adapted loopback clock circuit

RW

1

31:29

RESERVED

RO

0x0

28:27

MEM_SIZE_ON_CS3

Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.

RW

0x0

26:25

MEM_SIZE_ON_CS2

Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.

RW

0x0

24:23

MEM_SIZE_ON_CS1

Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.

RW

0x0

22:21

MEM_SIZE_ON_CS0

Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.

RW

0x0

20:16

BYTES_PER_SUBSECTOR

Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number.

RW

0x10

15:4

BYTES_PER_DEVICE_PAGE

Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries.

RW

0x100

3:0

NUM_ADDR_BYTES

Number of address bytes. A value of 0 indicates 1 byte.

RW

0x2

31:8

RESERVED

RO

0x00 0000

7:0

THRESHOLD

Defines the size of the indirect read partition in the SRAM,
in units of SRAM locations. By default, half of the SRAM is
reserved for indirect read operation, and half for indirect write.
The size of this register will scale with the depth of the SRAM.

RW

0x80

31:0

ADDR

This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM.

RW

0x0000 0000

31:12

RESERVED_2

RO

0x0 0000

11:8

NUM_BURST_REQ_BYTES

Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**(value in this register) which will simplify implementation.

RW

0x0

7:4

RESERVED

RO

0x0

3:0

NUM_SINGLE_REQ_BYTES

Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**(value in this register) which will simplify implementation.

RW

0x0

31:0

VALUE

This register is used to remap an incoming AHB address to a different address used by the FLASH device.

RW

0x0000 0000

31:24

RX_CRC_DATA_LOW

RX CRC data (lower) The first CRC byte returned after RX data chunk.

RO

0x00

23:16

RX_CRC_DATA_UP

RX CRC data (upper) The second CRC byte returned after RX data chunk.

RO

0x00

15

CRC_OUT_EN

CRC# output enable bit When enabled, the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly.

RW

0

14:11

RESERVED

RO

0x0

10:8

CHUNK_SIZE

It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers.

RW

0x2

7:0

MODE

These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled.

RW

0x00

31:16

SRAM_FILL_INDAC_WRITE

SRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition

RO

0x0000

15:0

SRAM_FILL_INDAC_READ

SRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition

RO

0x0000

31:5

RESERVED

RO

0x000 0000

4:0

LEVEL

Defines the level at which the small TX FIFO not full interrupt is generated

RW

0x01

31:5

RESERVED

RO

0x000 0000

4:0

LEVEL

Defines the level at which the small RX FIFO not empty interrupt is generated

RW

0x01

31:24

POLL_REP_DELAY

Defines additional delay for maintain Chip Select de-asserted during auto-polling phase

RW

0x00

23:16

POLL_COUNT

Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register.

RW

0x04

15

EN_POLLING_EXP

Set to '1' for enabling auto-polling expiration.

RW

0

14

DISABLE_POLLING

This switches off the automatic polling function

RW

0

13

POLLING_POLARITY

Defines the polling polarity. If '1', then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0', then the write transfer to the device will be complete if the polled bit is equal to '0'.

RW

0

12

RESERVED

RO

0

11

POLLING_ADDR_EN

Enables address phase of auto-polling (Read Status) command.

RW

0

10:8

POLLING_BIT_INDEX

Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for.

RW

0x0

7:0

OPCODE

Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default, this will poll the standard device STAUS register using opcode 0x05

RW

0x05

31:0

NO_OF_POLLS_BEF_EXP

Number of polls cycles before expiration

RW

0xFFFF FFFF

31:20

RESERVED_2

RO

0x000

19

ECC_FAIL

ECC failure This interrupt informs the system that Flash Device reported ECC error.

RW

0

18

TX_CRC_CHUNK_BRK

TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk.

RW

0

17

RX_CRC_DATA_VAL

RX CRC data valid New RX CRC data was captured from Flash Device

RW

0

16

RX_CRC_DATA_ERR

RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller.

RW

0

15

RESERVED

RO

0

14

STIG_REQ_INT

The controller is ready for getting another STIG request.

RW

0

13

POLL_EXP_INT

The maximum number of programmed polls cycles is expired

RW

0

12

INDRD_SRAM_FULL

Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation

RW

0

11

RX_FIFO_FULL

Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode

RW

0

10

RX_FIFO_NOT_EMPTY

Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode

RW

0

9

TX_FIFO_FULL

Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode

RW

0

8

TX_FIFO_NOT_FULL

Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode

RW

0

7

RECV_OVERFLOW

Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set.

RW

0

6

INDIRECT_XFER_LEVEL_BREACH

Indirect Transfer Watermark Level Breached

RW

0

5

ILLEGAL_ACCESS_DET

Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger.

RW

0

4

PROT_WR_ATTEMPT

Write to protected area was attempted and rejected.

RW

0

3

INDIRECT_TRANSFER_REJECT

Indirect operation was requested but could not be accepted. Two indirect operations already in storage.

RW

0

2

INDIRECT_OP_DONE

Indirect Operation Complete: Controller has completed last triggered indirect operation

RW

0

1

UNDERFLOW_DET

Underflow Detected:

RW

0

0

MODE_M_FAIL

Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read.

RW

0

31:20

RESERVED_2

RO

0x000

19

ECC_FAIL_MASK

ECC failure Mask

RW

0

18

TX_CRC_CHUNK_BRK_MASK

TX CRC chunk was broken Mask

RW

0

17

RX_CRC_DATA_VAL_MASK

RX CRC data valid Mask

RW

0

16

RX_CRC_DATA_ERR_MASK

RX CRC data error Mask

RW

0

15

RESERVED

RO

0

14

STIG_REQ_MASK

STIG request completion Mask

RW

0

13

POLL_EXP_INT_MASK

Polling expiration detected Mask

RW

0

12

INDRD_SRAM_FULL_MASK

Indirect Read Partition overflow mask

RW

0

11

RX_FIFO_FULL_MASK

Small RX FIFO full Mask

RW

0

10

RX_FIFO_NOT_EMPTY_MASK

Small RX FIFO not empty Mask

RW

0

9

TX_FIFO_FULL_MASK

Small TX FIFO full Mask

RW

0

8

TX_FIFO_NOT_FULL_MASK

Small TX FIFO not full Mask

RW

0

7

RECV_OVERFLOW_MASK

Receive Overflow Mask

RW

0

6

INDIRECT_XFER_LEVEL_BREACH_MASK

Transfer Watermark Breach Mask

RW

0

5

ILLEGAL_ACCESS_DET_MASK

Illegal Access Detected Mask

RW

0

4

PROT_WR_ATTEMPT_MASK

Protected Area Write Attempt Mask

RW

0

3

INDIRECT_TRANSFER_REJECT_MASK

Indirect Read Reject Mask

RW

0

2

INDIRECT_OP_DONE_MASK

Indirect Complete Mask

RW

0

1

UNDERFLOW_DET_MASK

Underflow Detected Mask

RW

0

0

MODE_M_FAIL_MASK

Mode M Failure Mask

RW

0

31:0

SUBSECTOR

The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register.

RW

0x0000 0000

31:0

SUBSECTOR

The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register.

RW

0x0000 0000

31:2

RESERVED

RO

0x0000 0000

1

ENB

Write Protection Enable Bit: When set to 1, any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source triggered. When set to 0, the protection region is disabled.

RW

0

0

INV

Write Protection Inversion Bit: When set to 1, the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0, the protection region defined in the lower and upper write protection registers is the region that the system is not permitted to write to.

RW

0

31:8

RESERVED

RO

0x00 0000

7:6

NUM_IND_OPS_DONE

This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it.

RO

0x0

5

IND_OPS_DONE_STAUS

Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.

RW

0

4

RD_QUEUED

Two indirect read operations have been queued

RO

0

3

SRAM_FULL

SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\"; indirect operation (status)

RW

0

2

RD_STAUS

Indirect Read Status: Indirect read operation in progress (status)

RO

0

1

CANCEL

Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations.

WO

0

0

START

Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation.

WO

0

31:0

LEVEL

Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark, an interrupt is also generated. This field can be disabled by writing a value of all zeroes.

RW

0x0000 0000

31:0

ADDR

This is the start address from which the indirect access will commence its READ operation.

RW

0x0000 0000

31:0

VALUE

This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM.

RW

0x0000 0000

31:8

RESERVED_2

RO

0x00 0000

7:6

NUM_IND_OPS_DONE

This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it.

RO

0x0

5

IND_OPS_DONE_STAUS

Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.

RW

0

4

WR_QUEUED

Two indirect write operations have been queued

RO

0

3

RESERVED

RO

0

2

WR_STAUS

Indirect Write Status: Indirect write operation in progress (status)

RO

0

1

CANCEL

Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations.

WO

0

0

START

Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation.

WO

0

31:0

LEVEL

Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark, an interrupt is also generated. This field can be disabled by writing a value of all ones.

RW

0xFFFF FFFF

31:0

ADDR

Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation.

RW

0x0000 0000

31:0

VALUE

Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM.

RW

0x0000 0000

31:4

RESERVED

RO

0x000 0000

3:0

IND_RANGE_WIDTH

This is the address offset of Indirect Trigger Address Register.

RW

0x4

31:29

RESERVED_3

RO

0x0

28:20

MEM_BANK_ADDR

The address of the Memory Bank which data will be read from.

RW

0x000

19

RESERVED_2

RO

0

18:16

NB_OF_STIG_READ_BYTES

It defines the number of read bytes for the extended STIG.

RW

0x0

15:8

MEM_BANK_READ_DATA

Last requested data from the STIG Memory Bank.

RO

0x00

7:2

RESERVED

RO

0x00

1

MEM_BANK_REQ_IN_PROGRESS

Memory Bank data request in progress.

RO

0

0

TRIGGER_MEM_BANK_REQ

Trigger the Memory Bank data request.

WO

0

31:24

CMD_OPCODE

Command Opcode: The command opcode field should be setup before triggering the command. For example, 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 2'b00, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 2'b01, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.

RW

0x00

23

ENB_READ_DATA

Read Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device.

RW

0

22:20

NUM_RD_DATA_BYTES

Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes.

RW

0x0

19

ENB_COMD_ADDR

Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field.

RW

0

18

ENB_MODE_BIT

Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.

RW

0

17:16

NUM_ADDR_BYTES

Number of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDR REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes

RW

0x0

15

ENB_WRITE_DATA

Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device.

RW

0

14:12

NUM_WR_DATA_BYTES

Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for 8 bytes.

RW

0x0

11:7

NUM_DUMMY_CYCLES

Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register.

RW

0x00

6:3

CMD_GEN_FSM_STAE

CMD_GEN_FSM_STAE ?is used to define the ?Polling flag?:?
If (CMD_GEN_FSM_STAE[6:3] = 0x7 or 0x8 or 0xa or 0xb? ?) then ?Polling_flag?=1
Usage: In order to make sure a write to external device was done and ended successfully, ?following condition should be met:
?Command execution in progress? (FLASH_CMD_CTRL.CMD_EXEC_STAUS) = 0 ?AND ?Polling flag? is ?0?.
Design NOTE: Command gen FSM polling states are:
????? CMD_GEN_FSM_STAE == POLL_STAUS_AFTER_WRITE? ?(0x7)
????? CMD_GEN_FSM_STAE == POLL_STAUS_AFTER_WRITE2 ?(0x8)
????? CMD_GEN_FSM_STAE == POLL_STAUS_WAIT ?(0xb)
????? CMD_GEN_FSM_STAE == LET_TXFIFO_EMPTY ??(0xa)

RO

0x0

2

STIG_MEM_BANK_EN

STIG Memory Bank enable bit.

RW

0

1

CMD_EXEC_STAUS

Command execution in progress.

RO

0

0

CMD_EXEC

Execute the command.

WO

0

31:0

ADDR

Command Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control register.

RW

0x0000 0000

31:0

DATA

This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.

RO

0x0000 0000

31:0

DATA

This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.

RO

0x0000 0000

31:0

DATA

Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register.

RW

0x0000 0000

31:0

DATA

Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register.

RW

0x0000 0000