IOMUX

This section provides information on the IOMUX Module Instance within this product. Each of the registers within the Module Instance is described separately below.

IOMUX Registers Mapping Summary

:IOMUX Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
CTL0_SLOW_CLOCK_IN	RW	32	0x0000 0800	0x0000 0000
CTL1_SLOW_CLOCK_IN	RW	32	0x0000 0002	0x0000 0004
CTL2_SLOW_CLOCK_IN	RW	32	0x0000 0000	0x0000 0008
CTL3_SLOW_CLOCK_IN	RW	32	0x0000 0000	0x0000 000C
CTL0_LFXTAL_N	RW	32	0x0000 1200	0x0000 1000
CTL1_LFXTAL_N	RW	32	0x0000 0002	0x0000 1004
CTL2_LFXTAL_N	RW	32	0x0000 0000	0x0000 1008
CTL3_LFXTAL_N	RW	32	0x0000 0000	0x0000 100C
CTL0_GPIO2	RW	32	0x0000 1200	0x0000 2000
CTL1_GPIO2	RW	32	0x0000 0001	0x0000 2004
CTL2_GPIO2	RW	32	0x0000 0000	0x0000 2008
CTL3_GPIO2	RW	32	0x0000 0000	0x0000 200C
CTL0_GPIO3	RW	32	0x0000 1200	0x0000 3000
CTL1_GPIO3	RW	32	0x0000 0001	0x0000 3004
CTL2_GPIO3	RW	32	0x0000 0000	0x0000 3008
CTL3_GPIO3	RW	32	0x0000 0000	0x0000 300C
CTL0_GPIO4	RW	32	0x0000 1200	0x0000 4000
CTL1_GPIO4	RW	32	0x0000 0001	0x0000 4004
CTL2_GPIO4	RW	32	0x0000 0000	0x0000 4008
CTL3_GPIO4	RW	32	0x0000 0000	0x0000 400C
CTL0_GPIO5	RW	32	0x0000 1200	0x0000 5000
CTL1_GPIO5	RW	32	0x0000 0001	0x0000 5004
CTL2_GPIO5	RW	32	0x0000 0000	0x0000 5008
CTL3_GPIO5	RW	32	0x0000 0000	0x0000 500C
CTL0_GPIO6	RW	32	0x0000 1200	0x0000 6000
CTL1_GPIO6	RW	32	0x0000 0001	0x0000 6004
CTL2_GPIO6	RW	32	0x0000 0000	0x0000 6008
CTL3_GPIO6	RW	32	0x0000 0000	0x0000 600C
CTL0_SWDIO	RW	32	0x0000 1800	0x0000 7000
CTL1_SWDIO	RW	32	0x0000 0001	0x0000 7004
CTL2_SWDIO	RW	32	0x0000 0000	0x0000 7008
CTL3_SWDIO	RW	32	0x0000 0000	0x0000 700C
CTL0_SWCLK	RW	32	0x0000 1800	0x0000 8000
CTL1_SWCLK	RW	32	0x0000 0002	0x0000 8004
CTL2_SWCLK	RW	32	0x0000 0000	0x0000 8008
CTL3_SWCLK	RW	32	0x0000 0000	0x0000 800C
CTL0_LOGGER	RW	32	0x0000 1800	0x0000 9000
CTL1_LOGGER	RW	32	0x0000 0001	0x0000 9004
CTL2_LOGGER	RW	32	0x0000 0000	0x0000 9008
CTL3_LOGGER	RW	32	0x0000 0000	0x0000 900C
CTL0_GPIO10	RW	32	0x0000 1200	0x0000 A000
CTL1_GPIO10	RW	32	0x0000 0001	0x0000 A004
CTL2_GPIO10	RW	32	0x0000 0000	0x0000 A008
CTL3_GPIO10	RW	32	0x0000 0000	0x0000 A00C
CTL0_GPIO11	RW	32	0x0000 1200	0x0000 B000
CTL1_GPIO11	RW	32	0x0000 0001	0x0000 B004
CTL2_GPIO11	RW	32	0x0000 0000	0x0000 B008
CTL3_GPIO11	RW	32	0x0000 0000	0x0000 B00C
CTL0_GPIO12	RW	32	0x0000 1800	0x0000 C000
CTL1_GPIO12	RW	32	0x0000 0001	0x0000 C004
CTL2_GPIO12	RW	32	0x0000 0000	0x0000 C008
CTL3_GPIO12	RW	32	0x0000 0000	0x0000 C00C
CTL0_GPIO13	RW	32	0x0000 1800	0x0000 D000
CTL1_GPIO13	RW	32	0x0000 0001	0x0000 D004
CTL2_GPIO13	RW	32	0x0000 0000	0x0000 D008
CTL3_GPIO13	RW	32	0x0000 0000	0x0000 D00C
CTL0_GPIO14	RW	32	0x0000 1800	0x0000 E000
CTL1_GPIO14	RW	32	0x0000 0001	0x0000 E004
CTL2_GPIO14	RW	32	0x0000 0000	0x0000 E008
CTL3_GPIO14	RW	32	0x0000 0000	0x0000 E00C
CTL0_GPIO15	RW	32	0x0000 1800	0x0000 F000
CTL1_GPIO15	RW	32	0x0000 0001	0x0000 F004
CTL2_GPIO15	RW	32	0x0000 0000	0x0000 F008
CTL3_GPIO15	RW	32	0x0000 0000	0x0000 F00C
CTL0_GPIO16	RW	32	0x0000 1800	0x0001 0000
CTL1_GPIO16	RW	32	0x0000 0001	0x0001 0004
CTL2_GPIO16	RW	32	0x0000 0000	0x0001 0008
CTL3_GPIO16	RW	32	0x0000 0000	0x0001 000C
CTL0_GPIO17	RW	32	0x0000 1800	0x0001 1000
CTL1_GPIO17	RW	32	0x0000 0001	0x0001 1004
CTL2_GPIO17	RW	32	0x0000 0000	0x0001 1008
CTL3_GPIO17	RW	32	0x0000 0000	0x0001 100C
CTL0_GPIO18	RW	32	0x0000 1800	0x0001 2000
CTL1_GPIO18	RW	32	0x0000 0001	0x0001 2004
CTL2_GPIO18	RW	32	0x0000 0000	0x0001 2008
CTL3_GPIO18	RW	32	0x0000 0000	0x0001 200C
CTL0_GPIO19	RW	32	0x0000 1800	0x0001 3000
CTL1_GPIO19	RW	32	0x0000 0001	0x0001 3004
CTL2_GPIO19	RW	32	0x0000 0000	0x0001 3008
CTL3_GPIO19	RW	32	0x0000 0000	0x0001 300C
CTL0_GPIO20	RW	32	0x0000 0800	0x0001 4000
CTL1_GPIO20	RW	32	0x0000 0001	0x0001 4004
CTL2_GPIO20	RW	32	0x0000 0000	0x0001 4008
CTL3_GPIO20	RW	32	0x0000 0000	0x0001 400C
CTL0_GPIO21	RW	32	0x0000 1800	0x0001 5000
CTL1_GPIO21	RW	32	0x0000 0001	0x0001 5004
CTL2_GPIO21	RW	32	0x0000 0000	0x0001 5008
CTL3_GPIO21	RW	32	0x0000 0000	0x0001 500C
CTL0_GPIO22	RW	32	0x0000 1800	0x0001 6000
CTL1_GPIO22	RW	32	0x0000 0001	0x0001 6004
CTL2_GPIO22	RW	32	0x0000 0000	0x0001 6008
CTL3_GPIO22	RW	32	0x0000 0000	0x0001 600C
CTL0_GPIO23	RW	32	0x0000 1800	0x0001 7000
CTL1_GPIO23	RW	32	0x0000 0001	0x0001 7004
CTL2_GPIO23	RW	32	0x0000 0000	0x0001 7008
CTL3_GPIO23	RW	32	0x0000 0000	0x0001 700C
CTL0_GPIO24	RW	32	0x0000 0800	0x0001 8000
CTL1_GPIO24	RW	32	0x0000 0001	0x0001 8004
CTL2_GPIO24	RW	32	0x0000 0000	0x0001 8008
CTL3_GPIO24	RW	32	0x0000 0000	0x0001 800C
CTL0_GPIO25	RW	32	0x0000 1800	0x0001 9000
CTL1_GPIO25	RW	32	0x0000 0001	0x0001 9004
CTL2_GPIO25	RW	32	0x0000 0000	0x0001 9008
CTL3_GPIO25	RW	32	0x0000 0000	0x0001 900C
CTL0_GPIO26	RW	32	0x0000 1800	0x0001 A000
CTL1_GPIO26	RW	32	0x0000 0001	0x0001 A004
CTL2_GPIO26	RW	32	0x0000 0000	0x0001 A008
CTL3_GPIO26	RW	32	0x0000 0000	0x0001 A00C
CTL0_GPIO27	RW	32	0x0000 1800	0x0001 B000
CTL1_GPIO27	RW	32	0x0000 0001	0x0001 B004
CTL2_GPIO27	RW	32	0x0000 0000	0x0001 B008
CTL3_GPIO27	RW	32	0x0000 0000	0x0001 B00C
CTL0_GPIO28	RW	32	0x0000 1800	0x0001 C000
CTL1_GPIO28	RW	32	0x0000 0001	0x0001 C004
CTL2_GPIO28	RW	32	0x0000 0000	0x0001 C008
CTL3_GPIO28	RW	32	0x0000 0000	0x0001 C00C
CTL0_GPIO29	RW	32	0x0000 1800	0x0001 D000
CTL1_GPIO29	RW	32	0x0000 0001	0x0001 D004
CTL2_GPIO29	RW	32	0x0000 0000	0x0001 D008
CTL3_GPIO29	RW	32	0x0000 0000	0x0001 D00C
CTL0_GPIO30	RW	32	0x0000 1800	0x0001 E000
CTL1_GPIO30	RW	32	0x0000 0001	0x0001 E004
CTL2_GPIO30	RW	32	0x0000 0000	0x0001 E008
CTL3_GPIO30	RW	32	0x0000 0000	0x0001 E00C
CTL0_GPIO31	RW	32	0x0000 1800	0x0001 F000
CTL1_GPIO31	RW	32	0x0000 0001	0x0001 F004
CTL2_GPIO31	RW	32	0x0000 0000	0x0001 F008
CTL3_GPIO31	RW	32	0x0000 0000	0x0001 F00C
CTL0_GPIO32	RW	32	0x0000 1800	0x0002 0000
CTL1_GPIO32	RW	32	0x0000 0001	0x0002 0004
CTL2_GPIO32	RW	32	0x0000 0000	0x0002 0008
CTL3_GPIO32	RW	32	0x0000 0000	0x0002 000C
CTL0_GPIO33	RW	32	0x0000 1800	0x0002 1000
CTL1_GPIO33	RW	32	0x0000 0001	0x0002 1004
CTL2_GPIO33	RW	32	0x0000 0000	0x0002 1008
CTL3_GPIO33	RW	32	0x0000 0000	0x0002 100C
CTL0_GPIO34	RW	32	0x0000 1800	0x0002 2000
CTL1_GPIO34	RW	32	0x0000 0001	0x0002 2004
CTL2_GPIO34	RW	32	0x0000 0000	0x0002 2008
CTL3_GPIO34	RW	32	0x0000 0000	0x0002 200C
CTL0_GPIO35	RW	32	0x0000 1800	0x0002 3000
CTL1_GPIO35	RW	32	0x0000 0001	0x0002 3004
CTL2_GPIO35	RW	32	0x0000 0000	0x0002 3008
CTL3_GPIO35	RW	32	0x0000 0000	0x0002 300C
CTL0_GPIO36	RW	32	0x0000 1800	0x0002 4000
CTL1_GPIO36	RW	32	0x0000 0002	0x0002 4004
CTL2_GPIO36	RW	32	0x0000 0000	0x0002 4008
CTL3_GPIO36	RW	32	0x0000 0000	0x0002 400C
CTL0_GPIO37	RW	32	0x0000 1800	0x0002 5000
CTL1_GPIO37	RW	32	0x0000 0002	0x0002 5004
CTL2_GPIO37	RW	32	0x0000 0000	0x0002 5008
CTL3_GPIO37	RW	32	0x0000 0000	0x0002 500C
CTL0_GPIO38	RW	32	0x0000 1800	0x0002 6000
CTL1_GPIO38	RW	32	0x0000 0001	0x0002 6004
CTL2_GPIO38	RW	32	0x0000 0000	0x0002 6008
CTL3_GPIO38	RW	32	0x0000 0000	0x0002 600C
CTL0_GPIO39	RW	32	0x0000 1800	0x0002 7000
CTL1_GPIO39	RW	32	0x0000 0001	0x0002 7004
CTL2_GPIO39	RW	32	0x0000 0000	0x0002 7008
CTL3_GPIO39	RW	32	0x0000 0000	0x0002 700C
CTL0_GPIO40	RW	32	0x0000 1800	0x0002 8000
CTL1_GPIO40	RW	32	0x0000 0001	0x0002 8004
CTL2_GPIO40	RW	32	0x0000 0000	0x0002 8008
CTL3_GPIO40	RW	32	0x0000 0000	0x0002 800C
CTL0_GPIO41	RW	32	0x0000 1800	0x0002 9000
CTL1_GPIO41	RW	32	0x0000 0001	0x0002 9004
CTL2_GPIO41	RW	32	0x0000 0000	0x0002 9008
CTL3_GPIO41	RW	32	0x0000 0000	0x0002 900C
CTL0_GPIO42	RW	32	0x0000 1800	0x0002 A000
CTL1_GPIO42	RW	32	0x0000 0001	0x0002 A004
CTL2_GPIO42	RW	32	0x0000 0000	0x0002 A008
CTL3_GPIO42	RW	32	0x0000 0000	0x0002 A00C
CTL0_GPIO43	RW	32	0x0000 1800	0x0002 B000
CTL1_GPIO43	RW	32	0x0000 0001	0x0002 B004
CTL2_GPIO43	RW	32	0x0000 0000	0x0002 B008
CTL3_GPIO43	RW	32	0x0000 0000	0x0002 B00C
CTL0_GPIO44	RW	32	0x0000 1800	0x0002 C000
CTL1_GPIO44	RW	32	0x0000 0001	0x0002 C004
CTL2_GPIO44	RW	32	0x0000 0000	0x0002 C008
CTL3_GPIO44	RW	32	0x0000 0000	0x0002 C00C
SOPDIS	RW	32	0x0000 0000	0x0002 D000
CTL_COMMON_SLOW_CLOCK_IN	RW	32	0x0000 0000	0x0002 D004
CTL_COMMON_LFXTAL_N	RW	32	0x0000 0000	0x0002 D008
CTL_COMMON_GPIO2	RW	32	0x0000 0000	0x0002 D00C
CTL_COMMON_GPIO3	RW	32	0x0000 0000	0x0002 D010
CTL_COMMON_GPIO4	RW	32	0x0000 0000	0x0002 D014
CTL_COMMON_GPIO5	RW	32	0x0000 0000	0x0002 D018
CTL_COMMON_GPIO6	RW	32	0x0000 0000	0x0002 D01C
CTL_COMMON_SWDIO	RW	32	0x0000 0000	0x0002 D020
CTL_COMMON_SWCLK	RW	32	0x0000 0000	0x0002 D024
CTL_COMMON_LOGGER	RW	32	0x0000 0000	0x0002 D028
CTL_COMMON_GPIO10	RW	32	0x0000 0000	0x0002 D02C
CTL_COMMON_GPIO11	RW	32	0x0000 0000	0x0002 D030
CTL_COMMON_GPIO12	RW	32	0x0000 0000	0x0002 D034
CTL_COMMON_GPIO13	RW	32	0x0000 0000	0x0002 D038
CTL_COMMON_GPIO14	RW	32	0x0000 0000	0x0002 D03C
CTL_COMMON_GPIO15	RW	32	0x0000 0000	0x0002 D040
CTL_COMMON_GPIO16	RW	32	0x0000 0000	0x0002 D044
CTL_COMMON_GPIO17	RW	32	0x0000 0000	0x0002 D048
CTL_COMMON_GPIO18	RW	32	0x0000 0000	0x0002 D04C
CTL_COMMON_GPIO19	RW	32	0x0000 0000	0x0002 D050
CTL_COMMON_GPIO20	RW	32	0x0000 0000	0x0002 D054
CTL_COMMON_GPIO21	RW	32	0x0000 0000	0x0002 D058
CTL_COMMON_GPIO22	RW	32	0x0000 0000	0x0002 D05C
CTL_COMMON_GPIO23	RW	32	0x0000 0000	0x0002 D060
CTL_COMMON_GPIO24	RW	32	0x0000 0000	0x0002 D064
CTL_COMMON_GPIO25	RW	32	0x0000 0000	0x0002 D068
CTL_COMMON_GPIO26	RW	32	0x0000 0000	0x0002 D06C
CTL_COMMON_GPIO27	RW	32	0x0000 0000	0x0002 D070
CTL_COMMON_GPIO28	RW	32	0x0000 0000	0x0002 D074
CTL_COMMON_GPIO29	RW	32	0x0000 0000	0x0002 D078
CTL_COMMON_GPIO30	RW	32	0x0000 0000	0x0002 D07C
CTL_COMMON_GPIO31	RW	32	0x0000 0000	0x0002 D080
CTL_COMMON_GPIO32	RW	32	0x0000 0000	0x0002 D084
CTL_COMMON_GPIO33	RW	32	0x0000 0000	0x0002 D088
CTL_COMMON_GPIO34	RW	32	0x0000 0000	0x0002 D08C
CTL_COMMON_GPIO35	RW	32	0x0000 0000	0x0002 D090
CTL_COMMON_GPIO36	RW	32	0x0000 0000	0x0002 D094
CTL_COMMON_GPIO37	RW	32	0x0000 0000	0x0002 D098
CTL_COMMON_GPIO38	RW	32	0x0000 0000	0x0002 D09C
CTL_COMMON_GPIO39	RW	32	0x0000 0000	0x0002 D0A0
CTL_COMMON_GPIO40	RW	32	0x0000 0000	0x0002 D0A4
CTL_COMMON_GPIO41	RW	32	0x0000 0000	0x0002 D0A8
CTL_COMMON_GPIO42	RW	32	0x0000 0000	0x0002 D0AC
CTL_COMMON_GPIO43	RW	32	0x0000 0000	0x0002 D0B0
CTL_COMMON_GPIO44	RW	32	0x0000 0000	0x0002 D0B4
PROCCOMP	RW	32	0x0000 0000	0x0002 D0BC
CTL_COMMON_GPIO45	RW	32	0x0000 0000	0x0002 D0C0
CTL_COMMON_GPIO46	RW	32	0x0000 0000	0x0002 D0C4
CTL_COMMON_GPIO47	RW	32	0x0000 0000	0x0002 D0C8
CTL_COMMON_GPIO48	RW	32	0x0000 0000	0x0002 D0CC
CTL0_GPIO45	RW	32	0x0000 1800	0x0002 E000
CTL1_GPIO45	RW	32	0x0000 0001	0x0002 E004
CTL2_GPIO45	RW	32	0x0000 0000	0x0002 E008
CTL3_GPIO45	RW	32	0x0000 0000	0x0002 E00C
CTL0_GPIO46	RW	32	0x0000 1800	0x0002 F000
CTL1_GPIO46	RW	32	0x0000 0001	0x0002 F004
CTL2_GPIO46	RW	32	0x0000 0000	0x0002 F008
CTL3_GPIO46	RW	32	0x0000 0000	0x0002 F00C
CTL0_GPIO47	RW	32	0x0000 1800	0x0003 0000
CTL1_GPIO47	RW	32	0x0000 0001	0x0003 0004
CTL2_GPIO47	RW	32	0x0000 0000	0x0003 0008
CTL3_GPIO47	RW	32	0x0000 0000	0x0003 000C
CTL0_GPIO48	RW	32	0x0000 1800	0x0003 1000
CTL1_GPIO48	RW	32	0x0000 0001	0x0003 1004
CTL2_GPIO48	RW	32	0x0000 0000	0x0003 1008
CTL3_GPIO48	RW	32	0x0000 0000	0x0003 100C

IOMUX Instances Register Mapping Summary

IOMUX Register Descriptions

:IOMUX Common Register Descriptions

:IOMUX:CTL0_SLOW_CLOCK_IN

Address offset	0x0000 0000
Description	CFG register for IO SLOW_CLOCK_IN. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	RESERVED14	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
13	RESERVED13	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
12	RESERVED12	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
11	MEM_IE_SLOW_CLOCK_IN	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	RESERVED6	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_SLOW_CLOCK_IN

Address offset	0x0000 0004
Description	Pull control register of IO SLOW_CLOCK_IN This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	SLOW_CLOCK_IN_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_SLOW_CLOCK_IN	The fields defines the pull control		RW	0x2
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	RSVD RESERVED
		0x3	DISABLE Pull disable

:IOMUX:CTL2_SLOW_CLOCK_IN

Address offset	0x0000 0008
Description	Control register of IO SLOW_CLOCK_IN This register controls the IO state
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
9	RESERVED9	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0
8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00
1	SLOW_CLOCK_IN_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value	RO	0
0	SLOW_CLOCK_IN_IO_IN_LVL	This field captures the received value from pad	RO	0

:IOMUX:CTL3_SLOW_CLOCK_IN

Address offset	0x0000 000C
Description	Event control register for IO SLOW_CLOCK_IN This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_SLOW_CLOCK_IN_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_SLOW_CLOCK_IN	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_SLOW_CLOCK_IN	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_LFXTAL_N

Address offset	0x0000 1000
Description	CFG register for IO LFXTAL_N. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_LFXTAL_N	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_LFXTAL_N	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_LFXTAL_N	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_LFXTAL_N	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_LFXTAL_N	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_LFXTAL_N	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	LFXTAL_N_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_LFXTAL_N

Address offset	0x0000 1004
Description	Pull control register of IO LFXTAL_N This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	LFXTAL_N_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	LFXTAL_N_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_LFXTAL_N	The fields defines the pull control		RW	0x2
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_LFXTAL_N

Address offset	0x0000 1008
Description	Control register of IO LFXTAL_N This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_LFXTAL_N	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_LFXTAL_N	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	LFXTAL_N_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	LFXTAL_N_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_LFXTAL_N

Address offset	0x0000 100C
Description	Event control register for IO LFXTAL_N This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_LFXTAL_N_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_LFXTAL_N	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_LFXTAL_N	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO2

Address offset	0x0000 2000
Description	CFG register for IO GPIO2. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO2	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO2	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO2	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO2	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO2	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO2	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO2_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO2

Address offset	0x0000 2004
Description	Pull control register of IO GPIO2 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO2_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO2_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO2	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO2

Address offset	0x0000 2008
Description	Control register of IO GPIO2 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO2	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO2	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO2_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO2_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO2

Address offset	0x0000 200C
Description	Event control register for IO GPIO2 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO2_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO2	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO2	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO3

Address offset	0x0000 3000
Description	CFG register for IO GPIO3. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO3	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO3	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO3	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO3	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO3	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO3	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO3_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO3

Address offset	0x0000 3004
Description	Pull control register of IO GPIO3 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO3_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO3_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO3	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO3

Address offset	0x0000 3008
Description	Control register of IO GPIO3 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO3	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO3	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO3_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO3_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO3

Address offset	0x0000 300C
Description	Event control register for IO GPIO3 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO3_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO3	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO3	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO4

Address offset	0x0000 4000
Description	CFG register for IO GPIO4. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO4	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO4	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO4	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO4	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO4	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO4	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO4_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO4

Address offset	0x0000 4004
Description	Pull control register of IO GPIO4 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO4_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO4_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO4	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO4

Address offset	0x0000 4008
Description	Control register of IO GPIO4 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO4	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO4	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO4_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO4_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO4

Address offset	0x0000 400C
Description	Event control register for IO GPIO4 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO4_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO4	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO4	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO5

Address offset	0x0000 5000
Description	CFG register for IO GPIO5. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO5	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO5	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO5	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO5	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO5	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO5	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO5_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO5

Address offset	0x0000 5004
Description	Pull control register of IO GPIO5 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO5_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO5_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO5	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO5

Address offset	0x0000 5008
Description	Control register of IO GPIO5 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO5	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO5	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO5_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO5_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO5

Address offset	0x0000 500C
Description	Event control register for IO GPIO5 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO5_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO5	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO5	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO6

Address offset	0x0000 6000
Description	CFG register for IO GPIO6. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO6	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO6	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO6	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO6	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO6	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO6	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO6_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO6

Address offset	0x0000 6004
Description	Pull control register of IO GPIO6 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO6_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO6_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO6	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO6

Address offset	0x0000 6008
Description	Control register of IO GPIO6 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO6	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO6	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO6_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO6_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO6

Address offset	0x0000 600C
Description	Event control register for IO GPIO6 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO6_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO6	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO6	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_SWDIO

Address offset	0x0000 7000
Description	CFG register for IO SWDIO. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_SWDIO	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_SWDIO	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_SWDIO	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_SWDIO	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	SWDIO_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_SWDIO

Address offset	0x0000 7004
Description	Pull control register of IO SWDIO This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	SWDIO_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	SWDIO_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_SWDIO	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_SWDIO

Address offset	0x0000 7008
Description	Control register of IO SWDIO This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_SWDIO	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_SWDIO	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	SWDIO_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	SWDIO_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_SWDIO

Address offset	0x0000 700C
Description	Event control register for IO SWDIO This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_SWDIO_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_SWDIO	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_SWDIO	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_SWCLK

Address offset	0x0000 8000
Description	CFG register for IO SWCLK. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_SWCLK	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_SWCLK	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_SWCLK	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_SWCLK	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	SWCLK_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_SWCLK

Address offset	0x0000 8004
Description	Pull control register of IO SWCLK This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	SWCLK_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	SWCLK_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_SWCLK	The fields defines the pull control		RW	0x2
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_SWCLK

Address offset	0x0000 8008
Description	Control register of IO SWCLK This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_SWCLK	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_SWCLK	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	SWCLK_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	SWCLK_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_SWCLK

Address offset	0x0000 800C
Description	Event control register for IO SWCLK This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_SWCLK_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_SWCLK	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_SWCLK	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_LOGGER

Address offset	0x0000 9000
Description	CFG register for IO LOGGER. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_LOGGER	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_LOGGER	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_LOGGER	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_LOGGER	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	LOGGER_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_LOGGER

Address offset	0x0000 9004
Description	Pull control register of IO LOGGER This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	LOGGER_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	LOGGER_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_LOGGER	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_LOGGER

Address offset	0x0000 9008
Description	Control register of IO LOGGER This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_LOGGER	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_LOGGER	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	LOGGER_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	LOGGER_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_LOGGER

Address offset	0x0000 900C
Description	Event control register for IO LOGGER This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_LOGGER_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_LOGGER	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_LOGGER	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO10

Address offset	0x0000 A000
Description	CFG register for IO GPIO10. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO10	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO10	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO10	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO10	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO10	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO10	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO10_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO10

Address offset	0x0000 A004
Description	Pull control register of IO GPIO10 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO10_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO10_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO10	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO10

Address offset	0x0000 A008
Description	Control register of IO GPIO10 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO10	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO10	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO10_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO10_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO10

Address offset	0x0000 A00C
Description	Event control register for IO GPIO10 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO10_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO10	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO10	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO11

Address offset	0x0000 B000
Description	CFG register for IO GPIO11. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO11	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO11	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO11	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO11	This field enables the receiver operation from the pad		RW	0
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9	MEM_IO_ANA_SW_GPIO11	This field controls the analog switch override		RW	1
		0	DISABLE Analog switch is controlled by IP
		1	ENABLE Enable override on analog switch control
8	MEM_IO_ANA_SW_VAL_GPIO11	This field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled		RW	0
		0	DISABLE Analog switch open
		1	ENABLE Analog switch closed
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO11_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO11

Address offset	0x0000 B004
Description	Pull control register of IO GPIO11 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO11_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO11_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO11	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO11

Address offset	0x0000 B008
Description	Control register of IO GPIO11 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO11	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO11	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO11_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO11_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO11

Address offset	0x0000 B00C
Description	Event control register for IO GPIO11 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO11_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO11	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO11	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO12

Address offset	0x0000 C000
Description	CFG register for IO GPIO12. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO12	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO12	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO12	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO12	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO12_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO12

Address offset	0x0000 C004
Description	Pull control register of IO GPIO12 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO12_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO12_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO12	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO12

Address offset	0x0000 C008
Description	Control register of IO GPIO12 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO12	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO12	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO12_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO12_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO12

Address offset	0x0000 C00C
Description	Event control register for IO GPIO12 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO12_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO12	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO12	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO13

Address offset	0x0000 D000
Description	CFG register for IO GPIO13. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO13	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO13	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO13	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO13	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO13_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO13

Address offset	0x0000 D004
Description	Pull control register of IO GPIO13 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO13_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO13_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO13	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO13

Address offset	0x0000 D008
Description	Control register of IO GPIO13 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO13	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO13	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO13_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO13_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO13

Address offset	0x0000 D00C
Description	Event control register for IO GPIO13 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO13_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO13	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO13	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO14

Address offset	0x0000 E000
Description	CFG register for IO GPIO14. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO14	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO14	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO14	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO14	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO14_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO14

Address offset	0x0000 E004
Description	Pull control register of IO GPIO14 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO14_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO14_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO14	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO14

Address offset	0x0000 E008
Description	Control register of IO GPIO14 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO14	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO14	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO14_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO14_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO14

Address offset	0x0000 E00C
Description	Event control register for IO GPIO14 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO14_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO14	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO14	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO15

Address offset	0x0000 F000
Description	CFG register for IO GPIO15. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO15	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO15	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO15	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO15	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO15_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO15

Address offset	0x0000 F004
Description	Pull control register of IO GPIO15 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO15_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO15_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO15	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO15

Address offset	0x0000 F008
Description	Control register of IO GPIO15 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO15	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO15	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO15_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO15_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO15

Address offset	0x0000 F00C
Description	Event control register for IO GPIO15 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO15_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO15	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO15	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO16

Address offset	0x0001 0000
Description	CFG register for IO GPIO16. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO16	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO16	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO16	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO16	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO16_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO16

Address offset	0x0001 0004
Description	Pull control register of IO GPIO16 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO16_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO16_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO16	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO16

Address offset	0x0001 0008
Description	Control register of IO GPIO16 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO16	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO16	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO16_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO16_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO16

Address offset	0x0001 000C
Description	Event control register for IO GPIO16 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO16_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO16	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO16	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO17

Address offset	0x0001 1000
Description	CFG register for IO GPIO17. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO17	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO17	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO17	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO17	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO17_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO17

Address offset	0x0001 1004
Description	Pull control register of IO GPIO17 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO17_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO17_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO17	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO17

Address offset	0x0001 1008
Description	Control register of IO GPIO17 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO17	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO17	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO17_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO17_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO17

Address offset	0x0001 100C
Description	Event control register for IO GPIO17 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO17_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO17	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO17	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO18

Address offset	0x0001 2000
Description	CFG register for IO GPIO18. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO18	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO18	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO18	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO18	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO18_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO18

Address offset	0x0001 2004
Description	Pull control register of IO GPIO18 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO18_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO18_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO18	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO18

Address offset	0x0001 2008
Description	Control register of IO GPIO18 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO18	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO18	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO18_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO18_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO18

Address offset	0x0001 200C
Description	Event control register for IO GPIO18 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO18_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO18	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO18	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO19

Address offset	0x0001 3000
Description	CFG register for IO GPIO19. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO19	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO19	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO19	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO19	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO19_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO19

Address offset	0x0001 3004
Description	Pull control register of IO GPIO19 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO19_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO19_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO19	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO19

Address offset	0x0001 3008
Description	Control register of IO GPIO19 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO19	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO19	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO19_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO19_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO19

Address offset	0x0001 300C
Description	Event control register for IO GPIO19 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO19_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO19	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO19	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO20

Address offset	0x0001 4000
Description	CFG register for IO GPIO20. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO20	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO20	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO20	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	0
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO20	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO20_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO20

Address offset	0x0001 4004
Description	Pull control register of IO GPIO20 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO20_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO20_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO20	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO20

Address offset	0x0001 4008
Description	Control register of IO GPIO20 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO20	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO20	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO20_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO20_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO20

Address offset	0x0001 400C
Description	Event control register for IO GPIO20 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO20_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO20	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO20	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO21

Address offset	0x0001 5000
Description	CFG register for IO GPIO21. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO21	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO21	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO21	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO21	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO21_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO21

Address offset	0x0001 5004
Description	Pull control register of IO GPIO21 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO21_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO21_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO21	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO21

Address offset	0x0001 5008
Description	Control register of IO GPIO21 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO21	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO21	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO21_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO21_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO21

Address offset	0x0001 500C
Description	Event control register for IO GPIO21 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO21_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO21	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO21	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO22

Address offset	0x0001 6000
Description	CFG register for IO GPIO22. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO22	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO22	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO22	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO22	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO22_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO22

Address offset	0x0001 6004
Description	Pull control register of IO GPIO22 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO22_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO22_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO22	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO22

Address offset	0x0001 6008
Description	Control register of IO GPIO22 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO22	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO22	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO22_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO22_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO22

Address offset	0x0001 600C
Description	Event control register for IO GPIO22 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO22_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO22	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO22	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO23

Address offset	0x0001 7000
Description	CFG register for IO GPIO23. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO23	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO23	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO23	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO23	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO23_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO23

Address offset	0x0001 7004
Description	Pull control register of IO GPIO23 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO23_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO23_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO23	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO23

Address offset	0x0001 7008
Description	Control register of IO GPIO23 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO23	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO23	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO23_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO23_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO23

Address offset	0x0001 700C
Description	Event control register for IO GPIO23 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO23_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO23	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO23	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO24

Address offset	0x0001 8000
Description	CFG register for IO GPIO24. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO24	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO24	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO24	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	0
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO24	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO24_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO24

Address offset	0x0001 8004
Description	Pull control register of IO GPIO24 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO24_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO24_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO24	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO24

Address offset	0x0001 8008
Description	Control register of IO GPIO24 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO24	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO24	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO24_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO24_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO24

Address offset	0x0001 800C
Description	Event control register for IO GPIO24 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO24_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO24	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO24	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO25

Address offset	0x0001 9000
Description	CFG register for IO GPIO25. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO25	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO25	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO25	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO25	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO25_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO25

Address offset	0x0001 9004
Description	Pull control register of IO GPIO25 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO25_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO25_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO25	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO25

Address offset	0x0001 9008
Description	Control register of IO GPIO25 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO25	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO25	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO25_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO25_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO25

Address offset	0x0001 900C
Description	Event control register for IO GPIO25 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO25_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO25	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO25	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO26

Address offset	0x0001 A000
Description	CFG register for IO GPIO26. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO26	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO26	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO26	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO26	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO26_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO26

Address offset	0x0001 A004
Description	Pull control register of IO GPIO26 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO26_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO26_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO26	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO26

Address offset	0x0001 A008
Description	Control register of IO GPIO26 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO26	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO26	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO26_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO26_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO26

Address offset	0x0001 A00C
Description	Event control register for IO GPIO26 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO26_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO26	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO26	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO27

Address offset	0x0001 B000
Description	CFG register for IO GPIO27. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO27	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO27	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO27	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO27	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO27_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO27

Address offset	0x0001 B004
Description	Pull control register of IO GPIO27 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO27_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO27_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO27	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO27

Address offset	0x0001 B008
Description	Control register of IO GPIO27 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO27	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO27	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO27_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO27_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO27

Address offset	0x0001 B00C
Description	Event control register for IO GPIO27 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO27_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO27	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO27	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO28

Address offset	0x0001 C000
Description	CFG register for IO GPIO28. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO28	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO28	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO28	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO28	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO28_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO28

Address offset	0x0001 C004
Description	Pull control register of IO GPIO28 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO28_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO28_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO28	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO28

Address offset	0x0001 C008
Description	Control register of IO GPIO28 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO28	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO28	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO28_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO28_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO28

Address offset	0x0001 C00C
Description	Event control register for IO GPIO28 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO28_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO28	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO28	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO29

Address offset	0x0001 D000
Description	CFG register for IO GPIO29. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO29	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO29	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO29	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO29	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO29_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO29

Address offset	0x0001 D004
Description	Pull control register of IO GPIO29 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO29_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO29_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO29	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO29

Address offset	0x0001 D008
Description	Control register of IO GPIO29 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO29	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO29	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO29_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO29_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO29

Address offset	0x0001 D00C
Description	Event control register for IO GPIO29 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO29_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO29	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO29	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO30

Address offset	0x0001 E000
Description	CFG register for IO GPIO30. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO30	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO30	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO30	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO30	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO30_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO30

Address offset	0x0001 E004
Description	Pull control register of IO GPIO30 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO30_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO30_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO30	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO30

Address offset	0x0001 E008
Description	Control register of IO GPIO30 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO30	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO30	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO30_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO30_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO30

Address offset	0x0001 E00C
Description	Event control register for IO GPIO30 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO30_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO30	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO30	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO31

Address offset	0x0001 F000
Description	CFG register for IO GPIO31. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO31	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO31	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO31	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO31	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO31_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO31

Address offset	0x0001 F004
Description	Pull control register of IO GPIO31 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO31_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO31_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO31	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO31

Address offset	0x0001 F008
Description	Control register of IO GPIO31 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO31	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO31	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO31_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO31_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO31

Address offset	0x0001 F00C
Description	Event control register for IO GPIO31 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO31_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO31	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO31	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO32

Address offset	0x0002 0000
Description	CFG register for IO GPIO32. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO32	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO32	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO32	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO32	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO32_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO32

Address offset	0x0002 0004
Description	Pull control register of IO GPIO32 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO32_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO32_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO32	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO32

Address offset	0x0002 0008
Description	Control register of IO GPIO32 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO32	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO32	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO32_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO32_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO32

Address offset	0x0002 000C
Description	Event control register for IO GPIO32 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO32_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO32	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO32	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO33

Address offset	0x0002 1000
Description	CFG register for IO GPIO33. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO33	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO33	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO33	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO33	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO33_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO33

Address offset	0x0002 1004
Description	Pull control register of IO GPIO33 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO33_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO33_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO33	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO33

Address offset	0x0002 1008
Description	Control register of IO GPIO33 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO33	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO33	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO33_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO33_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO33

Address offset	0x0002 100C
Description	Event control register for IO GPIO33 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO33_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO33	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO33	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO34

Address offset	0x0002 2000
Description	CFG register for IO GPIO34. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO34	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO34	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO34	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO34	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO34_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO34

Address offset	0x0002 2004
Description	Pull control register of IO GPIO34 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO34_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO34_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO34	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO34

Address offset	0x0002 2008
Description	Control register of IO GPIO34 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO34	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO34	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO34_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO34_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO34

Address offset	0x0002 200C
Description	Event control register for IO GPIO34 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO34_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO34	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO34	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO35

Address offset	0x0002 3000
Description	CFG register for IO GPIO35. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO35	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO35	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO35	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO35	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO35_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO35

Address offset	0x0002 3004
Description	Pull control register of IO GPIO35 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO35_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO35_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO35	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO35

Address offset	0x0002 3008
Description	Control register of IO GPIO35 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO35	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO35	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO35_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO35_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO35

Address offset	0x0002 300C
Description	Event control register for IO GPIO35 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO35_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO35	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO35	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO36

Address offset	0x0002 4000
Description	CFG register for IO GPIO36. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO36	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO36	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO36	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO36	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO36_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO36

Address offset	0x0002 4004
Description	Pull control register of IO GPIO36 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO36_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO36_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO36	The fields defines the pull control		RW	0x2
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO36

Address offset	0x0002 4008
Description	Control register of IO GPIO36 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO36	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO36	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO36_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO36_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO36

Address offset	0x0002 400C
Description	Event control register for IO GPIO36 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO36_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO36	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO36	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO37

Address offset	0x0002 5000
Description	CFG register for IO GPIO37. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO37	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO37	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO37	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO37	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO37_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO37

Address offset	0x0002 5004
Description	Pull control register of IO GPIO37 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO37_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO37_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO37	The fields defines the pull control		RW	0x2
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO37

Address offset	0x0002 5008
Description	Control register of IO GPIO37 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO37	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO37	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO37_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO37_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO37

Address offset	0x0002 500C
Description	Event control register for IO GPIO37 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO37_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO37	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO37	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO38

Address offset	0x0002 6000
Description	CFG register for IO GPIO38. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO38	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO38	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO38	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO38	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO38_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO38

Address offset	0x0002 6004
Description	Pull control register of IO GPIO38 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO38_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO38_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO38	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO38

Address offset	0x0002 6008
Description	Control register of IO GPIO38 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO38	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO38	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO38_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO38_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO38

Address offset	0x0002 600C
Description	Event control register for IO GPIO38 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO38_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO38	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO38	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO39

Address offset	0x0002 7000
Description	CFG register for IO GPIO39. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO39	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO39	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO39	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO39	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO39_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO39

Address offset	0x0002 7004
Description	Pull control register of IO GPIO39 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO39_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO39_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO39	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO39

Address offset	0x0002 7008
Description	Control register of IO GPIO39 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO39	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO39	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO39_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO39_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO39

Address offset	0x0002 700C
Description	Event control register for IO GPIO39 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO39_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO39	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO39	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO40

Address offset	0x0002 8000
Description	CFG register for IO GPIO40. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO40	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO40	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO40	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO40	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO40_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO40

Address offset	0x0002 8004
Description	Pull control register of IO GPIO40 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO40_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO40_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO40	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO40

Address offset	0x0002 8008
Description	Control register of IO GPIO40 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO40	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO40	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO40_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO40_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO40

Address offset	0x0002 800C
Description	Event control register for IO GPIO40 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO40_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO40	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO40	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO41

Address offset	0x0002 9000
Description	CFG register for IO GPIO41. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO41	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO41	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO41	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO41	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO41_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO41

Address offset	0x0002 9004
Description	Pull control register of IO GPIO41 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO41_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO41_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO41	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO41

Address offset	0x0002 9008
Description	Control register of IO GPIO41 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO41	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO41	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO41_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO41_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO41

Address offset	0x0002 900C
Description	Event control register for IO GPIO41 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO41_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO41	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO41	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO42

Address offset	0x0002 A000
Description	CFG register for IO GPIO42. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO42	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO42	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO42	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO42	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO42_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO42

Address offset	0x0002 A004
Description	Pull control register of IO GPIO42 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO42_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO42_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO42	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO42

Address offset	0x0002 A008
Description	Control register of IO GPIO42 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO42	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO42	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO42_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO42_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO42

Address offset	0x0002 A00C
Description	Event control register for IO GPIO42 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO42_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO42	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO42	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO43

Address offset	0x0002 B000
Description	CFG register for IO GPIO43. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO43	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO43	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO43	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO43	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO43_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO43

Address offset	0x0002 B004
Description	Pull control register of IO GPIO43 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO43_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO43_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO43	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO43

Address offset	0x0002 B008
Description	Control register of IO GPIO43 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO43	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO43	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO43_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO43_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO43

Address offset	0x0002 B00C
Description	Event control register for IO GPIO43 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO43_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO43	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO43	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO44

Address offset	0x0002 C000
Description	CFG register for IO GPIO44. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO44	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO44	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO44	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO44	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO44_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO44

Address offset	0x0002 C004
Description	Pull control register of IO GPIO44 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO44_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO44_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO44	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO44

Address offset	0x0002 C008
Description	Control register of IO GPIO44 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO44	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO44	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO44_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO44_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO44

Address offset	0x0002 C00C
Description	Event control register for IO GPIO44 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO44_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO44	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO44	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:SOPDIS

Address offset	0x0002 D000
Description	This register disables the SOP overrides when the device was powered in one of the SoP modes.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	RESERVED_1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	MEM_SOPDISABLE	The field is to disable SOP		RW	0
		0	USE Use SOP
		1	DISABLE Disable SOP

:IOMUX:CTL_COMMON_SLOW_CLOCK_IN

Address offset	0x0002 D004
Description	Port configuration register for IO SLOW_CLOCK_IN
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_SLOW_CLOCK_IN	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- slow_clock_in sel 5'd2 -- wifi_gpio_0 sel 5'd9 -- gpt1_1 sel 5'd10 -- gpt0_1 sel 5'd21 -- coex_req		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 slow_clock_in
		0x02	SEL_2 wifi_gpio_0
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 gpt0_1
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 coex_req
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_LFXTAL_N

Address offset	0x0002 D008
Description	Port configuration register for IO LFXTAL_N
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_LFXTAL_N	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- lfxt_n sel 5'd2 -- wifi_gpio_1 sel 5'd7 -- gpt1_pre_event sel 5'd8 -- gpt0_pre_event sel 5'd9 -- gpt1_0 sel 5'd10 -- gpt0_0 sel 5'd11 -- gpt_infrared sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd23 -- ant_sel_0		RW	0x00
		0x00	SEL_0 lfxt_n
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_1
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 gpt1_pre_event
		0x08	SEL_8 gpt0_pre_event
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 gpt0_0
		0x0B	SEL_11 gpt_infrared
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 sdio_oob_irq
		0x14	SEL_20 coex_grant
		0x15	SEL_21 coex_req
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO2

Address offset	0x0002 D00C
Description	Port configuration register for IO GPIO2
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO2	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_2 sel 5'd3 -- sdio_mmc_cd sel 5'd6 -- i2c1_clk sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_6 sel 5'd12 -- debug_bus_4 sel 5'd16 -- spi0_cs4 sel 5'd18 -- gpt1_pre_event sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd22 -- ble_rftrc sel 5'd23 -- ant_sel_2 sel 5'd24 -- cca sel 5'd26 -- trclk		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_ram
		0x02	SEL_2 wifi_gpio_2
		0x03	SEL_3 sdio_mmc_cd
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt1_3
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 wake_observe_bus_6
		0x0C	SEL_12 debug_bus_4
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs4
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_pre_event
		0x13	SEL_19 sdio_oob_irq
		0x14	SEL_20 coex_grant
		0x15	SEL_21 coex_req
		0x16	SEL_22 ble_rftrc
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 cca
		0x19	SEL_25 reserved
		0x1A	SEL_26 trclk
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO3

Address offset	0x0002 D010
Description	Port configuration register for IO GPIO3
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO3	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_tx sel 5'd2 -- wifi_gpio_3 sel 5'd3 -- sdio_mmc_wp sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_rts sel 5'd6 -- i2s_mclk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_7 sel 5'd12 -- debug_bus_0 sel 5'd16 -- spi0_cs3 sel 5'd17 -- xspi_cs_ram sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_clk sel 5'd20 -- coex_req sel 5'd21 -- gpt0_0_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_3 sel 5'd24 -- ble_rfc_gpo_7 sel 5'd25 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- i2c1_data sel 5'd30 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 uart1_tx
		0x02	SEL_2 wifi_gpio_3
		0x03	SEL_3 sdio_mmc_wp
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart1_rts
		0x06	SEL_6 i2s_mclk
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 wake_observe_bus_7
		0x0C	SEL_12 debug_bus_0
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs3
		0x11	SEL_17 xspi_cs_ram
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 sdio_clk
		0x14	SEL_20 coex_req
		0x15	SEL_21 gpt0_0_n
		0x16	SEL_22 gpt_infrared
		0x17	SEL_23 ant_sel_3
		0x18	SEL_24 ble_rfc_gpo_7
		0x19	SEL_25 swo_m3
		0x1A	SEL_26 reserved
		0x1B	SEL_27 swo_m33
		0x1C	SEL_28 i2c1_data
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_tx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO4

Address offset	0x0002 D014
Description	Port configuration register for IO GPIO4
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO4	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_rx sel 5'd2 -- wifi_gpio_4 sel 5'd3 -- sdio_mmc_cd sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_cts sel 5'd6 -- i2s_bclk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_8 sel 5'd12 -- debug_bus_1 sel 5'd16 -- spi0_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_cmd sel 5'd20 -- coex_priority sel 5'd21 -- gpt0_1_n sel 5'd24 -- ble_rfc_gpo_6 sel 5'd28 -- i2c1_clk sel 5'd30 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 uart1_rx
		0x02	SEL_2 wifi_gpio_4
		0x03	SEL_3 sdio_mmc_cd
		0x04	SEL_4 spi1_cs1
		0x05	SEL_5 uart1_cts
		0x06	SEL_6 i2s_bclk
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 wake_observe_bus_8
		0x0C	SEL_12 debug_bus_1
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs2
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 sdio_cmd
		0x14	SEL_20 coex_priority
		0x15	SEL_21 gpt0_1_n
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 ble_rfc_gpo_6
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 i2c1_clk
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_rx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO5

Address offset	0x0002 D018
Description	Port configuration register for IO GPIO5
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO5	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_5 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_mclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_2 sel 5'd10 -- dcan_tx sel 5'd11 -- jtag_tdi sel 5'd12 -- debug_bus_11 sel 5'd16 -- spi0_cs4 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_d0 sel 5'd20 -- coex_req sel 5'd21 -- gpt0_2_n sel 5'd22 -- ble_rftrc sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd28 -- i2c1_data sel 5'd30 -- uart2_rts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_ram
		0x02	SEL_2 wifi_gpio_5
		0x03	SEL_3 sdio_mmc_pow2
		0x04	SEL_4 spi1_miso
		0x05	SEL_5 uart1_tx
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_mclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt1_2
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 jtag_tdi
		0x0C	SEL_12 debug_bus_11
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs4
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 sdio_d0
		0x14	SEL_20 coex_req
		0x15	SEL_21 gpt0_2_n
		0x16	SEL_22 ble_rftrc
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 i2c1_data
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_rts
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO6

Address offset	0x0002 D01C
Description	Port configuration register for IO GPIO6
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO6	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_6 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_rx sel 5'd11 -- sdio_mmc_wp sel 5'd12 -- debug_bus_12 sel 5'd16 -- spi0_cs4 sel 5'd17 -- i2s_bclk sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_d1 sel 5'd20 -- coex_priority sel 5'd21 -- gpt0_3_n sel 5'd22 -- gpt1_pre_event sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_3 sel 5'd26 -- coex_grant sel 5'd28 -- i2c1_clk sel 5'd29 -- sdio_mmc_pow2 sel 5'd30 -- uart2_cts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_6
		0x03	SEL_3 sdio_mmc_pow1
		0x04	SEL_4 spi1_mosi
		0x05	SEL_5 uart1_rx
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt1_3
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 sdio_mmc_wp
		0x0C	SEL_12 debug_bus_12
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs4
		0x11	SEL_17 i2s_bclk
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 sdio_d1
		0x14	SEL_20 coex_priority
		0x15	SEL_21 gpt0_3_n
		0x16	SEL_22 gpt1_pre_event
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 cca
		0x19	SEL_25 ble_rfc_gpi_3
		0x1A	SEL_26 coex_grant
		0x1B	SEL_27 reserved
		0x1C	SEL_28 i2c1_clk
		0x1D	SEL_29 sdio_mmc_pow2
		0x1E	SEL_30 uart2_cts
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_SWDIO

Address offset	0x0002 D020
Description	Port configuration register for IO SWDIO
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_SWDIO	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- swdio sel 5'd2 -- wifi_gpio_7 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- jtag_tms sel 5'd23 -- ant_sel_0		RW	0x00
		0x00	SEL_0 swdio
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_7
		0x03	SEL_3 sdio_mmc_pow2
		0x04	SEL_4 jtag_tms
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_SWCLK

Address offset	0x0002 D024
Description	Port configuration register for IO SWCLK
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_SWCLK	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- swclk sel 5'd2 -- wifi_gpio_8 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- jtag_tck sel 5'd23 -- ant_sel_1		RW	0x00
		0x00	SEL_0 swclk
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_8
		0x03	SEL_3 sdio_mmc_pow1
		0x04	SEL_4 jtag_tck
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_LOGGER

Address offset	0x0002 D028
Description	Port configuration register for IO LOGGER
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_LOGGER	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- logger sel 5'd2 -- wifi_gpio_9 sel 5'd3 -- sdio_mmc_cd sel 5'd4 -- ble_rftrc sel 5'd11 -- jtag_tdo sel 5'd23 -- ant_sel_2 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 logger
		0x02	SEL_2 wifi_gpio_9
		0x03	SEL_3 sdio_mmc_cd
		0x04	SEL_4 ble_rftrc
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 jtag_tdo
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 swo_m3
		0x1B	SEL_27 swo_m33
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO10

Address offset	0x0002 D02C
Description	Port configuration register for IO GPIO10
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO10	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_tx sel 5'd2 -- wifi_gpio_10 sel 5'd3 -- sdio_mmc_data_3 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_rx sel 5'd11 -- uart_rs232_rx sel 5'd12 -- debug_bus_10 sel 5'd16 -- spi0_cs3 sel 5'd18 -- gpt1_3_n sel 5'd19 -- sdio_d3 sel 5'd20 -- coex_priority sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_2 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trdata_0 sel 5'd30 -- uart2_rts sel 5'd31 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 uart1_tx
		0x02	SEL_2 wifi_gpio_10
		0x03	SEL_3 sdio_mmc_data_3
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart1_rts
		0x06	SEL_6 i2c1_data
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 uart_rs232_rx
		0x0C	SEL_12 debug_bus_10
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs3
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_3_n
		0x13	SEL_19 sdio_d3
		0x14	SEL_20 coex_priority
		0x15	SEL_21 coex_grant
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 cca
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 trdata_0
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_rts
		0x1F	SEL_31 uart2_tx

:IOMUX:CTL_COMMON_GPIO11

Address offset	0x0002 D030
Description	Port configuration register for IO GPIO11
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO11	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_rx sel 5'd2 -- wifi_gpio_11 sel 5'd3 -- sdio_mmc_data_2 sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- uart_rs232_tx sel 5'd12 -- debug_bus_9 sel 5'd16 -- spi0_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_2_n sel 5'd19 -- sdio_d2 sel 5'd20 -- coex_req sel 5'd23 -- ant_sel_3 sel 5'd24 -- cca sel 5'd25 -- swo_m3 sel 5'd26 -- trdata_1 sel 5'd30 -- uart2_cts sel 5'd31 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 uart1_rx
		0x02	SEL_2 wifi_gpio_11
		0x03	SEL_3 sdio_mmc_data_2
		0x04	SEL_4 spi1_cs1
		0x05	SEL_5 uart1_cts
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 uart_rs232_tx
		0x0C	SEL_12 debug_bus_9
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs2
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt1_2_n
		0x13	SEL_19 sdio_d2
		0x14	SEL_20 coex_req
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_3
		0x18	SEL_24 cca
		0x19	SEL_25 swo_m3
		0x1A	SEL_26 trdata_1
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_cts
		0x1F	SEL_31 uart2_rx

:IOMUX:CTL_COMMON_GPIO12

Address offset	0x0002 D034
Description	Port configuration register for IO GPIO12
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO12	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_12 sel 5'd3 -- sdio_mmc_data_1 sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_rts sel 5'd6 -- uart0_rts sel 5'd7 -- i2s_wclk sel 5'd9 -- gpt1_2 sel 5'd10 -- uart_rs232_tx sel 5'd11 -- jtag_tdo sel 5'd12 -- debug_bus_8 sel 5'd16 -- gpt0_pre_event sel 5'd17 -- gpt1_pre_event sel 5'd18 -- gpt1_3_n sel 5'd19 -- sdio_clk sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd26 -- trdata_2 sel 5'd31 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_12
		0x03	SEL_3 sdio_mmc_data_1
		0x04	SEL_4 spi1_cs1
		0x05	SEL_5 uart1_rts
		0x06	SEL_6 uart0_rts
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt1_2
		0x0A	SEL_10 uart_rs232_tx
		0x0B	SEL_11 jtag_tdo
		0x0C	SEL_12 debug_bus_8
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 gpt0_pre_event
		0x11	SEL_17 gpt1_pre_event
		0x12	SEL_18 gpt1_3_n
		0x13	SEL_19 sdio_clk
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_7
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 trdata_2
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 uart2_tx

:IOMUX:CTL_COMMON_GPIO13

Address offset	0x0002 D038
Description	Port configuration register for IO GPIO13
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO13	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_13 sel 5'd3 -- sdio_mmc_data_0 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_cts sel 5'd6 -- uart0_tx sel 5'd7 -- i2s_bclk sel 5'd8 -- i2s_mclk sel 5'd9 -- gpt1_3 sel 5'd11 -- wake_observe_bus_14 sel 5'd12 -- debug_bus_7 sel 5'd18 -- gpt1_2_n sel 5'd19 -- sdio_cmd sel 5'd20 -- coex_priority sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_0 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trdata_3 sel 5'd31 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_13
		0x03	SEL_3 sdio_mmc_data_0
		0x04	SEL_4 spi1_mosi
		0x05	SEL_5 uart1_cts
		0x06	SEL_6 uart0_tx
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 i2s_mclk
		0x09	SEL_9 gpt1_3
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_14
		0x0C	SEL_12 debug_bus_7
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_2_n
		0x13	SEL_19 sdio_cmd
		0x14	SEL_20 coex_priority
		0x15	SEL_21 ble_rftrc
		0x16	SEL_22 ble_rfc_gpo_6
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 trdata_3
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 uart2_rx

:IOMUX:CTL_COMMON_GPIO14

Address offset	0x0002 D03C
Description	Port configuration register for IO GPIO14
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO14	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_14 sel 5'd3 -- sdio_mmc_clk sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- uart0_rx sel 5'd9 -- gpt1_0 sel 5'd11 -- wake_observe_bus_15 sel 5'd12 -- debug_bus_clk sel 5'd16 -- spi0_cs2 sel 5'd17 -- gpt1_pre_event sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_d0 sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_4 sel 5'd24 -- ble_rfc_gpi_2 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trclk sel 5'd27 -- digital_fast_clk_in		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_14
		0x03	SEL_3 sdio_mmc_clk
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart1_tx
		0x06	SEL_6 uart0_rx
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_15
		0x0C	SEL_12 debug_bus_clk
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs2
		0x11	SEL_17 gpt1_pre_event
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 sdio_d0
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_4
		0x17	SEL_23 reserved
		0x18	SEL_24 ble_rfc_gpi_2
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 trclk
		0x1B	SEL_27 digital_fast_clk_in
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO15

Address offset	0x0002 D040
Description	Port configuration register for IO GPIO15
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO15	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_15 sel 5'd3 -- sdio_mmc_cmd sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_rx sel 5'd6 -- uart0_cts sel 5'd9 -- gpt1_1 sel 5'd10 -- uart_rs232_rx sel 5'd11 -- jtag_tdi sel 5'd12 -- debug_bus_6 sel 5'd16 -- spi1_cs2 sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_d1 sel 5'd20 -- coex_req sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_5 sel 5'd25 -- ble_rfc_gpi_3 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_15
		0x03	SEL_3 sdio_mmc_cmd
		0x04	SEL_4 spi1_miso
		0x05	SEL_5 uart1_rx
		0x06	SEL_6 uart0_cts
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 uart_rs232_rx
		0x0B	SEL_11 jtag_tdi
		0x0C	SEL_12 debug_bus_6
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs2
		0x11	SEL_17 gpt0_pre_event
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 sdio_d1
		0x14	SEL_20 coex_req
		0x15	SEL_21 ble_rftrc
		0x16	SEL_22 ble_rfc_gpo_5
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_3
		0x1A	SEL_26 swo_m3
		0x1B	SEL_27 swo_m33
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO16

Address offset	0x0002 D044
Description	Port configuration register for IO GPIO16
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO16	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_16 sel 5'd3 -- sdio_mmc_data_7 sel 5'd4 -- spi0_cs1 sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_0 sel 5'd10 -- uart_rs232_rx sel 5'd11 -- wake_observe_bus_12 sel 5'd12 -- debug_bus_5 sel 5'd16 -- spi1_cs2 sel 5'd18 -- gpt0_1_n sel 5'd19 -- sdio_d2 sel 5'd21 -- gpt1_0_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_0 sel 5'd26 -- trdata_0 sel 5'd30 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_16
		0x03	SEL_3 sdio_mmc_data_7
		0x04	SEL_4 spi0_cs1
		0x05	SEL_5 uart0_rts
		0x06	SEL_6 i2c1_data
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt0_0
		0x0A	SEL_10 uart_rs232_rx
		0x0B	SEL_11 wake_observe_bus_12
		0x0C	SEL_12 debug_bus_5
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs2
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt0_1_n
		0x13	SEL_19 sdio_d2
		0x14	SEL_20 reserved
		0x15	SEL_21 gpt1_0_n
		0x16	SEL_22 gpt_infrared
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 trdata_0
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_tx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO17

Address offset	0x0002 D048
Description	Port configuration register for IO GPIO17
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO17	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- sdio_mmc_wp sel 5'd2 -- wifi_gpio_17 sel 5'd3 -- sdio_mmc_data_6 sel 5'd4 -- spi0_clk sel 5'd5 -- uart0_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd10 -- uart_rs232_tx sel 5'd11 -- wake_observe_bus_9 sel 5'd12 -- debug_bus_2 sel 5'd16 -- spi1_cs3 sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_grant sel 5'd21 -- gpt1_1_n sel 5'd23 -- ant_sel_1 sel 5'd26 -- trdata_1		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 sdio_mmc_wp
		0x02	SEL_2 wifi_gpio_17
		0x03	SEL_3 sdio_mmc_data_6
		0x04	SEL_4 spi0_clk
		0x05	SEL_5 uart0_tx
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt0_1
		0x0A	SEL_10 uart_rs232_tx
		0x0B	SEL_11 wake_observe_bus_9
		0x0C	SEL_12 debug_bus_2
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs3
		0x11	SEL_17 sdio_oob_irq
		0x12	SEL_18 gpt0_0_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_grant
		0x15	SEL_21 gpt1_1_n
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 trdata_1
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO18

Address offset	0x0002 D04C
Description	Port configuration register for IO GPIO18
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO18	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_18 sel 5'd3 -- sdio_mmc_data_5 sel 5'd4 -- spi0_miso sel 5'd5 -- uart0_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt0_2 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_10 sel 5'd12 -- debug_bus_3 sel 5'd16 -- spi1_cs4 sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_req sel 5'd21 -- gpt1_2_n sel 5'd23 -- ant_sel_2 sel 5'd26 -- trdata_2		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_18
		0x03	SEL_3 sdio_mmc_data_5
		0x04	SEL_4 spi0_miso
		0x05	SEL_5 uart0_rx
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt0_2
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 wake_observe_bus_10
		0x0C	SEL_12 debug_bus_3
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs4
		0x11	SEL_17 sdio_oob_irq
		0x12	SEL_18 gpt0_0_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_req
		0x15	SEL_21 gpt1_2_n
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 trdata_2
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO19

Address offset	0x0002 D050
Description	Port configuration register for IO GPIO19
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO19	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_19 sel 5'd3 -- sdio_mmc_data_4 sel 5'd4 -- spi0_mosi sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_3 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_11 sel 5'd12 -- debug_bus_4 sel 5'd16 -- gpt0_pre_event sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_1_n sel 5'd19 -- sdio_d3 sel 5'd20 -- coex_priority sel 5'd21 -- gpt1_3_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_3 sel 5'd26 -- trdata_3 sel 5'd30 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_19
		0x03	SEL_3 sdio_mmc_data_4
		0x04	SEL_4 spi0_mosi
		0x05	SEL_5 uart0_cts
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt0_3
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 wake_observe_bus_11
		0x0C	SEL_12 debug_bus_4
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 gpt0_pre_event
		0x11	SEL_17 sdio_oob_irq
		0x12	SEL_18 gpt0_1_n
		0x13	SEL_19 sdio_d3
		0x14	SEL_20 coex_priority
		0x15	SEL_21 gpt1_3_n
		0x16	SEL_22 gpt_infrared
		0x17	SEL_23 ant_sel_3
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 trdata_3
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 uart2_rx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO20

Address offset	0x0002 D054
Description	Port configuration register for IO GPIO20
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO20	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_cs_flash sel 5'd2 -- wifi_gpio_20		RW	0x00
		0x00	SEL_0 xspi_cs_flash
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_20
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO21

Address offset	0x0002 D058
Description	Port configuration register for IO GPIO21
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO21	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_1 sel 5'd2 -- wifi_gpio_21		RW	0x00
		0x00	SEL_0 xspi_data_1
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_21
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO22

Address offset	0x0002 D05C
Description	Port configuration register for IO GPIO22
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO22	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_2 sel 5'd2 -- wifi_gpio_22		RW	0x00
		0x00	SEL_0 xspi_data_2
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_22
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO23

Address offset	0x0002 D060
Description	Port configuration register for IO GPIO23
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO23	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_3 sel 5'd2 -- wifi_gpio_23		RW	0x00
		0x00	SEL_0 xspi_data_3
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_23
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO24

Address offset	0x0002 D064
Description	Port configuration register for IO GPIO24
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO24	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_clk sel 5'd2 -- wifi_gpio_24		RW	0x00
		0x00	SEL_0 xspi_clk
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_24
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO25

Address offset	0x0002 D068
Description	Port configuration register for IO GPIO25
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO25	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_0 sel 5'd2 -- wifi_gpio_25		RW	0x00
		0x00	SEL_0 xspi_data_0
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_25
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO26

Address offset	0x0002 D06C
Description	Port configuration register for IO GPIO26
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO26	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_4 sel 5'd2 -- wifi_gpio_26 sel 5'd4 -- spi0_cs1 sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_0 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_0 sel 5'd12 -- debug_bus_13 sel 5'd16 -- spi1_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt0_1_n sel 5'd19 -- gpt1_0_n sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt_infrared sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- ble_rfc_gpi_3 sel 5'd30 -- sdio_oob_irq sel 5'd31 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_data_4
		0x02	SEL_2 wifi_gpio_26
		0x03	SEL_3 reserved
		0x04	SEL_4 spi0_cs1
		0x05	SEL_5 uart0_rts
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt0_0
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 wake_observe_bus_0
		0x0C	SEL_12 debug_bus_13
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs2
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt0_1_n
		0x13	SEL_19 gpt1_0_n
		0x14	SEL_20 coex_grant
		0x15	SEL_21 coex_req
		0x16	SEL_22 ble_rfc_gpo_4
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 gpt_infrared
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 ble_rfc_gpi_3
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_oob_irq
		0x1F	SEL_31 uart2_tx

:IOMUX:CTL_COMMON_GPIO27

Address offset	0x0002 D070
Description	Port configuration register for IO GPIO27
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO27	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_5 sel 5'd2 -- wifi_gpio_27 sel 5'd4 -- spi0_clk sel 5'd5 -- uart0_tx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd11 -- wake_observe_bus_1 sel 5'd12 -- debug_bus_14 sel 5'd16 -- spi1_cs3 sel 5'd18 -- gpt0_0_n sel 5'd19 -- gpt1_1_n sel 5'd20 -- coex_req sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd31 -- uart2_rts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_data_5
		0x02	SEL_2 wifi_gpio_27
		0x03	SEL_3 reserved
		0x04	SEL_4 spi0_clk
		0x05	SEL_5 uart0_tx
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt0_1
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_1
		0x0C	SEL_12 debug_bus_14
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs3
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt0_0_n
		0x13	SEL_19 gpt1_1_n
		0x14	SEL_20 coex_req
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_5
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 uart2_rts

:IOMUX:CTL_COMMON_GPIO28

Address offset	0x0002 D074
Description	Port configuration register for IO GPIO28
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO28	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_6 sel 5'd2 -- wifi_gpio_28 sel 5'd4 -- spi0_miso sel 5'd5 -- uart0_rx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_2 sel 5'd11 -- wake_observe_bus_2 sel 5'd12 -- debug_bus_15 sel 5'd16 -- spi1_cs4 sel 5'd18 -- gpt0_0_n sel 5'd19 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_2 sel 5'd24 -- gpt0_pre_event sel 5'd25 -- ble_rfc_gpi_3 sel 5'd31 -- uart2_cts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_data_6
		0x02	SEL_2 wifi_gpio_28
		0x03	SEL_3 reserved
		0x04	SEL_4 spi0_miso
		0x05	SEL_5 uart0_rx
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt0_2
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_2
		0x0C	SEL_12 debug_bus_15
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs4
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt0_0_n
		0x13	SEL_19 gpt1_2_n
		0x14	SEL_20 coex_priority
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_6
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 gpt0_pre_event
		0x19	SEL_25 ble_rfc_gpi_3
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 uart2_cts

:IOMUX:CTL_COMMON_GPIO29

Address offset	0x0002 D078
Description	Port configuration register for IO GPIO29
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO29	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_7 sel 5'd2 -- wifi_gpio_29 sel 5'd4 -- spi0_mosi sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt0_3 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_3 sel 5'd12 -- i2s_mclk sel 5'd16 -- spi1_cs4 sel 5'd17 -- ext_clk sel 5'd18 -- gpt0_1_n sel 5'd19 -- gpt1_3_n sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_3 sel 5'd30 -- sdio_oob_irq sel 5'd31 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_data_7
		0x02	SEL_2 wifi_gpio_29
		0x03	SEL_3 reserved
		0x04	SEL_4 spi0_mosi
		0x05	SEL_5 uart0_cts
		0x06	SEL_6 i2c1_data
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt0_3
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 wake_observe_bus_3
		0x0C	SEL_12 i2s_mclk
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi1_cs4
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt0_1_n
		0x13	SEL_19 gpt1_3_n
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_7
		0x17	SEL_23 ant_sel_3
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_oob_irq
		0x1F	SEL_31 uart2_rx

:IOMUX:CTL_COMMON_GPIO30

Address offset	0x0002 D07C
Description	Port configuration register for IO GPIO30
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO30	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_dqs sel 5'd2 -- wifi_gpio_30 sel 5'd3 -- xspi_reset_flash sel 5'd4 -- xspi_reset_ram sel 5'd5 -- i2c1_clk sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_4 sel 5'd12 -- xspi_cs_ram sel 5'd16 -- spi0_cs2 sel 5'd17 -- spi0_cs2 sel 5'd18 -- gpt0_2_n sel 5'd19 -- coex_grant sel 5'd20 -- coex_req sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- gpt1_pre_event sel 5'd29 -- gpt0_pre_event sel 5'd30 -- sdio_d3 sel 5'd31 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_dqs
		0x02	SEL_2 wifi_gpio_30
		0x03	SEL_3 xspi_reset_flash
		0x04	SEL_4 xspi_reset_ram
		0x05	SEL_5 i2c1_clk
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 wake_observe_bus_4
		0x0C	SEL_12 xspi_cs_ram
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs2
		0x11	SEL_17 spi0_cs2
		0x12	SEL_18 gpt0_2_n
		0x13	SEL_19 coex_grant
		0x14	SEL_20 coex_req
		0x15	SEL_21 ble_rftrc
		0x16	SEL_22 ble_rfc_gpo_4
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 cca
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 swo_m3
		0x1B	SEL_27 swo_m33
		0x1C	SEL_28 gpt1_pre_event
		0x1D	SEL_29 gpt0_pre_event
		0x1E	SEL_30 sdio_d3
		0x1F	SEL_31 uart2_tx

:IOMUX:CTL_COMMON_GPIO31

Address offset	0x0002 D080
Description	Port configuration register for IO GPIO31
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO31	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_31 sel 5'd3 -- xspi_reset_flash sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_rts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_tx sel 5'd16 -- spi0_cs3 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_1_n sel 5'd19 -- gpt0_0_n sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt_infrared sel 5'd25 -- ble_rfc_gpi_3 sel 5'd30 -- sdio_d2 sel 5'd31 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_31
		0x03	SEL_3 xspi_reset_flash
		0x04	SEL_4 spi1_cs1
		0x05	SEL_5 uart1_rts
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs3
		0x11	SEL_17 ext_clk
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 gpt0_0_n
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_6
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 gpt_infrared
		0x19	SEL_25 ble_rfc_gpi_3
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_d2
		0x1F	SEL_31 uart2_tx

:IOMUX:CTL_COMMON_GPIO32

Address offset	0x0002 D084
Description	Port configuration register for IO GPIO32
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO32	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_32 sel 5'd3 -- spi1_cs1 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_5 sel 5'd16 -- spi0_cs3 sel 5'd18 -- gpt1_0_n sel 5'd19 -- gpt0_1_n sel 5'd20 -- coex_req sel 5'd23 -- ant_sel_1 sel 5'd30 -- sdio_d1 sel 5'd31 -- uart2_rts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_32
		0x03	SEL_3 spi1_cs1
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart1_tx
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 wake_observe_bus_5
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs3
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 gpt0_1_n
		0x14	SEL_20 coex_req
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_d1
		0x1F	SEL_31 uart2_rts

:IOMUX:CTL_COMMON_GPIO33

Address offset	0x0002 D088
Description	Port configuration register for IO GPIO33
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO33	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_33 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_2 sel 5'd10 -- dcan_tx sel 5'd16 -- spi0_cs4 sel 5'd18 -- gpt1_0_n sel 5'd19 -- gpt0_2_n sel 5'd20 -- coex_grant sel 5'd23 -- ant_sel_2 sel 5'd24 -- gpt1_pre_event sel 5'd25 -- ble_rfc_gpi_2 sel 5'd30 -- sdio_d0 sel 5'd31 -- uart2_cts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_33
		0x03	SEL_3 reserved
		0x04	SEL_4 spi1_miso
		0x05	SEL_5 uart1_rx
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt1_2
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs4
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 gpt0_2_n
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 gpt1_pre_event
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_d0
		0x1F	SEL_31 uart2_cts

:IOMUX:CTL_COMMON_GPIO34

Address offset	0x0002 D08C
Description	Port configuration register for IO GPIO34
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO34	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_34 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_cts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_rx sel 5'd16 -- spi0_cs2 sel 5'd18 -- gpt1_1_n sel 5'd19 -- gpt0_3_n sel 5'd20 -- coex_req sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_3 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd30 -- sdio_clk sel 5'd31 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_ram
		0x02	SEL_2 wifi_gpio_34
		0x03	SEL_3 reserved
		0x04	SEL_4 spi1_mosi
		0x05	SEL_5 uart1_cts
		0x06	SEL_6 i2c1_data
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt1_3
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs2
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 gpt0_3_n
		0x14	SEL_20 coex_req
		0x15	SEL_21 reserved
		0x16	SEL_22 ble_rfc_gpo_7
		0x17	SEL_23 ant_sel_3
		0x18	SEL_24 reserved
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 sdio_clk
		0x1F	SEL_31 uart2_rx

:IOMUX:CTL_COMMON_GPIO35

Address offset	0x0002 D090
Description	Port configuration register for IO GPIO35
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO35	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_flash sel 5'd2 -- wifi_gpio_35 sel 5'd3 -- spi1_clk sel 5'd4 -- xspi_reset_ram sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_1 sel 5'd10 -- dcan_rx sel 5'd11 -- i2c1_data sel 5'd12 -- xspi_cs_ram sel 5'd16 -- spi0_cs4 sel 5'd17 -- spi0_cs3 sel 5'd18 -- gpt0_2_n sel 5'd19 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt1_pre_event sel 5'd25 -- ble_rfc_gpi_2 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- xspi_dqs sel 5'd29 -- coex_req sel 5'd30 -- sdio_cmd sel 5'd31 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_flash
		0x02	SEL_2 wifi_gpio_35
		0x03	SEL_3 spi1_clk
		0x04	SEL_4 xspi_reset_ram
		0x05	SEL_5 uart1_rx
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_data1
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt0_1
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 i2c1_data
		0x0C	SEL_12 xspi_cs_ram
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 spi0_cs4
		0x11	SEL_17 spi0_cs3
		0x12	SEL_18 gpt0_2_n
		0x13	SEL_19 gpt1_2_n
		0x14	SEL_20 coex_priority
		0x15	SEL_21 ble_rftrc
		0x16	SEL_22 ble_rfc_gpo_5
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 gpt1_pre_event
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 swo_m3
		0x1B	SEL_27 swo_m33
		0x1C	SEL_28 xspi_dqs
		0x1D	SEL_29 coex_req
		0x1E	SEL_30 sdio_cmd
		0x1F	SEL_31 uart2_rx

:IOMUX:CTL_COMMON_GPIO36

Address offset	0x0002 D094
Description	Port configuration register for IO GPIO36
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO36	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- fast_clk_req sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_36 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- sdio_mmc_wp sel 5'd11 -- wake_observe_bus_13 sel 5'd12 -- debug_bus_1 sel 5'd19 -- coex_req sel 5'd20 -- coex_grant sel 5'd21 -- fast_clk_req sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_1 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_2		RW	0x00
		0x00	SEL_0 fast_clk_req
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_36
		0x03	SEL_3 sdio_mmc_pow2
		0x04	SEL_4 sdio_mmc_wp
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_13
		0x0C	SEL_12 debug_bus_1
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 coex_req
		0x14	SEL_20 coex_grant
		0x15	SEL_21 fast_clk_req
		0x16	SEL_22 ble_rfc_gpo_5
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 cca
		0x19	SEL_25 ble_rfc_gpi_2
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO37

Address offset	0x0002 D098
Description	Port configuration register for IO GPIO37
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO37	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_37 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- sdio_mmc_wp sel 5'd11 -- wake_observe_bus_12 sel 5'd12 -- debug_bus_0 sel 5'd18 -- coex_req sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- fast_clk_req sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_37
		0x03	SEL_3 sdio_mmc_pow1
		0x04	SEL_4 sdio_mmc_wp
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 wake_observe_bus_12
		0x0C	SEL_12 debug_bus_0
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 coex_req
		0x13	SEL_19 sdio_oob_irq
		0x14	SEL_20 coex_grant
		0x15	SEL_21 fast_clk_req
		0x16	SEL_22 ble_rfc_gpo_4
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 cca
		0x19	SEL_25 ble_rfc_gpi_1
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO38

Address offset	0x0002 D09C
Description	Port configuration register for IO GPIO38
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO38	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_38 sel 5'd3 -- ext_clk sel 5'd4 -- spi1_clk sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_tx sel 5'd18 -- gpt1_1_n sel 5'd20 -- coex_grant sel 5'd23 -- ant_sel_0 sel 5'd29 -- coex_req sel 5'd30 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_38
		0x03	SEL_3 ext_clk
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart0_cts
		0x06	SEL_6 i2c1_clk
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt1_0
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_1_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_req
		0x1E	SEL_30 uart2_rx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO39

Address offset	0x0002 D0A0
Description	Port configuration register for IO GPIO39
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO39	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_39 sel 5'd3 -- uart0_rx sel 5'd4 -- spi1_miso sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_rx sel 5'd11 -- xspi_dqs sel 5'd18 -- gpt1_0_n sel 5'd20 -- coex_req sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_1 sel 5'd29 -- coex_priority sel 5'd30 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_ram
		0x02	SEL_2 wifi_gpio_39
		0x03	SEL_3 uart0_rx
		0x04	SEL_4 spi1_miso
		0x05	SEL_5 uart0_rts
		0x06	SEL_6 i2c1_data
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt1_1
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 xspi_dqs
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt1_0_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_req
		0x15	SEL_21 coex_grant
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_priority
		0x1E	SEL_30 uart2_tx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO40

Address offset	0x0002 D0A4
Description	Port configuration register for IO GPIO40
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO40	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_40 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart0_tx sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_2 sel 5'd16 -- gpt1_pre_event sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_2 sel 5'd29 -- coex_grant sel 5'd30 -- uart2_rts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_40
		0x03	SEL_3 reserved
		0x04	SEL_4 spi1_mosi
		0x05	SEL_5 uart0_tx
		0x06	SEL_6 reserved
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 pdm_data1
		0x09	SEL_9 gpt1_2
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 gpt1_pre_event
		0x11	SEL_17 gpt0_pre_event
		0x12	SEL_18 gpt1_2_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_priority
		0x15	SEL_21 reserved
		0x16	SEL_22 gpt_infrared
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_grant
		0x1E	SEL_30 uart2_rts
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO41

Address offset	0x0002 D0A8
Description	Port configuration register for IO GPIO41
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO41	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_41 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_cts sel 5'd7 -- i2s_data0 sel 5'd9 -- gpt0_0 sel 5'd16 -- gpt1_pre_event sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt0_1_n sel 5'd20 -- coex_grant sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_0 sel 5'd29 -- coex_grant sel 5'd30 -- uart2_rx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_41
		0x03	SEL_3 reserved
		0x04	SEL_4 spi1_miso
		0x05	SEL_5 uart1_cts
		0x06	SEL_6 reserved
		0x07	SEL_7 i2s_data0
		0x08	SEL_8 reserved
		0x09	SEL_9 gpt0_0
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 gpt1_pre_event
		0x11	SEL_17 gpt0_pre_event
		0x12	SEL_18 gpt0_1_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_grant
		0x15	SEL_21 reserved
		0x16	SEL_22 gpt_infrared
		0x17	SEL_23 ant_sel_0
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_grant
		0x1E	SEL_30 uart2_rx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO42

Address offset	0x0002 D0AC
Description	Port configuration register for IO GPIO42
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO42	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_42 sel 5'd3 -- uart1_rx sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_rts sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd10 -- dcan_rx sel 5'd11 -- xspi_dqs sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_req sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_1 sel 5'd29 -- coex_req sel 5'd30 -- uart2_tx		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_reset_ram
		0x02	SEL_2 wifi_gpio_42
		0x03	SEL_3 uart1_rx
		0x04	SEL_4 spi1_mosi
		0x05	SEL_5 uart1_rts
		0x06	SEL_6 i2c0_data
		0x07	SEL_7 i2s_wclk
		0x08	SEL_8 pdm_data0
		0x09	SEL_9 gpt0_1
		0x0A	SEL_10 dcan_rx
		0x0B	SEL_11 xspi_dqs
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt0_0_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_req
		0x15	SEL_21 coex_grant
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_1
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_req
		0x1E	SEL_30 uart2_tx
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO43

Address offset	0x0002 D0B0
Description	Port configuration register for IO GPIO43
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO43	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_43 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_2 sel 5'd10 -- dcan_tx sel 5'd18 -- gpt0_2_n sel 5'd20 -- coex_priority sel 5'd23 -- ant_sel_2 sel 5'd29 -- coex_priority sel 5'd30 -- uart2_rts		RW	0x00
		0x00	SEL_0 reserved
		0x01	SEL_1 xspi_cs_ram
		0x02	SEL_2 wifi_gpio_43
		0x03	SEL_3 reserved
		0x04	SEL_4 spi1_clk
		0x05	SEL_5 uart1_tx
		0x06	SEL_6 i2c0_clk
		0x07	SEL_7 i2s_bclk
		0x08	SEL_8 pdm_bclk
		0x09	SEL_9 gpt0_2
		0x0A	SEL_10 dcan_tx
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 gpt0_2_n
		0x13	SEL_19 reserved
		0x14	SEL_20 coex_priority
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 ant_sel_2
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 coex_priority
		0x1E	SEL_30 uart2_rts
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO44

Address offset	0x0002 D0B4
Description	Port configuration register for IO GPIO44
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO44	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_clk_input sel 5'd2 -- wifi_gpio_44		RW	0x00
		0x00	SEL_0 xspi_clk_input
		0x01	SEL_1 reserved
		0x02	SEL_2 wifi_gpio_44
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:PROCCOMP

Address offset	0x0002 D0BC
Description	The IO Process compensation is used to override the process compensation bits form the eFuse:IO Process: Common for all IOs.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED_16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
14:12	FUSE_PROG_IO_P	PROG IO P value from fuse ROM		RO	0x0
11	RESERVED_11	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
10:8	FUSE_PROG_IO_N	PROG IO N value from fuse ROM		RO	0x0
7	MEM_PROGIO_P_OVERRIDE	The field selects the PROGIO P override between Fuse ROM and MMR		RW	0
		0	DISABLE Use Fuse ROM (bits (14:12))
		1	ENABLE Use MMR (bits (6:4))
6:4	MEM_PROGIO_P_VAL	This field configures the value of override PROG IO N		RW	0x0
3	MEM_PROGIO_N_OVERRIDE	The field selects the PROGIO N override between Fuse ROM and MMR		RW	0
		0	DISABLE Use Fuse ROM (bits (10:8))
		1	ENABLE Use MMR (bits (2:0))
2:0	MEM_PROGIO_N_VAL	This field configures the value of override PROG IO N		RW	0x0

:IOMUX:CTL_COMMON_GPIO45

Address offset	0x0002 D0C0
Description	Port configuration register for IO GPIO45
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO45	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_0_ram		RW	0x00
		0x00	SEL_0 xspi_data_0_ram
		0x01	SEL_1 reserved
		0x02	SEL_2 reserved
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO46

Address offset	0x0002 D0C4
Description	Port configuration register for IO GPIO46
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO46	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_1_ram		RW	0x00
		0x00	SEL_0 xspi_data_1_ram
		0x01	SEL_1 reserved
		0x02	SEL_2 reserved
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO47

Address offset	0x0002 D0C8
Description	Port configuration register for IO GPIO47
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO47	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_2_ram		RW	0x00
		0x00	SEL_0 xspi_data_2_ram
		0x01	SEL_1 reserved
		0x02	SEL_2 reserved
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL_COMMON_GPIO48

Address offset	0x0002 D0CC
Description	Port configuration register for IO GPIO48
Type	RW

Bits	Field Name	Description		Type	Reset
31:5	RESERVED_5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
4:0	MEM_IO_SEL_GPIO48	Pinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_3_ram		RW	0x00
		0x00	SEL_0 xspi_data_3_ram
		0x01	SEL_1 reserved
		0x02	SEL_2 reserved
		0x03	SEL_3 reserved
		0x04	SEL_4 reserved
		0x05	SEL_5 reserved
		0x06	SEL_6 reserved
		0x07	SEL_7 reserved
		0x08	SEL_8 reserved
		0x09	SEL_9 reserved
		0x0A	SEL_10 reserved
		0x0B	SEL_11 reserved
		0x0C	SEL_12 reserved
		0x0D	SEL_13 reserved
		0x0E	SEL_14 reserved
		0x0F	SEL_15 reserved
		0x10	SEL_16 reserved
		0x11	SEL_17 reserved
		0x12	SEL_18 reserved
		0x13	SEL_19 reserved
		0x14	SEL_20 reserved
		0x15	SEL_21 reserved
		0x16	SEL_22 reserved
		0x17	SEL_23 reserved
		0x18	SEL_24 reserved
		0x19	SEL_25 reserved
		0x1A	SEL_26 reserved
		0x1B	SEL_27 reserved
		0x1C	SEL_28 reserved
		0x1D	SEL_29 reserved
		0x1E	SEL_30 reserved
		0x1F	SEL_31 reserved

:IOMUX:CTL0_GPIO45

Address offset	0x0002 E000
Description	CFG register for IO GPIO45. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO45	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO45	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO45	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO45	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO45_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO45

Address offset	0x0002 E004
Description	Pull control register of IO GPIO45 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO45_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO45_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO45	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO45

Address offset	0x0002 E008
Description	Control register of IO GPIO45 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO45	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO45	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO45_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO45_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO45

Address offset	0x0002 E00C
Description	Event control register for IO GPIO45 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO45_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO45	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO45	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO46

Address offset	0x0002 F000
Description	CFG register for IO GPIO46. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO46	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO46	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO46	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO46	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO46_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO46

Address offset	0x0002 F004
Description	Pull control register of IO GPIO46 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO46_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO46_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO46	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO46

Address offset	0x0002 F008
Description	Control register of IO GPIO46 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO46	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO46	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO46_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO46_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO46

Address offset	0x0002 F00C
Description	Event control register for IO GPIO46 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO46_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO46	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO46	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO47

Address offset	0x0003 0000
Description	CFG register for IO GPIO47. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO47	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO47	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO47	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO47	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO47_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO47

Address offset	0x0003 0004
Description	Pull control register of IO GPIO47 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO47_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO47_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO47	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO47

Address offset	0x0003 0008
Description	Control register of IO GPIO47 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO47	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO47	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO47_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO47_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO47

Address offset	0x0003 000C
Description	Event control register for IO GPIO47 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO47_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO47	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO47	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection

:IOMUX:CTL0_GPIO48

Address offset	0x0003 1000
Description	CFG register for IO GPIO48. This register configures the corresponding pad
Type	RW

Bits	Field Name	Description		Type	Reset
31:15	RESERVED_15	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
14	MEM_IO_DS_GPIO48	This field controls the IO drive strength		RW	0
		0	LOW IO drives low power
		1	HIGH IO drives high power
13	MEM_IO_GZ_GPIO48	This field controls the [OUTDIS] override		RW	0
		0	DISABLE Disable the override
		1	ENABLE Enable the override
12	MEM_IO_GZ_VAL_GPIO48	This field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled		RW	1
		0	ENABLE Output from the pad is enabled
		1	DISABLE Output from the pad is disabled
11	MEM_IE_GPIO48	This field enables the receiver operation from the pad		RW	1
		0	DISABLE Disable the receiver operation
		1	ENABLE Enable the receiver operation
10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0
9:8	RESERVED_8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	GPIO48_IO_GZ_VALUE	The field gives the status of [OUTDIS]		RO	0
		Read 0	ENABLED Output is enabled
		Read 1	DISABLED Output is disabled
5:0	RESERVED_0	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00

:IOMUX:CTL1_GPIO48

Address offset	0x0003 1004
Description	Pull control register of IO GPIO48 This register configures the pull control
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	GPIO48_IO_PULL_DOWN_LVL	This field gives the IO pull down level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull down
8	GPIO48_IO_PULL_UP_LVL	This field gives the IO pull up level status		RO	0
		Read 0	DISABLED Pull disabled
		Read 1	ENABLED Pull up
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MEM_IO_PULL_GPIO48	The fields defines the pull control		RW	0x1
		0x0	IPCTRL IP Pull Control
		0x1	UP Pull up
		0x2	DOWN Pull down
		0x3	DISABLE Pull disable

:IOMUX:CTL2_GPIO48

Address offset	0x0003 1008
Description	Control register of IO GPIO48 This register controls the IO state
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED_10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	MEM_IO_OUT_OVR_GPIO48	This field contols the override on output		RW	0
		0	DISABLE Output controlled by IP
		1	ENABLE Enable override on output
8	MEM_IO_OUT_VAL_GPIO48	This field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE		RW	0
		0	LOW IO drives 0
		1	HIGH IO drives 1
7:2	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1	GPIO48_GPIO_FROM_PAD_VAL_SYNC	This field captures the sychronized(to SOC clock) received value		RO	0
0	GPIO48_IO_IN_LVL	This field captures the received value from pad		RO	0

:IOMUX:CTL3_GPIO48

Address offset	0x0003 100C
Description	Event control register for IO GPIO48 This register controls the Event configuration and behaviour
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED_4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	GPIO_RIS_CLR_GPIO48_WRCL	This bit is to be used to generate CLR pulse for the event		WO	0
		Write 0	NOEFF No effect
		Write 1	CLEAR Clear the event
2	MEM_ELP_GPIO_IO_EV_POL_GPIO48	This field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL		RW	0
		0	HIGH Non Inverted polarity
		1	LOW Inverted polarity
1:0	MEM_EVT_CFG_GPIO48	This field is to be configured to define the IO detection method		RW	0x0
		0x0	MASK Masking the event
		0x1	POS_EDGE Rising edge/Positive edge detection
		0x2	NEG_EDGE Falling edge/Negative edge detection
		0x3	LEVEL Level detection