ICACHE

ICACHE

This section provides information on the ICACHE Module Instance within this product. Each of the registers within the Module Instance is described separately below.

ICACHE Registers Mapping Summary

:ICACHE Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
MOD_VERSION	RO	32	0x6880 0800	0x0000 0000
CTRL	RW	32	0x0000 0000	0x0000 0004
STATUS	RO	32	0x0000 0000	0x0000 0008
CACHE_ADDRESS_LOW	RW	32	0x0000 0000	0x0000 0010
CACHE_ADDRESS_HIGH	RW	32	0x0000 0000	0x0000 0018
REGISTER_ADDRESS	RW	32	0x0000 0000	0x0000 0020
HIT_COUNTER	RW	32	0x0000 0000	0x0000 0040
MISS_COUNTER	RW	32	0x0000 0000	0x0000 0044
IRQ_STATUS_RAW	RW	32	0x0000 0000	0x0000 0080
IRQ_STATUS_MASK	RW	32	0x0000 0000	0x0000 0084
IRQ_ENABLE_SET	RW	32	0x0000 0000	0x0000 0088
IRQ_ENABLE_CLR	RW	32	0x0000 0000	0x0000 008C

ICACHE Instances Register Mapping Summary

ICACHE Register Descriptions

:ICACHE Common Register Descriptions

:ICACHE:MOD_VERSION

Address offset	0x0000 0000
Description	The Module and Version Register identifies the module identifier and revision of the icache module.
Type	RO

Bits	Field Name	Description			Type	Reset
31:30	SCHEME	Module Scheme			RO	0x1
29:28	BU	Module Business Unit			RO	0x2
27:16	MODULE_ID	Module ID			RO	0x880
15:11	RTL_VERSION	RTL version			RO	0x01
10:8	MAJOR_REVISION	Major Revision			RO	0x0
7:6	CUSTOM_REVISION	Custom Revision			RO	0x0
5:0	MINOR_REVISION	Minor revision			RO	0x00

:ICACHE:CTRL

Address offset	0x0000 0004
Description	The control register defines the size of the remote cache data storage memory to use and whether the icache controller is enabled.
Type	RW

Bits	Field Name	Description			Type	Reset
31	MEM_CENABLE	.			RW	0
30	MEM_RENABLE	.			RW	0
29:0	Reserved				RO	0x0000 0000

:ICACHE:STATUS

Address offset	0x0000 0008
Description	The Status register displays the state of the icache controller.
Type	RO

Bits	Field Name	Description			Type	Reset
31	OK_TO_GO	The ok_to_go status bit indicates the Tag/LRU Ram has been initialized and the cache is in an operable state.			RO	0
30:0	Reserved				RO	0x0000 0000

:ICACHE:CACHE_ADDRESS_LOW

Address offset	0x0000 0010
Description	The Cache Address Low Register defines start of the cacheable space. The icache controller can cache up to a range of 8MB of of the target Flash as defined by CAL gt= CachedRange lt= CAH. This register is write protected when cenable is set.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	MEM_ADDR_LOW	The addr_lo defines the cache low address[31:12] for the icache controller to cache. The remaining bits 10:0 are assumed to be zero			RW	0x0 0000
11:0	Reserved				RO	0x000

:ICACHE:CACHE_ADDRESS_HIGH

Address offset	0x0000 0018
Description	The L1 Cache Address High Register defines end of the L1 cacheable space. The L1 cache can cache up to a range of 8MB of of the target Flash as defined by CAL >= CachedRange <= CAH. This register is write protected when cenable is set.
Type	RW

Bits	Field Name	Description			Type	Reset
31:12	MEM_ADDR_HIGH	The addr_hi defines the L1 high address[31:12] for the L1 to cache. The remaining bits 10:0 are assumed to be ones.			RW	0x0 0000
11:0	Reserved				RO	0x000

:ICACHE:REGISTER_ADDRESS

Address offset	0x0000 0020
Description	The RAM Address register defines the upper 17 bits of address for the RAM when renable is set. This register is write protected when renable is set
Type	RW

Bits	Field Name	Description			Type	Reset
31:15	MEM_SEG_ADDR	The seg_addr defines RAM address[31:15] value for RAM access .			RW	0x0 0000
14:0	Reserved				RO	0x0000

:ICACHE:HIT_COUNTER

Address offset	0x0000 0040
Description	The HIT Counter register holds the number of cache Hits to the internal cache
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_HIT_COUNTER	The hit Counts the number of hits to the L1 cache. Writing zero to this register will clear its contents.			RW	0x0000 0000

:ICACHE:MISS_COUNTER

Address offset	0x0000 0044
Description	The MISS Counter register holds the number of cache misses to the internal cache .
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_MISS_COUNTER	The miss Counts the number of misses to the L1 cache. Writing zero to this register will clear its contents.			RW	0x0000 0000

:ICACHE:IRQ_STATUS_RAW

Address offset	0x0000 0080
Description	The Interrupt Raw Status Register holds the raw status of the icache error interrupts .
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved				RO	0x0000 0000
1	WR_HIT	The wr_hit bit indicates a write to the cacheable range has occured potentially causing a coherency issue and the L1 is logically disabled while this bit is a '1'. Write 1 to set the wr_hit status for diagnostic purposes. Writing a 0 has no effect.			RW	0
0	WR_ERR	The wr_err bit indicates a write error has occured to the remote cache data storage memory and the L1 is logically disabled while this bit is a '1'. Write 1 to set the wr_err status for diagnostic purposes. Writing a 0 has no effect.			RW	0

:ICACHE:IRQ_STATUS_MASK

Address offset	0x0000 0084
Description	The Interrupt Masked Status Register holds the masked status for the icache error interrupts. Writing to this register will EOI the interrupt, that is if another interrupt is pending, a new pulse interrupt will be generated .
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved				RO	0x0000 0000
1	MEM_HIT	The wr_hit bit indicates a write to the cacheable range has occured potentially causing a coherency issue and the L1 is logically disabled while this bit is a '1'. Write 1 to clear the wr_hit status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field.			RW	0
0	MEM_ERR	The wr_err bit indicates a write error has occured to the remote cache data storage memory and the L1 is logically disabled while this bit is a '1'. Write 1 to clear the wr_err status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field.			RW	0

:ICACHE:IRQ_ENABLE_SET

Address offset	0x0000 0088
Description	The Interrupt Enable Set Register holds the interrupt enable status of the icache error interrupts .
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved				RO	0x0000 0000
1	EN_WR_HIT	Interrupt Enable Set for wr_hit error bit. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.			RW	0
0	EN_WR_ERR	Interrupt Enable Set for wr_err error bit. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.			RW	0

:ICACHE:IRQ_ENABLE_CLR

Address offset	0x0000 008C
Description	The Interrupt Enable Clear Register holds the interrupt enable status of the icache error interrupts.
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved				RO	0x0000 0000
1	EN_WR_HIT	Interrupt Enable Clear for wr_hit error bit. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect			RW	0
0	EN_WR_ERR	Interrupt Enable Clear for wr_err error bit. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.			RW	0