31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

2

WCLKINV

Inverts **WCLK** source (pad or internal) when set.
0: Not inverted
1: Inverted

RW

0

1:0

WBCLKSRC

Selects **WCLK**/**BCLK** source for **AIF**.

RW

0x0

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

ENDFRAMIDX

Defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes AIF. Note that before doing so, all other configuration must have been done, and [AIFINPTNXT.*]/[AIFOPTNXT.*] must have been loaded.

RW

0x00

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

5:4

AD1

Configures the **AD1** audio data pin usage:
0x3: Reserved

RW

0x0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

1:0

AD0

Configures the **AD0** audio data pin usage:
0x3: Reserved

RW

0x0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:8

DATADELAY

The number of **BCLK** periods between a **WCLK** edge and **MSB** of the first word in a phase:
0x00: **LJF** and **DSP** format
0x01: **I2S** and **DSP** format
0x02: **RJF** format
...
0xFF: **RJF** format
Note: When 0, **MSB** of the next word will be output in the idle period between **LSB** of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.

RW

0x01

7

LEN32

The size of each word stored to or loaded from memory:

RW

0

6

SMPLEDGE

On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.

RW

1

5

DUALPHASE

Selects dual- or single-phase format.
0: Single-phase: **DSP** format
1: Dual-phase: **I2S**, **LJF** and **RJF** formats

RW

1

4:0

WORDLEN

Number of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.
Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by [MEM_LEN_24]. Bit widths that differ from this alignment will either be truncated or zero padded.

RW

0x10

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00 0000

7:0

MASK

Bit-mask indicating valid channels in a frame on AD0.
In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.

RW

0x03

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7:0

MASK

Bit-mask indicating valid channels in a frame on AD1.
In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.

RW

0x03

31:0

PTR

Pointer to the first byte in the next **DMA** input buffer.
The read value equals the last written value until the currently used **DMA** input buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by [IRQFLAGS-AIFDMAIN].
At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*].
The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, [IRQFLAGS.PTRERR] will be raised and all input pins will be disabled.

RW

0x0000 0000

31:0

PTR

Value of the **DMA** input buffer pointer currently used by the **DMA** controller. Incremented by 1 (byte) or 2 (word) for each **AHB** access.

RO

0x0000 0000

31:0

PTR

Pointer to the first byte in the next **DMA** output buffer.
The read value equals the last written value until the currently used **DMA** output buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by [IRQFLAGS.AIFDMAOUT].
At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*]. At this time, the first two samples will be fetched from memory.
The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, [IRQFLAGS.PTRERR] will be raised and all output pins will be disabled.

RW

0x0000 0000

31:0

PTR

Value of the **DMA** output buffer pointer currently used by the **DMA** controller Incremented by 1 (byte) or 2 (word) for each **AHB** access.

RO

0x0000 0000

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

2

OUTRDY

Low until the output pins are ready to be started by the samplestamp generator. When started (that is [STMPOTRIG.*] equals the **WCLK** counter) the bit goes back low.

RO

0

1

INRDY

Low until the input pins are ready to be started by the samplestamp generator. When started (that is [STMPINTRIG.*] equals the **WCLK** counter) the bit goes back low.

RO

0

0

STMPEN

Enables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.
When cleared, all samplestamp generator counters and capture values are cleared.

RW

0

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

CAPTVAL

The value of the samplestamp **XOSC** counter ([STMPXCNT.CURRVAL]) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected **WCLK**.
The value is cleared when [STMPCTL.STMPEN] = 0.
Note: Due to buffering and synchronization, **WCLK** is delayed by a small number of **BCLK** periods and clk periods.
Note: When calculating the fractional part of the sample stamp, [STMPXPER.*] may be less than this bit field.

RO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

VALUE

The number of 24 MHz clock cycles in the previous **WCLK** period (that is - the next value of the **XOSC** counter at the positive **WCLK** edge, had it not been reset to 0).
The value is cleared when [STMPCTL.STMPEN] = 0.

RO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

CAPTVAL

The value of the samplestamp **WCLK** counter ([STMPWCNT.CURRVAL]) last time an event was pulsed (event source selected in [EVENT:I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of positive **WCLK** edges since the samplestamp generator was enabled (not taking modification through [STMPWADD.*]/[STMPWSET.*] into account).
The value is cleared when [STMPCTL.STMPEN] = 0.

RO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

VALUE

Used to define when [STMPWCNT.*] is to be reset so number of **WCLK** edges are found for the size of the sample buffer. This is thus a modulo value for the **WCLK** counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).

RW

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

INSTRTWCNT

Compare value used to start the incoming audio streams.
This bit field shall equal the **WCLK** counter value during the **WCLK** period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first **DMA** input buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as inputs in [AIFDIRCFG.*].
- [AIFDMACFG.*] has been configured for the correct buffer size, and at least 32 **BCLK** cycle ticks have happened.
Note: To avoid false triggers, this bit field should be set higher than [STMPWPER.VALUE].

RW

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

OSTRTWCNT

OUT START WCNT:
Compare value used to start the outgoing audio streams.
This bit field must equal the **WCLK** counter value during the **WCLK** period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first **DMA** output buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as outputs in [AIFDIRCFG.*].
- [AIFDMACFG.*] has been configured for the correct buffer size, and 32 **BCLK** cycle ticks have happened.
- 2 samples have been preloaded from memory (examine the [AIFOUTPTR.*] register if necessary).
Note: The memory read access is only performed when required, that is channels 0/1 must be selected in [AIFWMASK0.*]/[AIFWMASK1.*].
Note: To avoid false triggers, this bit field should be set higher than [STMPWPER.VALUE].

RW

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

VALUE

**WCLK** counter modification: Sets the running **WCLK** counter equal to the written value.

WO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

VALINC

**WCLK** counter modification: Adds the written value to the running **WCLK** counter. If a positive edge of **WCLK** occurs at the same time as the operation, this will be taken into account.
To add a negative value, write "[STMPWPER.VALUE] - value".

WO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

VALUE

Each time [STMPXPER.*] is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.
When written, the register is reset to 0xFFFF (65535), regardless of the value written.
The minimum value can be used to detect extra **WCLK** pulses (this registers value will be significantly smaller than [STMPXPER.VALUE]).

RW

0xFFFF

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

CURRVAL

Current value of the **WCLK** counter

RO

0x0000

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

CURRVAL

Current value of the **XOSC** counter, latched when reading [STMPWCNT.*].

RO

0x0000

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

6

XCNTCPT

[IRQFLAGS.XCNTCPT] interrupt mask
0: Disable
1: Enable

RW

0

5

AIFDMAIN

[IRQFLAGS.AIFDMAIN] interrupt mask
0: Disable
1: Enable

RW

0

4

AIFDMAOUT

[IRQFLAGS.AIFDMAOUT] interrupt mask
0: Disable
1: Enable

RW

0

3

WCLKTOUT

[IRQFLAGS.WCLKTOUT] interrupt mask
0: Disable
1: Enable

RW

0

2

BUSERR

[IRQFLAGS.BUSERR] interrupt mask
0: Disable
1: Enable

RW

0

1

WCLKERR

[IRQFLAGS.WCLKERR] interrupt mask
0: Disable
1: Enable

RW

0

0

PTRERR

[IRQFLAGS.PTRERR] interrupt mask.
0: Disable
1: Enable

RW

0

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

6

XCNTCPT

Will be set when xcnt counter is captured either by events or software.
Needs to be cleared by software.

RO

0

5

AIFDMAIN

Set when condition for this bit field event occurs (auto cleared when input pointer is updated - [AIFINPTNXT.*]), see description of [AIFINPTNXT.*] register for details.

RO

0

4

AIFDMAOUT

Set when condition for this bit field event occurs (auto cleared when output pointer is updated - [AIFOPTNXT.*]), see description of [AIFOPTNXT.*] register for details

RO

0

3

WCLKTOUT

Set when the sample stamp generator does not detect a positive **WCLK** edge for 65535 clk periods. This signalizes that the internal or external **BCLK** and **WCLK** generator source has been disabled.
The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.WCLKTOUT]).

RO

0

2

BUSERR

Set when a **DMA** operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.BUSERR]).
Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.
INTERNAL_NOTE:
The I2S module is not monitoring the AHB bus error response, hence bus faults resulting from access to illegal addresses are not generated. It is best practice to detect and report such errors and, therefore, a ticket has been entered into the CDDS bug tracking database for the I2S module. The reference is CC26_I2S--BUG00011.
All versions of CC13xx/CC26xx Chameleon and Lizard are impacted, and there is no plans to change this behavior.

RO

0

1

WCLKERR

Set when:
- An unexpected **WCLK** edge occurs during the data delay period of a phase. Note unexpected **WCLK** edges during the word and idle periods of the phase are not detected.
- In dual-phase mode, when two **WCLK** edges are less than 4 **BCLK** cycles apart.
- In single-phase mode, when a **WCLK** pulse occurs before the last channel.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.WCLKERR]).

RO

0

0

PTRERR

Set when [AIFINPTNXT.*] or [AIFOPTNXT.*] has not been loaded with the next block address in time.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.PTRERR]).

RO

0

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

WO

0x000 0000

6

XCNTCPT

1: Sets the interrupt of [IRQFLAGS.XCNTCPT] (unless a auto clear criteria was given at the same time, in which the set will be ignored)

WO

0

5

AIFDMAIN

1: Sets the interrupt of [IRQFLAGS.AIFDMAIN] (unless a auto clear criteria was given at the same time, in which the set will be ignored)

WO

0

4

AIFDMAOUT

1: Sets the interrupt of [IRQFLAGS.AIFDMAOUT] (unless a auto clear criteria was given at the same time, in which the set will be ignored)

WO

0

3

WCLKTOUT

1: Sets the interrupt of [IRQFLAGS.WCLKTOUT]

WO

0

2

BUSERR

1: Sets the interrupt of [IRQFLAGS.BUSERR]

WO

0

1

WCLKERR

1: Sets the interrupt of [IRQFLAGS.WCLKERR]

WO

0

0

PTRERR

1: Sets the interrupt of [IRQFLAGS.PTRERR]

WO

0

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

WO

0x000 0000

6

XCNTCPT

1: Clears the interrupt of [IRQFLAGS.XCNTCPT] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

5

AIFDMAIN

1: Clears the interrupt of [IRQFLAGS.AIFDMAIN] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

4

AIFDMAOUT

1: Clears the interrupt of [IRQFLAGS.AIFDMAOUT] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

3

WCLKTOUT

1: Clears the interrupt of [IRQFLAGS.WCLKTOUT] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

2

BUSERR

1: Clears the interrupt of [IRQFLAGS.BUSERR] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

1

WCLKERR

1: Clears the interrupt of [IRQFLAGS.WCLKERR] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

0

PTRERR

1: Clears the interrupt of [IRQFLAGS.PTRERR] (unless a set criteria was given at the same time in which the clear will be ignored)

WO

0

31:10

RESERVED10

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

9:0

MDIV

An unsigned factor of the division ratio used to generate **MCLK** [2-1024]:
**MCLK** = MCUCLK/MDIV[Hz] **MCUCLK** is upto 96MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one **MCUCLK** period longer than the high phase.

RW

0x000

31:10

RESERVED10

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

9:0

BDIV

An unsigned factor of the division ratio used to generate **BCLK** [2-1024]:
**BCLK** = MCUCLK/BDIV[Hz] **MCUCLK** can be upto 96MHz.
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 0, the low phase of the clock is one **MCUCLK** period longer than the high phase.
If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 1 , the high phase of the clock is one **MCUCLK** period longer than the low phase.

RW

0x000

31:16

RESERVED16

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000

15:0

WDIV

If [AIFCLKCTL.WCLKPHASE.*] = 0, Single phase. **WCLK** is high one **BCLK** period and low WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods.
**WCLK** = **MCUCLK** / BDIV*(WDIV[9:0] + 1) [Hz] **MCUCLK** upto 96MHz.
If [AIFCLKCTL.WCLKPHASE.*] = 1, Dual phase. Each phase on **WCLK** (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods.
**WCLK **= **MCUCLK **/ BDIV*(2*WDIV[9:0]) [Hz]
If [AIFCLKCTL.WCLKPHASE.*] = 2, User defined. **WCLK** is high WDIV[7:0] (unsigned, [1-255]) **BCLK** periods and low WDIV[15:8] (unsigned, [1-255]) **BCLK** periods.
**WCLK** = **MCUCLK **/ (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]

RW

0x0000

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

3

MEN

0: **MCLK** geneartion disabled, 1: **MCLK** generation enabled

RW

0

2:1

WCLKPHASE

Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See [AIFWCLKDIV.WDIV.*]).

RW

0x0

0

WBEN

0: WCLK/BCLK geneartion disabled, 1: WCLK/BCLK generation enabled

RW

0

31:8

RESERVED8

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x00 0000

7

ADFSEN

ADFS enable field

RW

0

6:4

CLKSEL

Audio clock selection

RW

0x0

3:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

0

EN

0: **I2S** clock disabled
1: **I2S** clock enabled

RW

0

31:21

RESERVED21

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000

20:0

TREF

TREF value for ADFS

RW

0x00 0000

31:30

RESERVED30

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

29:20

DIV

ADFS div value field

RW

0x000

19:18

RESERVED18

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0

17

DELTASIGN

ADFS delta sign field

RW

0

16:0

DELTA

ADFS delta value field

RW

0x0 0000