I2C

This section provides information on the I2C Module Instance within this product. Each of the registers within the Module Instance is described separately below.

I2C module with DMA and FIFO capabilites INTERNAL_NOTE: [Functional Specification](https://confluence.itg.ti.com/display/WNG/Mx+I2C)

I2C Registers Mapping Summary

:I2C Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
GFCTL	RW	32	0x0000 0000	0x0000 0100
CSA	RW	32	0x0000 0000	0x0000 0104
CCTR	RW	32	0x0000 0000	0x0000 0108
CSR	RO	32	0x0000 0020	0x0000 010C
CTPR	RW	32	0x0000 0001	0x0000 0110
CCR	RW	32	0x0000 0000	0x0000 0114
CBMON	RO	32	0x0000 0003	0x0000 0118
TOAR	RW	32	0x0000 4000	0x0000 011C
TOAR2	RW	32	0x0000 0000	0x0000 0120
TCTR	RW	32	0x0000 0004	0x0000 0124
TSR	RO	32	0x0000 0000	0x0000 0128
RXDATA	RO	32	0x0000 0000	0x0000 012C
TXDATA	RW	32	0x0000 0000	0x0000 0130
TACKCTL	RW	32	0x0000 0000	0x0000 0134
FIFOCTL	RW	32	0x0000 0000	0x0000 0138
FIFOSR	RO	32	0x0000 0800	0x0000 013C
FCLKDIV	RW	32	0x0000 0000	0x0000 0140
PDBGCTL	RW	32	0x0000 0003	0x0000 0000
EVENT0_IMASK	RW	32	0x0000 0000	0x0000 0004
EVENT0_RIS	RO	32	0x0000 0000	0x0000 0008
EVENT0_MIS	RO	32	0x0000 0000	0x0000 000C
EVENT0_IEN	WO	32	0x0000 0000	0x0000 0010
EVENT0_IDIS	WO	32	0x0000 0000	0x0000 0014
EVENT0_IMEN	WO	32	0x0000 0000	0x0000 0018
EVENT0_IMDIS	WO	32	0x0000 0000	0x0000 001C
EVT_MODE	RW	32	0x0000 0001	0x0000 0020
DESC	RO	32	0x1511 0010	0x0000 0024
CLKCFG	RW	32	0x0000 0000	0x0000 1000

I2C Instances Register Mapping Summary

I2C Register Descriptions

:I2C Common Register Descriptions

:I2C:GFCTL

Address offset	0x0000 0100
Description	This register controls the glitch filter on the SCL and SDA lines
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3:0	GFSEL	Glitch suppression pulse width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks.		RW	0x0
		0x0	DIS Bypass
		0x1	CLK_1 1 clock
		0x2	CLK_2 2 clocks
		0x3	CLK_3 3 clocks
		0x4	CLK_4 4 clocks
		0x5	CLK_5 5 clocks
		0x6	CLK_6 6 clocks
		0x7	CLK_7 7 clocks
		0x8	CLK_8 8 clocks
		0x9	CLK_9 10 clocks
		0xA	CLK_A 12 clocks
		0xB	CLK_B 14 clocks
		0xC	CLK_C 16 clocks
		0xD	CLK_D 20 clocks
		0xE	CLK_E 24 clocks
		0xF	CLK_F 31 clocks

:I2C:CSA

Address offset	0x0000 0104
Description	Controller target address register
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15	CMODE	This field selects the addressing mode(7-field/10-field) to be used in controller mode		RW	0
		0	SEVEN_BIT 7-field addressing mode
		1	TEN_BIT 10-field addressing mode
14:11	RESERVED11	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
10:1	TADDR	I2C Target Address This field specifies bits A9 through A0 of the target address. In 7-field addressing mode as selected by MODE field, the top 3 bits are don't care		RW	0x000
		0x000	MINIMUM Smallest value
		0x3FF	MAXIMUM Highest possible value
0	DIR	This field specifies if the next controller operation is a Receive or Transmit		RW	0
		0	TRANSMIT The controller is in transmit mode.
		1	RECEIVE The controller is in receive mode.

:I2C:CCTR

Address offset	0x0000 0108
Description	This control register configures the I2C controller operation. The START field generates the START or REPEATED START condition. The STOP field determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the I2C Controller Target Address [CSA] register is written with the desired address, the RS field is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an byte transaction completed interrupt becomes active and the data may be read from the RXDATA register. When the I2C module operates in Controller receiver mode, a set ACK field causes the I2C bus controller to transmit an acknowledge automatically after each byte. This field must be cleared when the I2C bus controller requires no further data to be transmitted from the target transmitter.
Type	RW

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27:16	MBLEN	Transaction length This field contains the programmed length of bytes of the Transaction.		RW	0x000
		0x000	MINIMUM Smallest value
		0xFFF	MAXIMUM Highest possible value
15:6	RESERVED6	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
5	RDONTXEMPTY	Read on TXFIFO empty		RW	0
		0	DIS No special behaviour
		1	EN When 1 the controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the [CSA.DIR] is not set to read, then this field is ignored. The Start must be set in the [CCTR] for proper I2C protocol. The controller will first send the Start Condition, I2C Address with R/W field set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in [CCTR] and [CSA] without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around.
4	CACKOEN	Controller ACK overrride enable		RW	0
		0	DIS No special behavior
		1	EN When 1 and the controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the [CCTR] register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop.
3	ACK	Data Acknowledge Enable. Configure this field to send the ACK or NACK.		RW	0
		0	DIS_ACK The last received data byte of a transaction is not acknowledged automatically by the controller.
		1	EN_ACK The last received data byte of a transaction is acknowledged automatically by the controller.
2	STOP	Generate STOP		RW	0
		0	DIS_STOP The controller does not generate the STOP condition.
		1	EN_STOP The controller generates the STOP condition
1	START	Generate START		RW	0
		0	DIS_START The controller does not generate the START condition.
		1	EN_START The controller generates the START or repeated START condition
0	BURSTRUN	Controller enable and start transaction		RW	0
		0	DIS In standard mode, the controller will be unable to transmit or receive data.
		1	EN The controller will be able to transmit or receive data

:I2C:CSR

Address offset	0x0000 010C
Description	The status register indicates the state of the bus controller.
Type	RO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27:16	CBCNT	Controller Transaction Count This field contains the current count-down value of the transaction.		RO	0x000
		Read 0x000	MINIMUM Smallest value
		Read 0xFFF	MAXIMUM Highest possible value
15:7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
6	BUSBSY	Bus is busy Controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the [CCTR] register to start the transaction so that if SCL goes low it will trigger the BUSBSY.		RO	0
		Read 0	CLEAR The bus is idle.
		Read 1	SET This Status field is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE field is low. Note that the controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the [CCTR] register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
5	IDLE	I2C Idle		RO	1
		Read 0	CLEAR The controller is not idle.
		Read 1	SET The controller is idle.
4	ARBLST	Arbitration lost		RO	0
		Read 0	CLEAR The controller won arbitration.
		Read 1	SET The controller lost arbitration.
3	DATACK	Acknowledge data		RO	0
		Read 0	CLEAR The transmitted data was acknowledged
		Read 1	SET The transmitted data was not acknowledged.
2	ADRACK	Acknowledge address		RO	0
		Read 0	CLEAR The transmitted address was acknowledged
		Read 1	SET The transmitted address was not acknowledged.
1	ERR	Error The error can be from the target address not being acknowledged or the transmit data not being acknowledged.		RO	0
		Read 0	CLEAR No error was detected on the last operation.
		Read 1	SET An error occurred on the last operation.
0	BUSY	Controller FSM busy The field is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in [CCTR.MBLEN] including START, RESTART, Address and STOP signal generation when required for the current transaction.		RO	0
		Read 0	CLEAR The controller is idle.
		Read 1	SET The controller is busy.

:I2C:CTPR

Address offset	0x0000 0110
Description	This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode.
Type	RW

Bits	Field Name	Description		Type	Reset
31:7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
6:0	TPR	Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) x (SCL_LP + SCL_HP ) x INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). INT_CLK_PRD is the functional clock period in ns. Note: INT_CLK_PRD is based on divider value selected in [FCLKDIV:FCLK:DIV]		RW	0x01
		0x00	MINIMUM Smallest value
		0x7F	MAXIMUM Highest possible value

:I2C:CCR

Address offset	0x0000 0114
Description	Controller configuration register
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	RESERVED9	Reads to this field return zero.Writes to this field are ignored.		RO	0x00 0000
8	LPBK	I2C Loopback		RW	0
		0	DIS Normal operation.
		1	EN The controller in a test mode loopback configuration.
7:3	RESERVED3	Reads to this field return zero.Writes to this field are ignored.		RO	0x00
2	CLKSTRETCH	Clock Stretching. This field controls the support for clock stretching of the I2C bus.		RW	0
		0	DIS Disables the clock stretching detection. This can be disabled if no target on the bus does support clock streching, so that the maximum speed on the bus can be reached.
		1	EN Enables the clock stretching detection. Enabling the clock strechting ensures compliance to the I2C standard but could limit the speed due the clock stretching.
1	MCST	Multicontroller mode. In Multicontroller mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.		RW	0
		0	DIS Disable Multicontroller mode.
		1	EN Enable Multicontroller mode.
0	ACTIVE	Device Active After this field has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.		RW	0
		0	DIS Disables the I2C controller operation.
		1	EN Enables the I2C controller operation.

:I2C:CBMON

Address offset	0x0000 0118
Description	This register is used to determine the SCL and SDA signal status.
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	RESERVED3	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	SDA	SDA status		RO	1
		Read 0	CLEAR The SDA signal is low.
		Read 1	SET The SDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place.
0	SCL	SCL status		RO	1
		Read 0	CLEAR The SCL signal is low.
		Read 1	SET The SCL signal is high Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place.

:I2C:TOAR

Address offset	0x0000 011C
Description	This register consists of seven address bits that identify the I2C device on the I2C bus.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15	MODE	This field selects the addressing mode(7-field/10-field) to be used in target mode.		RW	0
		0	SEVEN_BIT Enable 7-field addressing
		1	TEN_BIT Enable 10-field addressing
14	OAREN	Target own address enable		RW	1
		0	DIS Disable OAR address
		1	EN Enable OAR address
13:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
9:0	OAR	Target own address: This field specifies bits A9 through A0 of the target address. In 7-field addressing mode as selected by [TOAR.MODE] field, the top 3 bits are don't care		RW	0x000
		0x000	MINIMUM Smallest value
		0x3FF	MAXIMUM Highest possible value

:I2C:TOAR2

Address offset	0x0000 0120
Description	This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus.
Type	RW

Bits	Field Name	Description		Type	Reset
31:23	RESERVED23	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
22:16	OAR2_MASK	Target own address 2 mask: This field specifies bits A6 through A0 of the target address. The bits with value '1' in this field will make the corresponding incoming address bits to match by default regardless of the value inside this field i.e. corresponding bits of this field are don't care.		RW	0x00
		0x00	MINIMUM Minimum Value
		0x7F	MAXIMUM Maximum Value
15:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
7	OAR2EN	Target own address 2 enable		RW	0
		0	DIS The alternate address is disabled.
		1	EN Enables the use of the alternate address in the OAR2 field.
6:0	OAR2	Target own address 2 This field specifies the alternate target own address.		RW	0x00
		0x00	MINIMUM Smallest value
		0x7F	MAXIMUM Highest possible value

:I2C:TCTR

Address offset	0x0000 0124
Description	Target control register
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	ENDEFDEVADR	Enable default device address		RW	0
		0	DIS When this field is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside TOAR/TOAR2.
		1	EN When this field is 1, default device address of 7'h110_0001 is always matched by the target address match logic.
8	ENALRESPADR	Enable alert response address		RW	0
		0	DIS The alert response address is not matched. NOTE: It may still be matched if programmed inside [TOAR]/[TOAR2]
		1	EN Alert response address of 7'h000_1100 is always matched by the target address match logic.
7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	RXFULLONRREQ	Rx full interrupt generated based on [TSR.RREQ] filed.		RW	0
		0	DIS [RIS.TRXFULL] will be set when only the Target RX FIFO is full. This allows the [RIS.TRXFULL] interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current RX byte.
		1	EN [RIS.SRXFULL] will be set when the target state machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte.
5	TXWAITSTALETXFIFO	Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with [TCTR:TXEMPTYONTREQ] set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.		RW	0
		0	DIS The TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty.
		1	EN The TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the target state machine leaves the [TSR.TXMODE] field. This can occur is a stop or timeout occur when there are bytes left in the TX FIFO.
4	TXTRIGXMODE	Tx trigger when target FSM is in TX mode		RW	0
		0	DIS No special behavior
		1	EN [RIS.TXFIFOTRG] will be set when the Target TX FIFO has reached the trigger level AND the target state machine is in the as defined in the [TSR.TXMODE] field. When cleared [RIS.TXFIFOTRG] will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time.
3	TXEMPTYONTREQ	Tx Empty Interrupt on TREQ		RW	0
		0	DIS [RIS.TTXEMPTY] will be set when only the target TX FIFO is empty. This allows the [RIS.TTXEMPTY] interrupt to be used to indicate that the bus is being clock stretched and that target TX data is required.
		1	EN [RIS.STXEMPTY] will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty and the transaction is clock stretched waiting for the FIFO to receive data.
2	CLKSTRETCH	Target clock stretch enable		RW	1
		0	DIS Target clock stretching is disabled
		1	EN Target clock stretching is enabled
1	GENCALL	General call response enable.		RW	0
		0	DIS Do not respond to a general call
		1	EN Respond to a general call
0	ACTIVE	Device active. Setting this field enables the target functionality.		RW	0
		0	DIS Disables the target operation.
		1	EN Enables the target operation.

:I2C:TSR

Address offset	0x0000 0128
Description	Target status register
Type	RO

Bits	Field Name	Description		Type	Reset
31:19	RESERVED19	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
18:9	ADDRMATCH	Indicates the address for which target address match happened		RO	0x000
		Read 0x000	MINIMUM Minimum Value
		Read 0x3FF	MAXIMUM Maximum Value
8	STALETXFIFO	Stale TX FIFO		RO	0
		Read 0	CLEAR Tx FIFO is not stale
		Read 1	SET The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous transaction.
7	TXMODE	Target FSM is in TX MODE		RO	0
		Read 0	CLEAR The target state machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
		Read 1	SET The target state machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
6	BUSBSY	Bus is busy		RO	0
		Read 0	CLEAR Bus is not busy
		Read 1	SET Bus is busy. This is cleared on a timeout.
5	RESERVED5	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
4	RESERVED4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
3	OAR2SEL	OAR2 address matched This field gets re-evaluated after every address comparison.		RO	0
		Read 0	CLEAR Either the OAR2 address is not matched or the match is in legacy mode.
		Read 1	SET OAR2 address matched and acknowledged by the target.
2	RXMODE	Target FSM is in RX MODE		RO	0
		Read 0	CLEAR The target state machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
		Read 1	SET The target state machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
1	TREQ	Transmit Request		RO	0
		Read 0	CLEAR No outstanding transmit request.
		Read 1	SET The controller has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the TXDATA FIFO (Target TX FIFO is empty).
0	RREQ	Receive Request		RO	0
		Read 0	CLEAR No outstanding receive data.
		Read 1	SET The controller has outstanding receive data and is using clock stretching to delay the controller until the data has been read from the RXDATA FIFO (target RX FIFO is full).

:I2C:RXDATA

Address offset	0x0000 012C
Description	RX FIFO read data byte This field contains the current byte being read in the RX FIFO stack. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
Type	RO

Bits	Field Name	Description		Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
7:0	VALUE	Received Data. This field contains the last received data.		RO	0x00
		Read 0x00	MINIMUM Smallest value
		Read 0xFF	MAXIMUM Highest possible value

:I2C:TXDATA

Address offset	0x0000 0130
Description	Transmit data register. This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
Type	RW

Bits	Field Name	Description		Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
7:0	VALUE	Transmit data This byte contains the data to be transferred during the next transaction.		RW	0x00
		0x00	MINIMUM Smallest value
		0xFF	MAXIMUM Highest possible value

:I2C:TACKCTL

Address offset	0x0000 0134
Description	This register enables the target to not acknowledge (NACK) for invalid data or command or acknowledge (ACK) for valid data or command. The I2C clock is pulled low after the last data field until this register is written.
Type	RW

Bits	Field Name	Description		Type	Reset
31:3	RESERVED3	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
2	ACKOENONSTART	When set this field will automatically turn on the target ACKOEN field following a start condition.		RW	0
		0	DIS No special behavior
		1	EN When set this field will automatically turn on the Target ACKOEN field following a start condition.
1	ACKOVAL	Target ACK override Value Note: For general call this field will be ignored if set to NACK and target continues to receive data.		RW	0
		0	DIS An ACK is sent indicating valid data or command.
		1	EN A NACK is sent indicating invalid data or command.
0	ACKOEN	Target ACK override enable		RW	0
		0	DIS A response in not provided.
		1	EN An ACK or NACK is sent according to the value written to the ACKOVAL field.

:I2C:FIFOCTL

Address offset	0x0000 0138
Description	Target FIFO control
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED16	Reads to this field return zero.Writes to this field are ignored.		RO	0x0000
15	RXFLUSH	RX FIFO flush Setting this field will flush the RX FIFO. Before resetting this field to stop flush the [FIFOSR.RXFIFOCNT] should be checked to be 0 and indicating that the flush has completed.		RW	0
		0	DIS Do not flush FIFO
		1	EN Flush FIFO
14:11	RESERVED11	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
10:8	RXTRIG	RX FIFO trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming this field to 0x0 has no effect since no data is present to transfer out of RX FIFO.		RW	0x0
		0x0	LEVEL_1 Trigger when RX FIFO contains >= 1 byte
		0x1	LEVEL_2 Trigger when RX FIFO contains >= 2 byte
		0x2	LEVEL_3 Trigger when RX FIFO contains >= 3 byte
		0x3	LEVEL_4 Trigger when RX FIFO contains >= 4 byte
		0x4	LEVEL_5 Trigger when RX FIFO contains >= 5 byte
		0x5	LEVEL_6 Trigger when RX FIFO contains >= 6 byte
		0x6	LEVEL_7 Trigger when RX FIFO contains >= 7 byte
		0x7	LEVEL_8 Trigger when RX FIFO contains >= 8 byte
7	TXFLUSH	TX FIFO flush Setting this field will flush the TX FIFO. Before resetting this field to stop flush the TXFIFOCNT should be checked to be 8 and indicating that the flush has completed.		RW	0
		0	DIS Do not flush FIFO
		1	EN flush FIFO
6:3	RESERVED3	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
2:0	TXTRIG	TX FIFO trigger Indicates at what fill level in the TX FIFO a trigger will be generated.		RW	0x0
		0x0	EMPTY Trigger when the TX FIFO is empty.
		0x1	LEVEL_1 Trigger when TX FIFO contains bigger or equal to 1 byte
		0x2	LEVEL_2 Trigger when TX FIFO contains bigger or equal to 2 byte
		0x3	LEVEL_3 Trigger when TX FIFO contains bigger or equal to 3 byte
		0x4	LEVEL_4 Trigger when TX FIFO contains bigger or equal to 4 byte
		0x5	LEVEL_5 Trigger when TX FIFO contains bigger or equal to 5 byte
		0x6	LEVEL_6 Trigger when TX FIFO contains bigger or equal to 6 byte
		0x7	LEVEL_7 Trigger when TX FIFO contains bigger or equal to 7 byte

:I2C:FIFOSR

Address offset	0x0000 013C
Description	FIFO status register Note: This register should only be read when BUSY is 0
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15	TXFLUSH	TX FIFO flush When this field is set a flush operation for the TX FIFO is active. Clear [FIFOCTL.TXFLUSH] to stop.		RO	0
		Read 0	CLEAR FIFO flush not active
		Read 1	SET FIFO flush active
14:12	RESERVED12	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
11:8	TXFIFOCNT	Number of bytes which could be put into the TX FIFO		RO	0x8
		Read 0x0	MINIMUM Smallest value
		Read 0x8	MAXIMUM Highest possible value
7	RXFLUSH	RX FIFO flush When this field is set a flush operation for the RX FIFO is active. Clear the [FIFOCTL.RXFLUSH] field to stop.		RO	0
		Read 0	CLEAR FIFO flush not active
		Read 1	SET FIFO flush active
6:4	RESERVED4	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
3:0	RXFIFOCNT	Number of bytes which could be read from the RX FIFO		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0x8	MAXIMUM Highest possible value

:I2C:FCLKDIV

Address offset	0x0000 0140
Description	Register for the selection of divider value to generate functional clock from SVT clock
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED4			RO	0x000 0000
3:0	FCLKDIV	Divider value selection		RW	0x0
		0x0	BY_1 Divide by 1 = 80MHz
		0x1	BY_2 Divide by 2 = 40MHz
		0x2	BY_4 Divide by 4 = 20MHz
		0x3	BY_5 Divide by 5 = 16MHz
		0x4	BY_8 Divide by 8 = 10MHz
		0x5	BY_10 Divide by 10 = 8MHz
		0x6	BY_16 Divide by 16 = 5MHz
		0x7	BY_20 Divide by 20 = 4MHz
		0x8	BY_25 Divide by 25 = 3.2MHz
		0x9	BY_32 Divide by 32 = 2.5MHz
		0xA	BY_40 Divide by 40 = 2MHz
		0xB	BY_80 Divide by 80 = 1MHz

:I2C:PDBGCTL

Address offset	0x0000 0000
Description	This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	SOFT	Soft halt boundary control. This function is only available, if FREE is set to 'STOP'		RW	1
		0	DIS The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
		1	EN The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0	FREE	Free run control		RW	1
		0	DIS The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
		1	EN The peripheral ignores the state of the Core Halted input

:I2C:EVENT0_IMASK

Address offset	0x0000 0004
Description	Interrupt Mask. If a field is set, then corresponding interrupt is masked. Un-masking the interrupt causes the raw interrupt to be visible in [RIS], as well as [MIS].
Type	RW

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	TARBLOST	Target arbitration lost		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrupt Mask
26	RX_OVFL_T	RX FIFO overflow in target mode		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrupt Mask
25	TX_UNFL_T	TX FIFO underflow in target mode		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrupt Mask
24	TGENCALL	General call interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
23	TSTOP	Stop condition interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the Transmit FIFO in target mode have been shifted out and the transmit goes into idle mode.		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
20	RXFIFOFULLT	RX FIFO full event. This interrupt is set if an target RX FIFO is full in target mode.		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
19	TXFIFOTRGT	TX FIFO trigger in target mode		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
18	RXFIFOTRGMT	RX FIFO trigger in target mode		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
17	TTXDONE	Target transmit transaction completed interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
16	TRXDONE	Target receive data interrupt. Signals that a byte has been received		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
15:10	RESERVED11	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
8	CSTOP	STOP detection interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
7	CSTART	START detection interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
6	CNACK	Address/Data NACK interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
5	TXEMPTYC	TXFIFO empty interrupt in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
4	RXFIFOFULLC	RXFIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
3	TXFIFOTRGC	Transmit FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
2	RXFIFOTRGC	Receive FIFO trigger in controller code Trigger when RX FIFO contains >= defined bytes		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
1	CTXDONE	Controller transmit transaction completed Interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask
0	CRXDONE	Controller receive transaction completed Interrupt		RW	0
		0	DIS Clear Interrupt Mask
		1	EN Set Interrrupt Mask

:I2C:EVENT0_RIS

Address offset	0x0000 0008
Description	Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the [ICLR] register field even if the corresponding [IMASK] field is not enabled.
Type	RO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	TARBLOST	Target arbitration lost		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
26	RX_OVFL_T	RX FIFO overflow in target mode		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt Occured
25	TX_UNFL_T	TX FIFO underflow in target mode		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
24	TGENCALL	General call interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
23	TSTOP	Stop condition interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
22	TSTART	Target start condition interrupt.When the received address matches the target address, this interrupt asserted.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
20	RXFIFOFULLT	RX FIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
19	TXFIFOTRGT	TX FIFO trigger in target mode		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
18	RXFIFOTRGT	RX FIFO trigger in target mode		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
17	TTXDONE	Target transmit transaction completed interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
16	TRXDONE	Target receive data interrupt. Signals that a byte has been received		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
8	CSTOP	STOP detection interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
7	CSTART	START detection interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
6	CNACK	Address/Data NACK interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
5	TXEMPTYC	TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
4	RXFIFOFULLC	RX FIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
3	TXFIFOTRGC	TX FIFO Trigger in Transmit Mode Trigger when TX FIFO contains <= defined bytes		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
1	CTXDONE	Controller transmit transaction completed interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured
0	CRXDONE	Controller receive transaction completed interrupt		RO	0
		Read 0	CLR Interrupt did not occur
		Read 1	SET Interrupt occured

:I2C:EVENT0_MIS

Address offset	0x0000 000C
Description	Masked interrupt status. This is an AND of the [IMASK] and [RIS] registers.
Type	RO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	TARBLOST	Target arbitration lost		RO	0
		Read 0	CLR Clear interrupt mask
		Read 1	SET Masked interrupt occured
26	TRX_OVFL	RX FIFO overflow in target mode		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
25	TTX_UNFL	TX FIFO underflow in target mode		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
24	TGENCALL	General call interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
23	TSTOP	Target STOP detection interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
20	RXFIFOFULLT	RXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in target mode.		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
19	TXFIFOTRGT	TX FIFO trigger in target mode		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
18	RXFIFOTRGT	Target RX FIFO trigger		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
17	TTXDONE	Target transmit transaction completed interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
16	TRXDONE	Target receive data interrupt. Signals that a byte has been received		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
8	CSTOP	STOP detection interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
7	CSTART	START detection interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
6	CNACK	Address/Data NACK interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
5	TXEMPTYC	TX FIFO Empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
4	RXFIFOFULLC	RX FIFO full event. This interrupt is set if the RX FIFO is full in controller mode.		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
3	TXFIFOTRGC	TX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
1	CTXDONE	Controller transmit transaction completed interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured
0	CRXDONE	Controller receive data interrupt		RO	0
		Read 0	CLR Masked Interrupt did not occur
		Read 1	SET Masked interrupt occured

:I2C:EVENT0_IEN

Address offset	0x0000 0010
Description	Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a field in IEN will set the event and therefore the related RIS field also gets set. If the interrupt is enabled through the mask, then the corresponding MIS field is also set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0
27	TARBLOST	Target arbitration lost		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrupt
26	RX_OVFL_T	RX FIFO overflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
25	TX_UNFL_T	TX FIFO underflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set interrupt
24	TGENCALL	General call interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
23	TSTOP	Stop condition interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
20	RXFIFOFULLT	RXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in Target mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
19	TXFIFOTRGT	TX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
18	RXFIFOTRGT	RX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
17	TTXDONE	Target transmit transaction completed Interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
16	TRXDONE	Target receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
8	CSTOP	STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
7	CSTART	START detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
6	CNACK	Address/Data NACK interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
5	TXEMPTYC	TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
4	RXFIFOFULLC	RXFIFO full event in controller mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
3	TXFIFOTRGC	TX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
1	CTXDONE	Controller transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt
0	CRXDONE	Controller receive data interrupt Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set Interrrupt

:I2C:EVENT0_IDIS

Address offset	0x0000 0014
Description	Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	WO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	TARBLOST	Target arbitration lost		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
26	RX_OVFL_T	RX FIFO overflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
25	TX_UNFL_T	TX FIFO underflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
24	TGENCALL	General call interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
23	TSTOP	Target STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
20	RXFIFOFULLT	RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
19	TXFIFOTRGT	TX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
18	RXFIFOTRGT	RX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
17	TTXDONE	Target transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
16	TRXDONE	Target receive data interrupt Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
8	CSTOP	STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
7	CSTART	START detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
6	CNACK	Address/Data NACK interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
5	TXEMPTYC	TX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
4	RXFIFOFULLC	RXFIFO full event in controller mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
3	TXFIFOTRGC	TX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
1	CTXDONE	Controller transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt
0	CRXDONE	Controller receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear Interrupt

:I2C:EVENT0_IMEN

Address offset	0x0000 0018
Description	Interrupt mask set. Writing a 1 to a field in IMEN will set the related IMASK field.
Type	WO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0
27	TARBLOST	Target srbitration lost		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
26	RX_OVFL_T	RX FIFO overflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
25	TX_UNFL_T	TX FIFO underflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
24	TGENCALL	General call interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
23	TSTOP	Stop condition interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
21	TXEMPTYT	TX FIFO Empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
20	RXFIFOFULLT	RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
19	TXFIFOTRGST	TX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
18	RXFIFOTRGT	RX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
17	TTXDONE	Target transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
16	SRXDONE	Target receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
8	CSTOP	STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
7	CSTART	START detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
6	CNACK	Address/Data NACK interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
5	TXEMPTYC	TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
4	RXFIFOFULLC	RXFIFO full event in controller mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
3	TXFIFOTRGC	TX FIFO trigger in Controller mode Trigger when TX FIFO contains <= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
1	CTXDONE	Controller transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt
0	CRXDONE	Controller receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Set masked interrrupt

:I2C:EVENT0_IMDIS

Address offset	0x0000 001C
Description	Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type	WO

Bits	Field Name	Description		Type	Reset
31:28	RESERVED28	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
27	TARBLOST	Target arbitration lost		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
26	RX_OVFL_T	RX FIFO overflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
25	TX_UNFL_T	TX FIFO underflow in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
24	TGENCALL	General call interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
23	TSTOP	Target STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
22	TSTART	Target start condition interrupt. Asserted when the received address matches the target address.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
21	TXEMPTYT	TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
20	RXFIFOFULLT	RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
19	TXFIFOTRGT	TX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
18	RXFIFOTRGT	RX FIFO trigger in target mode		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
17	TTXDONE	Target transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
16	TRXDONE	Target receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
15:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
9	CARBLOST	Arbitration lost interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
8	CSTOP	STOP detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
7	CSTART	START detection interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
6	CNACK	Address/Data NACK interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
5	TXEMPTYC	TX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
4	RXFIFOFULLC	RX FIFO full event in controller mode.		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
3	TXFIFOTRGC	TX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
2	RXFIFOTRGC	RX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
1	CTXDONE	Controller transmit transaction completed interrupt		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt
0	CRXDONE	Controller receive data interrupt. Signals that a byte has been received		WO	0
		Write 0	DIS Writing 0 has no effect
		Write 1	EN Clear masked interrupt

:I2C:EVT_MODE

Address offset	0x0000 0020
Description	Event mode register. It is used to select whether each line is disabled, in software mode (software clears the [RIS]) or in hardware mode (hardware clears the [RIS])
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RESERVED2			RO	0x0000 0000
1:0	INT0_CFG	Event line mode select for event corresponding to [INT_EVENT0]		RO	0x1
		Read 0x0	DIS The interrupt or event line is disabled.
		Read 0x1	SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
		Read 0x2	HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

:I2C:DESC

Address offset	0x0000 0024
Description	This register identifies the peripheral and its exact version.
Type	RO

Bits	Field Name	Description		Type	Reset
31:16	MODULEID	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.		RO	0x1511
		Read 0x0000	MINIMUM Smallest value
		Read 0xFFFF	MAXIMUM Highest possible value
15:12	FEATUREVER	Feature Set for the module instance		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
11:8	INSTNUM	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
7:4	MAJREV	Major rev of the IP		RO	0x1
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value
3:0	MINREV	Minor rev of the IP		RO	0x0
		Read 0x0	MINIMUM Smallest value
		Read 0xF	MAXIMUM Highest possible value

:I2C:CLKCFG

Address offset	0x0000 1000
Description	This register controls the bus clock to I2C
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	RESERVED1	Reads to this field return zero.Writes to this field are ignored.		RO	0x0000 0000
0	ENABLE	This field enables or disables the bus clock to I2C		RW	0
		0	DIS I2C clock disabled
		1	EN I2C clock disabled