31:5

RESERVED5

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4

POLARITY_CONTROL_4

Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.

RW

0

3

POLARITY_CONTROL_3

Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.

RW

0

2

POLARITY_CONTROL_2

Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.

RW

0

1

POLARITY_CONTROL_1

Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.

RW

0

0

POLARITY_CONTROL_0

Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.

RW

0

31:5

RESERVED5

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4

TYPE_CONTROL_4

Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).

RW

0

3

TYPE_CONTROL_3

Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).

RW

0

2

TYPE_CONTROL_2

Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).

RW

0

1

TYPE_CONTROL_1

Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).

RW

0

0

TYPE_CONTROL_0

Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).

RW

0

31:5

RESERVED5

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4:0

ENABLE_CONTROL

Individual enable control bits per interrupt input: 0b = Disabled. 1b = Enabled

RW

0x00

31:5

RESERVED5

Reserved field. Write with zero

RO

0x000 0000

4:0

ENABLE_SET

Individual interrupt enable bits per interrupt input: 0b = No effect. 1b = Set the corresponding bit in the AICENCTL register, enabling the interrupt. After writing a 1b, there is no need to write a 0b.

WO

0x00

31:5

RESERVED5

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4

RAW_STATUS_4

Individual interrupt status bit before masking with enable_ctrl_r[4] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.

RO

0

3

RAW_STATUS_3

Individual interrupt status bit before masking with enable_ctrl_r[3] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.

RO

1

2

RAW_STATUS_2

Individual interrupt status bit before masking with enable_ctrl_r[2] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.

RO

1

1

RAW_STATUS_1

Individual interrupt status bit before masking with enable_ctrl_r[1] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.

RO

1

0

RAW_STATUS_0

Individual interrupt status bit before masking with enable_ctrl_r[0] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.

RO

1

31:5

RESERVED5

Reserved field. Write with zero

RO

0x000 0000

4

ACK_4

Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [4] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.

RW

0

3

ACK_3

Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [3] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.

RW

0

2

ACK_2

Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [2] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.

RW

0

1

ACK_1

Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [1] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.

RW

0

0

ACK_0

Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [0] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.

RW

0

31:5

RESERVED_0

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4:0

ENABLED_STATUS

These bits reflect the status of the interrupts after polarity control and optional edge detection, gated with bits in AICENCTL register: 0b = Inactive. 1b = Pending.

RO

0x00

31:5

RESERVED5

Reserved field. Write with zero

RO

0bxxx xxxx xxxx xxxx xxxx xxxx xxxx

4:0

ENABLE_CLR

Individual interrupt disable bits per interrupt input: 0b = No effect. 1b = Clear the corresponding bit in the AICENCTL register, disabling the interrupt. After writing a 1b, there is no need to write a 0b.

WO

0bx xxxx

31:9

RESERVED9

Reserved field. Write with zero and ignore on read

RO

0bxxx xxxx xxxx xxxx xxxx xxxx

8

MINI_REG_MAP

Mini register map.

RO

0

7

EXT_REG_MAP

Extended register map.

RO

0

6

RESERVED6

Reserved field. Write with zero and ignore on read

RO

X

5:0

NR_OF_INPUTS

The number of interrupt request inputs.

RO

0x05

31:28

RESERVED28

Reserved field. Write with zero and ignore on read

RO

0xX

27:24

MAJOR_VERSION

These bits encode the major version number for the EIP-201 module.

RO

0x1

23:20

MINOR_VERSION

These bits encode the minor version number for the EIP-201 module.

RO

0x4

19:16

PATCH_LEVEL

These bits encode the hardware patch level for the EIP-201 module, starting at value 0 on the first release.

RO

0x0

15:8

EIP_NUMBER_COMPL

These bits simply contain the complement of bits [7:0], used by a driver to ascertain that this version register is indeed read.

RO

0x36

7:0

EIP_NUMBER

These bits encode the Rambus EIP number.

RO

0xC9

31:8

RESERVED8

Reserved field. Write with zero

RO

0x00 0000

7

MBX2_UNLINK

Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MBXSTA

WO

0

6

MBX2_LINK

Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host

WO

0

5

MBX2_OUT_EMPTY

Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MBXSTA by writing 1b here.

WO

0

4

MBX2_IN_FULL

Set only - The Host linked to mailbox can set the mbx_in_full bit in MBXSTA by writing 1b here.

WO

0

3

MBX1_UNLINK

Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MBXSTA

WO

0

2

MBX1_LINK

Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host

WO

0

1

MBX1_OUT_EMPTY

Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MBXSTA by writing 1b here.

WO

0

0

MBX1_IN_FULL

Set only - The Host linked to mailbox can set the mbx_in_full bit in MBXSTA by writing 1b here.

WO

0

31:8

RESERVED8

Reserved field. Write with zero and ignore on read

RO

0xXX XXXX

7

MBX2_AVAILABLE

(set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host

RO

1

6

MBX2_LINKED

(set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox

RO

0

5

MBX2_OUT_FULL

(set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty

RO

0

4

MBX2_IN_FULL

(set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token

RO

0

3

MBX1_AVAILABLE

(set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host

RO

1

2

MBX1_LINKED

(set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox

RO

0

1

MBX1_OUT_FULL

(set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty

RO

0

0

MBX1_IN_FULL

(set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token

RO

0

31:8

RESERVED8

Reserved field. Write with zero

RO

0x00 0000

7

MBX2_UNLINK

Set only - Master Host can unlink mbx from it's current Host by writing 1b here.

WO

0

6

RESERVED6

Reserved field. Write with zero

RO

0

5

MBX2_OUT_EMPTY

Set only - Master Host can clear mbx_out_full bit in MBXSTA by writing 1b here.

WO

0

4

RESERVED4

Reserved field. Write with zero

RO

0

3

MBX1_UNLINK

Set only - Master Host can unlink mbx from it's current Host by writing 1b here.

WO

0

2

RESERVED2

Reserved field. Write with zero

RO

0

1

MBX1_OUT_EMPTY

Set only - Master Host can clear mbx_out_full bit in MBXSTA by writing 1b here.

WO

0

0

RESERVED0

Reserved field. Write with zero

RO

0

31:7

RESERVED_1

Reserved field. Write with zero and ignore on read

RO

0bx xxxx xxxx xxxx xxxx xxxx xxxx

6

MBX2_LINKED

(set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d

RO

0

5

MBX2_OUT_FULL

(set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty

RO

0

4

MBX2_IN_FULL

(set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token

RO

0

3

RESERVED_0

Reserved field. Write with zero and ignore on read

RO

X

2

MBX1_LINKED

(set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d

RO

0

1

MBX1_OUT_FULL

(set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty

RO

0

0

MBX1_IN_FULL

(set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token

RO

0

31:8

RESERVED8

Reserved field. Write with zero and ignore on read

RO

0xXX XXXX

7

MBX2_PROT_ACC

0: Mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Mailbox 2 is only accessible if the Host uses protected access.

RO

0

6:4

MBX2_LINK_ID

Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access

RO

0x0

3

MBX1_PROT_ACC

0: Mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Mailbox 1 is only accessible if the Host uses protected access.

RO

0

2:0

MBX1_LINK_ID

Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access

RO

0x0

31:8

RESERVED8

Reserved field. Write with zero and ignore on read

RO

0xXX XXXX

7

MBX2_PROT_ACC

0: Output mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 2 is only accessible if the Host uses protected access.

RO

0

6:4

MBX2_OUT_ID

Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access

RO

0x0

3

MBX1_PROT_ACC

0: Output mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 1 is only accessible if the Host uses protected access.

RO

0

2:0

MBX1_OUT_ID

Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access

RO

0x0

31:16

RESERVED16

Reserved field. Write with zero and ignore on read

RO

0xXXXX

15:8

MBX2_LOCKOUT

Bit map indicates which Hosts are blocked from accessing mailbox

RW

0x0E

7:0

MBX1_LOCKOUT

Bit map indicates which Hosts are blocked from accessing mailbox

RW

0x0E

31

FATAL_ERROR

Read-Only. Set if fatal error occured

RO

0

30:11

RESERVED11

Reserved field. Write with zero and ignore on read

RO

0xX XXXX

10

CRC24_ERROR

Read-Only. Set if CRC on ProgramROM is fails

RO

0

9

CRC24_OK

Read-Only. Set if CRC on ProgramROM is passes

RO

X

8

CRC24_BUSY

Read-Only. Set if CRC on ProgramROM is busy

RO

X

7:2

RESERVED2

Reserved field. Write with zero and ignore on read

RO

0bxx xxxx

1

NONFIPS_MODE

Read-Only. Set if VaultIP is in non-FIPS mode

RO

0

0

FIPS_MODE

Read-Only. Set if VaultIP is in FIPS mode

RO

0

31:26

RESERVED26

Reserved field. Write with zero and ignore on read

RO

0bxx xxxx

25

ADD_CE10

Set - an additional crypto engine is available in hardware as custom engine10

RO

0

24

ADD_CE9

Set - an additional crypto engine is available in hardware as custom engine9

RO

0

23

ADD_CE8

Set - an additional crypto engine is available in hardware as custom engine8

RO

0

22

ADD_CE7

Set - an additional crypto engine is available in hardware as custom engine7

RO

0

21

ADD_CE6

Set - an additional crypto engine is available in hardware as custom engine6

RO

1

20

ADD_CE5

Set - an additional crypto engine is available in hardware as custom engine5

RO

0

19

ADD_CE4

Set - an additional crypto engine is available in hardware as custom engine4

RO

0

18

ADD_CE3

Set - an additional crypto engine is available in hardware as custom engine3

RO

0

17

ADD_CE2

Set - an additional crypto engine is available in hardware as custom engine2

RO

0

16

ADD_CE1

Set - an additional crypto engine is available in hardware as custom engine1

RO

0

15:13

RESERVED13

Reserved field. Write with zero and ignore on read

RO

0bxxx

12

BUS_IFC

Bus interface type, for both Master and Slave: 0b = 32-bit AHB, 1b = 32-bit AXI

RO

0

11:10

RESERVED10

Reserved field. Write with zero and ignore on read

RO

0bxx

9

PROGRAMRAM

1b = downloadable RAM based firmware program memory. 0b = ROM only firmware program memory.

RO

0

8

C_CPU

C capable local cpu available

RO

0

7:6

RESERVED6

Reserved field. Write with zero and ignore on read

RO

0bxx

5

PKCP

PKCP Engine available

RO

1

4

CRC

CRC calculation available

RO

1

3

TRNG

Set - TRNG engine available

RO

1

2

SHA

Set - SHA1/SHA2 combination core available

RO

1

1

RESERVED1

Reserved field. Write with zero and ignore on read

RO

X

0

DES_AES

Set - (3)DES/AES combination crypto core available

RO

0

31:24

HOST_ID_SEC

Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active Hosts with secure access

RO

0x01

23

MY_ID_SEC

Indicates the current protection bit values of the Host actually reading the register

RO

1

22:20

MY_ID

Slave & Master interface support protection bit (secure/non-secure) accesses

RO

0x0

19

RESERVED19

Reserved field. Write with zero and ignore on read

RO

X

18:16

MASTER_ID

Value of the cpu_id that designates the Master Host

RO

0x0

15:8

HOST_ID

Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active

RO

0x0F

7:6

RESERVED6

Reserved field. Write with zero and ignore on read

RO

0bxx

5:4

MAILBOX_SIZE

Implemented size of Mailbox pairs - 00b-128bytes, 01b-256bytes, 10b-512bytes, 11b-1Kbyte

RO

0x1

3:0

NR_OF_MAILBOXES

Number of Input/Output Mailbox pairs

RO

0x2

31:28

RESERVED28

Reserved field. Write with zero and ignore on read

RO

0xX

27:24

MAJOR_VERSION

Major Version release number for this module

RO

0x4

23:20

MINOR_VERSION

Minor Version release number for this module

RO

0x0

19:16

PATCH_LEVEL

Hardware Patch Level for this module

RO

0x0

15:8

EIP_NUMBER_COMPL

Bit by Bit compliment of EIP Number

RO

0x7D

7:0

EIP_NUMBER

RAMBUS EIP number - EIP130

RO

0x82