31:0

WORD

WORD
write opt
IC to NAB write word

WO

0x0000 0000

31:0

WORD

WORD
read clear
NAB to IC read word

RO

0xEEEE EEEE

31:2

Reserved

RO

0x0000 0000

1:0

MEM_MOD_CFG

CONFIG
"00" - Direct Access WR
"01" - DMA WR
"10" - Direct Access RD
"11" - DMA RD

RW

0x0

31:22

Reserved

RO

0x000

21

FULL

FULL

RO

0

20

EMP

EMPTY

RO

1

19:13

Reserved

RO

0x00

12:8

WRPTR

WRITE POINTER

RO

0x00

7:5

Reserved

RO

0x0

4:0

RDPTR

READ POINTER

RO

0x00

31:1

Reserved

RO

0x0000 0000

0

UNDER_RDCL

STATUS
read clear
FIFO Underflow - RD when FIFO is empty.

RO

0

31:1

Reserved

RO

0x0000 0000

0

OVER_RDCL

STATUS
read clear
FIFO Overflow - WR when FIFO is full.

RO

0

31:1

Reserved

RO

0x0000 0000

0

FIFO

FIFO
write clear
Setting this bit clears the FIFO Controls.

WO

0

31:19

Reserved

RO

0x0000

18:16

RDNAB

READ NAB

RO

0x0

15:11

Reserved

RO

0x00

10:8

WRNAB

WRITE NAB

RO

0x0

7:3

Reserved

RO

0x00

2:0

HANDLER

HANDLER
IDLE = 3'b000
DMA_BL_WR = 3'b101
DMA_HOLD_WR = 3'b110
DIRECT_ACCESS_WR = 3'b111
NAB_WR = 3'b001
DMA_BL_RD = 3'b010
DIRECT_ACCESS_RD = 3'b011 ;

RO

0x0

31:29

Reserved

RO

0x0

28:24

SZOCC

SIZE OCCUPIED
indication of how many words have been written to FIFO
0 - nothing was written
1 - 1 word have been written
...
16 - 16 words have been written

RO

0x00

23:21

Reserved

RO

0x0

20:16

SZAVAIL

SIZE AVAILABLE
indication of free space left at FIFO
0 - FIFO full
1 - 1 word can be written
...
16 - 16 words can be written

RO

0x10

15:10

Reserved

RO

0x00

9

RDTHRHIT

READ THRESHOLD HIT
indication if the read threshold hit

RO

0

8

WRTHRNTHIT

WRITE THRESHOLD NOT HIT
indication if the write threshold not hit

RO

1

7:4

Reserved

RO

0x0

3:0

MEM_FIFOTH

THRESHOLD
Sets the HIF threshold:
for TX (DMA to NAB)-
0 - if there is room for 1 word the req to DMA will be send
...
15 - if there is room for 16 words the req to DMA will be send
for RX (NAB to DMA)-
0 - if FIFO is occupied by at lest 1 word, the req to DMA will be send
...
15 - if FIFO is occupied by at lest 16 word, the req to DMA will be send

RW

0xF

31:6

Reserved

RO

0x000 0000

5:0

RIS

RIS
read clear
bit[0] - empty
bit[1] - full
bit[2] - underflow
bit[3] - overflow
bit[4] - not empty with direct access read
bit[5] - nab data receive done

RO

0x01

31:12

Reserved

RO

0x0 0000

11:6

STA

STATUS
bit[0] - empty
bit[1] - full
bit[2] - underflow
bit[3] - overflow
bit[4] - not empty with direct access read
bit[5] - nab data receive done

RO

0x00

5:0

EVTBM

EVENT BIT MASK
'1' - Mask
'0' - Do Not Mask
bit[0] - empty
bit[1] - full
bit[2] - underflow
bit[3] - overflow
bit[4] - not empty with direct access read
bit[5] - nab data receive done

RW

0x3F

31:4

Reserved

RO

0x000 0000

3

FIFONEMPT

NAB HOST FIFO NOT EMPTY
indication when NAB FIFO not empty

RO

0

2

RCVDONEM2MIDL

RECEIVE DONE AND M2M IDLE
indication when NAB data recieve done and M2M FSM IDLE

RO

0

1

RCVDONE

RECEIVE DONE
indication when NAB data recieve done

RO

0

0

NABRDY_TO_RCV

TO RECEIVE
indication when NAB is ready to receive data

RO

0

31:0

TMSTMP

TIMESTAMP

RO

0x0000 0000

31:0

STA

STATUS
read clear
This is not a regular clear-on-read register.
A fresh status value from Rx sub system is being latch upon reading the register.
The objective is for the device to have the last value the host has read

RO

0x0000 0000

31:0

RXSTALAT

VALUE
Reflects the Rx status word current value (dynamic Read).
and automatically latch the value in RXSTALAT_LATCHED.
Usage: SDIO Wrapper reads this location and send the read value toward the host.
For bit field description refer to RXSTALAT.
This register is valid only in BSD_BYPASS=1 (Osprey).

RO

0x0000 0000

31:0

BMVAL

BIT MASK VALUE
Host interrupt status read register. non-intrusive read. Post mask (masked).

RO

0x0000 0000

31:0

BMVAL

BIT MASK VALUE
Read mask bitmap.
Mask bit legend:
'0' - do not mask the interrupt.
'1' - Mask the related interrupt.

RO

0x0000 0000

31:0

BMVAL_SET_WRCL

VALUE
write clear
Host interrupt mask register set
Writing to this register will set to '1' the related interrupt mask bit.
Mask bit legend:
'0' - do not mask the interrupt.
'1' - Mask the related interrupt.

WO

0x0000 0000

31:0

BMVAL_CLR_WRCL

VALUE
write clear
Host interrupt mask register clear
Writing to this register will clear the related interrupt mask bit.
Mask bit legend:
'0' - do not mask the interrupt.
'1' - Mask the related interrupt.

WO

0x0000 0000

31:0

STA

STATUS
read clear
Host interrupt status clear-on-read register
Clears all bits of upon read.
Usage: host reads the IRQ register which is automatically getting cleared by H/W
Osprey Note: The endianness correction and word-size correction are done in SDIO(WSPI) H/W.

RO

0x0000 0000

31:0

SET

SET
write clear register
Host interrupt set register

WO

0x0000 0000

31:0

SET

SET
write clear register
Host interrupt clear register

WO

0x0000 0000