GPTIMER

This section provides information on the GPTIMER Module Instance within this product. Each of the registers within the Module Instance is described separately below.

This component is a general purpose timer. The timer offers - generation of waveforms and events. - capture of signal period and duty cycle. - generation of **IR** signals. - decoding of quadrature encoded signals. - motor control features. It consists of a - 16-bit counter. - 8-bit prescaler - 3 capture compare channels. - 3 event outputs. - 3 capture inputs. Each channel subscribes to the synchronous event bus. They can control one or more event outputs in both capture and compare modes. [PRECFG.TICKSRC] selects tick source for the timer. INTERNAL_NOTE: [Functional Spec] https://confluence.itg.ti.com/display/LPRF/Implementation+Specification [Simple Block Diagram] https://confluence.itg.ti.com/display/LPRF/Implementation+Specification#ImplementationSpecification-_Toc2959138BlockDiagram

GPTIMER Registers Mapping Summary

:GPTIMER Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DESC	RO	32	0xDE49 1010	0x0000 0000
DESCEX	RO	32	0x000E 38E4	0x0000 0004
STARTCFG	RW	32	0x0000 0000	0x0000 0008
CTL	RW	32	0x0000 0000	0x0000 000C
OUTCTL	RW	32	0x0000 0000	0x0000 0010
CNTR	RW	32	0x0000 0000	0x0000 0014
PRECFG	RW	32	0x0000 0000	0x0000 0018
PREEVENT	RW	32	0x0000 0000	0x0000 001C
CHFILT	RW	32	0x0000 0000	0x0000 0020
FAULT	RW	32	0x0000 0000	0x0000 0024
PARK	RW	32	0x0000 0000	0x0000 0028
DBDLY	RW	32	0x0000 0000	0x0000 002C
DBCTL	RW	32	0x0000 0000	0x0000 0030
QDECSTAT	RO	32	0x0000 0000	0x0000 0034
IRGEN	RW	32	0x0000 0000	0x0000 0038
DMA	RW	32	0x0000 0000	0x0000 003C
DMARW	RW	32	0x0000 0000	0x0000 0040
ADCTRG	RW	32	0x0000 0000	0x0000 0044
IOCTL	RW	32	0x0000 0000	0x0000 0048
IMASK	RW	32	0x0000 0000	0x0000 0068
RIS	RO	32	0x0000 0000	0x0000 006C
MIS	RO	32	0x0000 0000	0x0000 0070
ISET	WO	32	0x0000 0000	0x0000 0074
ICLR	WO	32	0x0000 0000	0x0000 0078
IMSET	WO	32	0x0000 0000	0x0000 007C
IMCLR	WO	32	0x0000 0000	0x0000 0080
EMU	RW	32	0x0000 0000	0x0000 0084
C0CFG	RW	32	0x0000 0000	0x0000 00C0
C1CFG	RW	32	0x0000 0000	0x0000 00C4
C2CFG	RW	32	0x0000 0000	0x0000 00C8
C3CFG	RW	32	0x0000 0000	0x0000 00CC
PTGT	RW	32	0x0000 0000	0x0000 00FC
PC0CC	RW	32	0x0000 0000	0x0000 0100
PC1CC	RW	32	0x0000 0000	0x0000 0104
PC2CC	RW	32	0x0000 0000	0x0000 0108
PC3CC	RW	32	0x0000 0000	0x0000 010C
TGT	RW	32	0xFFFF FFFF	0x0000 013C
C0CC	RW	32	0x0000 0000	0x0000 0140
C1CC	RW	32	0x0000 0000	0x0000 0144
C2CC	RW	32	0x0000 0000	0x0000 0148
C3CC	RW	32	0x0000 0000	0x0000 014C
PTGTNC	RW	32	0x0000 0000	0x0000 017C
PC0CCNC	RW	32	0x0000 0000	0x0000 0180
PC1CCNC	RW	32	0x0000 0000	0x0000 0184
PC2CCNC	RW	32	0x0000 0000	0x0000 0188
PC3CCNC	RW	32	0x0000 0000	0x0000 018C
TGTNC	RW	32	0xFFFF FFFF	0x0000 01BC
C0CCNC	RW	32	0x0000 0000	0x0000 01C0
C1CCNC	RW	32	0x0000 0000	0x0000 01C4
C2CCNC	RW	32	0x0000 0000	0x0000 01C8
C3CCNC	RW	32	0x0000 0000	0x0000 01CC
CLKCFG	RW	32	0x0000 0000	0x0000 1000

GPTIMER Instances Register Mapping Summary

GPTIMER Register Descriptions

:GPTIMER Common Register Descriptions

:GPTIMER:DESC

Address offset	0x0000 0000
Description	Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	MODID	Module identifier used to uniquely identify this IP.	RO	0xDE49
15:12	STDIPOFF	Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)	RO	0x1
11:8	INSTIDX	IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number.	RO	0x0
7:4	MAJREV	Major revision of IP.	RO	0x1
3:0	MINREV	Minor revision of IP.	RO	0x0

:GPTIMER:DESCEX

Address offset	0x0000 0004
Description	Description Extended This register describes the parameters of the LGPT.
Type	RO

Bits	Field Name	Description		Type	Reset
31:20	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
19	HIR	Has IR logic.		RO	1
18	HDBF	Has Dead-Band, Fault, and Park logic.		RO	1
17:14	PREW	Prescaler width. The prescaler can maximum be configured to 2^[PREW]-1.		RO	0x8
13	HQDEC	Has Quadrature Decoder.		RO	1
12	HCIF	Has channel input filter.		RO	1
11:8	CIFS	Channel input filter size. The prevailing state filter can maximum be configured to 2^[CIFS]-1.		RO	0x8
7	HDMA	Has uDMA output and logic.		RO	1
6	HINT	Has interrupt output and logic.		RO	1
5:4	CNTRW	Counter bit-width. The maximum counter value is equal to 2^[CNTRW]-1.		RO	0x2
		Read 0x0	CNTR16 16-bit counter.
		Read 0x1	CNTR24 24-bit counter.
		Read 0x2	CNTR32 32-bit counter.
		Read 0x3	RESERVED RESERVED
3:0	NCH	Number of channels.		RO	0x4

:GPTIMER:STARTCFG

Address offset	0x0000 0008
Description	Start Configuration This register is only for when [CTL.MODE] is configured to one of the SYNC modes. This register defines when this LGPT starts.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1:0	LGPT0	LGPT start		RW	0x0
		0x0	EV_SYNC LGPT starts when synchronized event input is high. Configured here [EVTSVT:LGPTSYNCSEL].

:GPTIMER:CTL

Address offset	0x0000 000C
Description	Timer Control
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	C3RST	Channel 3 reset.		WO	0
		Write 0	NOEFF No effect.
		Write 1	RST Reset [C3CC.], [PC3CC.], and [C3CFG.*].
10	C2RST	Channel 2 reset.		WO	0
		Write 0	NOEFF No effect.
		Write 1	RST Reset [C2CC.], [PC2CC.], and [C2CFG.*].
9	C1RST	Channel 1 reset.		WO	0
		Write 0	NOEFF No effect.
		Write 1	RST Reset [C1CC.], [PC1CC.], and [C1CFG.*].
8	C0RST	Channel 0 reset.		WO	0
		Write 0	NOEFF No effect.
		Write 1	RST Reset [C0CC], [PC0CC], and [C0CFG].
7:6	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0
5	INTP	Interrupt Phase. This bit field controls when the [RIS.TGT] and [RIS.ZERO] interrupts are set.		RW	0
		0	EARLY [RIS.TGT] and [RIS.ZERO] are set one system clock cycle after [CNTR.*] = TARGET/ZERO.
		1	LATE [RIS.TGT] and [RIS.ZERO] are set one timer clock cycle after [CNTR.*] = TARGET/ZERO.
4:3	CMPDIR	Compare direction. This bit field controls the direction the counter must have in order to set the [RIS.*] compare interrupts.		RW	0x0
		0x0	BOTH Compare [RIS.*] fields are set on up count and down count.
		0x1	UP Compare [RIS.*] fields are only set on up count.
		0x2	DOWN Compare [RIS.*] fields are only set on down count.
		0x3	RESERVED RESERVED
2:0	MODE	Timer mode control The [CNTR.] restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. When writing MODE all internally queued updates to the channels and [TGT.] is cleared. When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example [C0CFG.*].		RW	0x0
		0x0	DIS Disable timer. Updates to counter, channels, and events stop.
		0x1	UP_ONCE Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS.
		0x2	UP_PER Count up periodically. The timer increments from 0 to target value, repeatedly. Period = (target value + 1) * timer clock period
		0x3	UPDWN_PER Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period
		0x4	QDEC The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectively as PHA, PHB and IDX inputs. IDX can be turned off by setting [C2CFG.EDGE] = NONE. The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in [PRECFG.*].
		0x5	SYNC_UP_ONCE Start counting up once synchronous to another LGPT, selected within [STARTCFG.*]. The timer is started by setting [CTL.MODE] = UP_ONCE automatically. It then functions as a normal timer in [CTL.MODE] = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS.
		0x6	SYNC_UP_PER Start counting up periodically synchronous to another LGPT, selected within [STARTCFG.]. The timer is started by setting [CTL.MODE] = UP_PER automatically. It then operates as a normal timer in [CTL.MODE] = UP_PER, incrementing from 0 to target value, repeatedly. Period = (target value 2) * timer clock period
		0x7	SYNC_UPDWN_PER Start counting up and down periodically synchronous to another LGPT, selected within [STARTCFG.]. The timer is started by setting [CTL.MODE] = UPDWN_PER automatically. It then operates as a normal timer in [CTL.MODE] = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly. Period = (target value 2) * timer clock period

:GPTIMER:OUTCTL

Address offset	0x0000 0010
Description	Output Control Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected. An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time. All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an additional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see [IOCTL.*].
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7	SETOUT3	Set output 3. Write 1 to set output 3.	WO	0
6	CLROUT3	Clear output 3. Write 1 to clear output 3.	WO	0
5	SETOUT2	Set output 2. Write 1 to set output 2.	WO	0
4	CLROUT2	Clear output 2. Write 1 to clear output 2.	WO	0
3	SETOUT1	Set output 1. Write 1 to set output 1.	WO	0
2	CLROUT1	Clear output 1. Write 1 to clear output 1.	WO	0
1	SETOUT0	Set output 0. Write 1 to set output 0.	WO	0
0	CLROUT0	Clear output 0. Write 1 to clear output 0.	WO	0

:GPTIMER:CNTR

Address offset	0x0000 0014
Description	Counter The counter of this timer. After [CTL.MODE] is set the counter updates at the rate specified in [PRECFG.*].
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Current counter value. If [CTL.MODE] = QDEC this can be used to set the initial counter value during QDEC.			RW	0x0000 0000

:GPTIMER:PRECFG

Address offset	0x0000 0018
Description	Clock Prescaler Configuration This register is used to set the timer clock period. The prescaler is a counter which counts down from the value [TICKDIV]. When the prescaler counter reaches zero, [CNTR.*] is updated. The field [TICKDIV] effectively divides the prescaler tick source. The timer clock frequency can be calculated as [TICKSRC]/([TICKDIV]+1).
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:8	TICKDIV	Tick division. [TICKDIV] determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by [TICKSRC] divided by ([TICKDIV] + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256.		RW	0x00
7:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	TICKSRC	Prescaler tick source. [TICKSRC] determines the source which decrements the prescaler.		RW	0x0
		0x0	CLK Prescaler is updated at the system clock.
		0x1	RISE_TICK Prescaler is updated at the rising edge of TICKEN.
		0x2	FALL_TICK Prescaler is updated at the falling edge of TICKEN.
		0x3	BOTH_TICK Prescaler is updated at both edges of TICKEN.

:GPTIMER:PREEVENT

Address offset	0x0000 001C
Description	Prescaler Event This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	VAL	Sets the HIGH time of the prescaler event output. Event goes high when the prescaler counter equals [VAL]. Event goes low when prescaler counter is 0. Note: - Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC. - If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer.	RW	0x00

:GPTIMER:CHFILT

Address offset	0x0000 0020
Description	Channel Input Filter This register is used to configure the filter on the channel inputs. The configuration is for all inputs. The filter is enabled when a channel is in capture mode. The input to the filter is passed to the edge detection logic if [LOAD] + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample. If two consecutive samples are unequal, the filter counter restarts from [LOAD]. If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic. The channel filter should only be configured while the [CTL.MODE] = DIS. Configuring the filter while the timer is running can result in unexpected behavior.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:8	LOAD	The input of the channel filter is passed to the edge detection logic after [LOAD] + 1 consecutive equal samples.		RW	0x00
7:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
1:0	MODE	Channel filter mode		RW	0x0
		0x0	BYPASS Filter is bypassed. No Filter is used.
		0x1	CLK Filter is clocked by system clock.
		0x2	TICKSRC Filter is clocked by [PRECFG.TICKSRC].
		0x3	TIMERCLK Filter is clocked by timer clock.

:GPTIMER:FAULT

Address offset	0x0000 0024
Description	Fault This register is used to configure the fault input logic. Primary use scenario is to select [CTL] before starting the timer. Follow these steps to configure [CTL] while [CTL.MODE] is different from DIS: - Set [C0CFG.EDGE] to NONE. - Configure [CTL]. - Wait for three system clock periods before setting [C0CFG.EDGE] different from NONE. These steps prevent fault detection caused by expired signal values in synchronize and edge-detection circuit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RES	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1:0	CTL	Fault control On active fault input the counter can optionally stop. If the counter stops this is done by hardware, software must then restart the timer if wanted. The fault input overrides channel 0 IOC input when [CTL] != DIS. This means that channel 0 receives fault as input signal when [C0CFG.INPUT] = IO and [CTL] != DIS. [CHFILT.] can be used to avoid glitching on the fault input. Fault is level triggered, the polarity is set by the [C0CFG.EDGE] field. Here [C0CFG.EDGE] = RISE gives active high and [C0CFG.EDGE] = FALL gives active low polarity. Fault is typically used together with [PARK.] to stop the PWM signal to an external motor control circuit safely. Configure [PARK.] to ensure predefined values of the PWM outputs. If [CTL] != DIS the [RIS.FAULT] interrupt is set immediately when the fault input is active while [CTL.MODE] != DIS. The three modes of fault is described below: [CTL] = IMMEDIATE In this mode the counter stops immediately on an active fault input. This is done by hardware by setting [CTL.MODE] = DIS. To start the counter software must set [CTL.MODE] != DIS. When the counter has stopped, the input synchronizers and the channel filter is not running. This means that if [RIS.FAULT] is cleared it will not be set again while [CTL.MODE] = DIS. [CTL] = ZEROCOND In this mode the counter stops when [CNTR.] = 0 after an active fault input. If the [RIS.FAULT] interrupt has been cleared by software before [CNTR.*] = 0, and the fault input is inactive, the counter will continue as normal. When the counter stops on zero, it can be started again by clearing the [RIS.FAULT] interrupt if the fault input is inactive. To change the counter mode set [CTL.MODE] = DIS, clear the [RIS.FAULT] interrupt, then start timer in wanted mode. [CTL] = IRQ In this mode only the [RIS.FAULT] flag is set on an active fault input.		RW	0x0
		0x0	DIS Disable. The timer ignores fault.
		0x1	IMMEDIATE Immediate reaction. The counter stops immediately on fault.
		0x2	ZERCOND Zero condition. The counter stops when [CNTR.*] = 0.
		0x3	IRQ Interrupt request. Only set [RIS.FAULT] on active fault.

:GPTIMER:PARK

Address offset	0x0000 0028
Description	Park This register configures how the outputs should be set in Park mode. Park mode is either entered by debug halt or fault. Park mode is activated when the counter stops. Park mode is inactive when the counter starts. When park mode is active all outputs are set to their predefined states. For IO output signals which have enabled dead band, a dead band insertion will be done before switching to the predefined state.
Type	RW

Bits	Field Name	Description		Type	Reset
31:10	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00 0000
9	IOCPS3	IO Complementary Park State 3 Park state for IO Complementary output 3.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
8	IOPS3	IO Park State 3 Park state for IO output 3.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
7	IOCPS2	IO Complementary Park State 2 Park state for IO Complementary output 2.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
6	IOPS2	IO Park State 2 Park state for IO output 2.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
5	IOCPS1	IO Complementary Park State 1 Park state for IO Complementary output 1.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
4	IOPS1	IO Park State 1 Park state for IO output 1.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
3	IOCPS0	IO Complementary Park State 0 Park state for IO Complementary output 0.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
2	IOPS0	IO Park State 0 Park state for IO output 0.		RW	0
		0	LOW Output is set low in park mode.
		1	HIGH Output is set high in park mode.
1:0	CTL	Park Control.		RW	0x0
		0x0	DIS Disable park mode.
		0x1	FAULT Enter park mode on fault.
		0x2	DEBUG Enter park mode on debug.
		0x3	BOTH Enter parkmode on fault or debug.

:GPTIMER:DBDLY

Address offset	0x0000 002C
Description	Dead Band Delay This register is used to insert a dead band delay when generating complementary PWM signals. To enable dead band, on for example IO output 0, create a reference PWM signal on Output 0, then set [DBCTL.IOC0] = EN. TBD: 12-bit width fall delay and rise delay may be excessive, if 8-bits are enough we can join DBDLY and DBCTL.
Type	RW

Bits	Field Name	Description	Type	Reset
31:28	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0
27:16	FALLDLY	Fall delay. The number of system clock periods inserted between the fall of the dead band reference signal and the rise of the inverted output signal.	RW	0x000
15:12	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0
11:0	RISEDLY	Rise delay. The number of system clock periods inserted between the rise of the dead band reference signal and the rise of the output signal.	RW	0x000

:GPTIMER:DBCTL

Address offset	0x0000 0030
Description	Dead Band Control This register is used to enable dead band for IOC outputs.
Type	RW

Bits	Field Name	Description		Type	Reset
31:4	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000 0000
3	IO3	Enable dead band on IO and IO complementary output 3.		RW	0
		0	DIS Disable
		1	EN Enable
2	IO2	Enable dead band on IO and IO complementary output 2.		RW	0
		0	DIS Disable
		1	EN Enable
1	IO1	Enable dead band on IO and IO complementary output 1.		RW	0
		0	DIS Disable
		1	EN Enable
0	IO0	Enable dead band on IO and IO complementary output 0.		RW	0
		0	DIS Disable
		1	EN Enable

:GPTIMER:QDECSTAT

Address offset	0x0000 0034
Description	Quadrature Decoder Status This register can be used during QDEC mode to check the status of the quadrature decoder.
Type	RO

Bits	Field Name	Description		Type	Reset
31:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	DBLTRANS	Double transition		RO	0
		Read 0	NONE Single or no transition on phase inputs.
		Read 1	DBL Double transition on phase inputs.
0	QDIR	Direction of count during QDEC mode.		RO	0
		Read 0	UP Up (PHA leads PHB)
		Read 1	DOWN Down (PHB leads PHA)

:GPTIMER:IRGEN

Address offset	0x0000 0038
Description	IR Generation Use this register to generate IR codes. When [CTL] = 1, an AND gate is enabled between IO output 0 in LGPT0 and IC output 0 in LGPT1. The output of the gate overrides IO output 0 in LGPT0. See [OUTCTL.] for explanation of outputs. To generate IR codes let LGPT0 generate the carrier wave on output 0. Set this output as tick input of LGPT1, with [PRECFG.TICKSRC] = FALL_TICK. Generate wanted IR codes by adjusting LGPT1 [PTGT.] and [PC0CC.*].
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
0	CTL	Control		RW	0
		0	DIS Disable.
		1	EN Enable.

:GPTIMER:DMA

Address offset	0x0000 003C
Description	Direct Memory Access This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write). Choose DMA request source by setting the [REQ] field. The setting of the corresponding interrupt in the [RIS.] registers also sets the DMA request. Upon a DMA request defined by [REQ] an internal address pointer is set to [ADDRESS]4. Every access to [DMARW.*] will increment the internal pointer by 4 such that the next DMA access will be to the next register. The internal pointer will stop after [RWC] increments. Further access will be ignored.
Type	RW

Bits	Field Name	Description		Type	Reset
31:20	RESERVED_3	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x000
19:16	RWC	The read/write counter. RWC+1 is the number of times the DMA can access (read/write) the [DMARW] register. For each DMA access to [DMARW] an internal counter is incremented, writing to the next address field. [ADDRESS] + 4*[RWC] is the final register address which can be accessed by the DMA.		RW	0x0
15	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
14:8	ADDRESS	The base address which the DMA access when reading/writing [DMARW]. The base address is set by taking the 9 LSB of the physical address and divide by 4. For example, if you wanted the [ADDRESS] to point to the [PTGT] register you should set [ADDRESS] = 0x0FC/4.		RW	0x00
7:3	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x00
2:0	REQ	DMA request trigger		RW	0x0
		0x0	DIS Disabled
		0x1	TGT Setting of [RIS.TGT] generates a DMA request.
		0x2	ZERO Setting of [RIS.ZERO] generates a DMA request.
		0x3	FAULT Setting of [RIS.FAULT] generates a DMA request.
		0x4	C0CC Setting of [RIS.C0CC] generates a DMA request.
		0x5	C1CC Setting of [RIS.C1CC] generates a DMA request.
		0x6	C2CC Setting of [RIS.C2CC] generates a DMA request.
		0x7	C3CC Setting of [RIS.C3CC] generates a DMA request.

:GPTIMER:DMARW

Address offset	0x0000 0040
Description	Direct Memory Access This register is used by the DMA to access (read/write) register inside this LGPT module. Each access to this register will increment the internal DMA address counter. See [DMA.*] for description.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	DMA read write value. The value that is read/written from/to the registers.			RW	0x0000 0000

:GPTIMER:ADCTRG

Address offset	0x0000 0044
Description	ADC Trigger This register is used to enable ADC trigger from the timer. Choose ADC trigger source by setting the [SRC] field. The setting of the corresponding interrupt in the [RIS.*] registers also sets the ADC trigger.
Type	RW

Bits	Field Name	Description		Type	Reset
31:3	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
2:0	SRC	ADC request trigger		RW	0x0
		0x0	DIS Disabled
		0x1	TGT Setting of [RIS.TGT] generates an ADC trigger.
		0x2	ZERO Setting of [RIS.ZERO] generates an ADC trigger.
		0x3	FAULT Setting of [RIS.FAULT] generates an ADC trigger.
		0x4	C0CC Setting of [RIS.C0CC] generates an ADC trigger.
		0x5	C1CC Setting of [RIS.C1CC] generates an ADC trigger.
		0x6	C2CC Setting of [RIS.C2CC] generates an ADC trigger.
		0x7	C3CC Setting of [RIS.C3CC] generates an ADC trigger.

:GPTIMER:IOCTL

Address offset	0x0000 0048
Description	IO Controller This register controls the IO outputs.
Type	RW

Bits	Field Name	Description		Type	Reset
31:16	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000
15:14	COUT3	IO complementary output 3 control This bit field controls IO complementary output 3.		RW	0x0
		0x0	NRM Normal output. The IO complementary output is not changed.
		0x1	LOW Driven low. The IO complementary output is driven low.
		0x2	HIGH Driven high. The IO complementary output is driven high.
		0x3	INV Inverted value. The IO complementary output is inverted.
13:12	OUT3	IO output 3 control This bit field controls IO output 3.		RW	0x0
		0x0	NRM Normal output. The IO output is not changed.
		0x1	LOW Driven low. The IO output is driven low.
		0x2	HIGH Driven high. The IO output is driven high.
		0x3	INV Inverted value. The IO output is inverted.
11:10	COUT2	IO complementary output 2 control This bit field controls IO complementary output 2.		RW	0x0
		0x0	NRM Normal output. The IO complementary output is not changed.
		0x1	LOW Driven low. The IO complementary output is driven low.
		0x2	HIGH Driven high. The IO complementary output is driven high.
		0x3	INV Inverted value. The IO complementary output is inverted.
9:8	OUT2	IO output 2 control This bit field controls IO output 2.		RW	0x0
		0x0	NRM Normal output. The IO output is not changed.
		0x1	LOW Driven low. The IO output is driven low.
		0x2	HIGH Driven high. The IO output is driven high.
		0x3	INV Inverted value. The IO output is inverted.
7:6	COUT1	IO complementary output 1 control This bit field controls IO complementary output 1.		RW	0x0
		0x0	NRM Normal output. The IO complementary output is not changed.
		0x1	LOW Driven low. The IO complementary output is driven low.
		0x2	HIGH Driven high. The IO complementary output is driven high.
		0x3	INV Inverted value. The IO complementary output is inverted.
5:4	OUT1	IO output 1 control This bit field controls IO output 1.		RW	0x0
		0x0	NRM Normal output. The IO output is not changed.
		0x1	LOW Driven low. The IO output is driven low.
		0x2	HIGH Driven high. The IO output is driven high.
		0x3	INV Inverted value. The IO output is inverted.
3:2	COUT0	IO complementary output 0 control This bit field controls IO complementary output 0.		RW	0x0
		0x0	NRM Normal output. The IO complementary output is not changed.
		0x1	LOW Driven low. The IO complementary output is driven low.
		0x2	HIGH Driven high. The IO complementary output is driven high.
		0x3	INV Inverted value. The IO complementary output is inverted.
1:0	OUT0	IO output 0 control This bit field controls IO output 0.		RW	0x0
		0x0	NRM Normal output. The IO output is not changed.
		0x1	LOW Driven low. The IO output is driven low.
		0x2	HIGH Driven high. The IO output is driven high.
		0x3	INV Inverted value. The IO output is inverted.

:GPTIMER:IMASK

Address offset	0x0000 0068
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.] to [MIS.] when the corresponding bit-fields are set to 1.
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	C3CC	Enable [RIS.C3CC] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
10	C2CC	Enable [RIS.C2CC] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
9	C1CC	Enable [RIS.C1CC] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
8	C0CC	Enable [RIS.C0CC] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	FAULT	Enable [RIS.FAULT] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
5	IDX	Enable [RIS.IDX] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
4	DIRCHNG	Enable [RIS.DIRCHNG] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
3	CNTRCHNG	Enable [RIS.CNTRCHNG] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
2	DBLTRANS	Enable [RIS.DBLTRANS] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
1	ZERO	Enable [RIS.ZERO] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable
0	TGT	Enable [RIS.TGT] interrupt.		RW	0
		0	DIS Disable
		1	EN Enable

:GPTIMER:RIS

Address offset	0x0000 006C
Description	Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	C3CC	Status of the [C3CC] interrupt. The interrupt is set when [C3CC] has capture or compare event.		RO	0
		Read 0	DIS Disable
		Read 1	EN Enable
10	C2CC	Status of the [C2CC] interrupt. The interrupt is set when [C2CC] has capture or compare event.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
9	C1CC	Status of the [C1CC] interrupt. The interrupt is set when [C1CC] has capture or compare event.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
8	C0CC	Status of the [C0CC] interrupt. The interrupt is set when [C0CC] has capture or compare event.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	FAULT	Status of the [FAULT] interrupt. The interrupt is set immediately on active fault input.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
5	IDX	Status of the [IDX] interrupt. The interrupt is set when [IDX] is active.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
4	DIRCHNG	Status of the [DIRCHNG] interrupt. The interrupt is set when the direction of the counter changes.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
3	CNTRCHNG	Status of the [CNTRCHNG] interrupt. The interrupt is set when the counter increments or decrements.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
2	DBLTRANS	Status of the [DBLTRANS] interrupt. The interrupt is set when a double transition has happened during QDEC mode.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
1	ZERO	Status of the [ZERO] interrupt. The interrupt is set when [CNTR.*] = 0.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
0	TGT	Status of the [TGT] interrupt. The interrupt is set when [CNTR.] = [TGT.].		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set

:GPTIMER:MIS

Address offset	0x0000 0070
Description	Masked interrupt status. This register is simply a bit-wise AND of the contents of [IMASK.] and RIS.] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
Type	RO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	C3CC	Masked status of the [RIS.C3CC] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
10	C2CC	Masked status of the [RIS.C2CC] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
9	C1CC	Masked status of the [RIS.C1CC] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
8	C0CC	Masked status of the [RIS.C0CC] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	FAULT	Masked status of the [RIS.FAULT] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
5	IDX	Masked status of the [RIS.IDX] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
4	DIRCHNG	Masked status of the [RIS.DIRCHNG] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
3	CNTRCHNG	Masked status of the [RIS.CNTRCHNG] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
2	DBLTRANS	Masked status of the [RIS.DBLTRANS] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
1	ZERO	Masked status of the [RIS.ZERO] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set
0	TGT	Masked status of the [RIS.TGT] interrupt.		RO	0
		Read 0	CLR Cleared
		Read 1	SET Set

:GPTIMER:ISET

Address offset	0x0000 0074
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.] bit also gets set. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets set.
Type	WO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0 0000
11	C3CC	Set the [RIS.C3CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
10	C2CC	Set the [RIS.C2CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
9	C1CC	Set the [RIS.C1CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
8	C0CC	Set the [RIS.C0CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0
6	FAULT	Set the [RIS.FAULT] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
5	IDX	Set the [RIS.IDX] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
4	DIRCHNG	Set the [RIS.DIRCHNG] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
3	CNTRCHNG	Set the [RIS.CNTRCHNG] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
2	DBLTRANS	Set the [RIS.DBLTRANS] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
1	ZERO	Set the [RIS.ZERO] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
0	TGT	Set the [RIS.TGT] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set

:GPTIMER:ICLR

Address offset	0x0000 0078
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.] bit also gets cleared. If the corresponding [IMASK.] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
Type	WO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0 0000
11	C3CC	Clear the [RIS.C3CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
10	C2CC	Clear the [RIS.C2CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
9	C1CC	Clear the [RIS.C1CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
8	C0CC	Clear the [RIS.C0CC] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0
6	FAULT	Clear the [RIS.FAULT] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
5	IDX	Clear the [RIS.IDX] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
4	DIRCHNG	Clear the [RIS.DIRCHNG] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
3	CNTRCHNG	Clear the [RIS.CNTRCHNG] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
2	DBLTRANS	Clear the [RIS.DBLTRANS] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
1	ZERO	Clear the [RIS.ZERO] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
0	TGT	Clear the [RIS.TGT] interrupt.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear

:GPTIMER:IMSET

Address offset	0x0000 007C
Description	Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
Type	WO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0 0000
11	C3CC	Set the [MIS.C3CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
10	C2CC	Set the [MIS.C2CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
9	C1CC	Set the [MIS.C1CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
8	C0CC	Set the [MIS.C0CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0
6	FAULT	Set the [MIS.FAULT] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
5	IDX	Set the [MIS.IDX] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
4	DIRCHNG	Set the [MIS.DIRCHNG] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
3	CNTRCHNG	Set the [MIS.CNTRCHNG] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
2	DBLTRANS	Set the [MIS.DBLTRANS] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
1	ZERO	Set the [MIS.ZERO] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set
0	TGT	Set the [MIS.TGT] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	SET Set

:GPTIMER:IMCLR

Address offset	0x0000 0080
Description	Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
Type	WO

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0x0 0000
11	C3CC	Clear the [MIS.C3CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
10	C2CC	Clear the [MIS.C2CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
9	C1CC	Clear the [MIS.C1CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
8	C0CC	Clear the [MIS.C0CC] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		WO	0
6	FAULT	Clear the [MIS.FAULT] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
5	IDX	Clear the [MIS.IDX] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
4	DIRCHNG	Clear the [MIS.DIRCHNG] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
3	CNTRCHNG	Clear the [MIS.CNTRCHNG] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
2	DBLTRANS	Clear the [MIS.DBLTRANS] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
1	ZERO	Clear the [MIS.ZERO] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear
0	TGT	Clear the [MIS.TGT] mask.		WO	0
		Write 0	NO_EFFECT No effect
		Write 1	CLR Clear

:GPTIMER:EMU

Address offset	0x0000 0084
Description	Debug control This register can be used to freeze the timer when CPU halts when [HALT] is set to 1. When [HALT] is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, [PARK.], if the timer has this register, should be configured additionally. If this timer does not have the [PARK.] register a predefined output value during CPU halt is not possible.
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0000 0000
1	CTL	Halt control. Configure when the counter shall stop upon CPU halt. This bitfield only applies if [HALT] = 1.		RW	0
		0	IMMEDIATE Immediate reaction. The counter stops immediately on debug halt.
		1	ZERCOND Zero condition. The counter stops when [CNTR.*] = 0.
0	HALT	Halt LGPT when CPU is halted in debug.		RW	0
		0	DIS Disable.
		1	EN Enable.

:GPTIMER:C0CFG

Address offset	0x0000 00C0
Description	Channel 0 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS. - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	OUT3	Output 3 enable. When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 0 does not control output 3.
		1	EN Channel 0 controls output 3.
10	OUT2	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 0 does not control output 2.
		1	EN Channel 0 controls output 2.
9	OUT1	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 0 does not control output 1.
		1	EN Channel 0 controls output 1.
8	OUT0	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 0 does not control output 0.
		1	EN Channel 0 controls output 0.
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	INPUT	Select channel input.		RW	0
		0	EV Event fabric
		1	IO IO controller
5:4	EDGE	Determines the edge that triggers the channel input event. This happens post filter.		RW	0x0
		0x0	NONE Input is turned off.
		0x1	RISE Input event is triggered at rising edge.
		0x2	FALL Input event is triggered at falling edge.
		0x3	BOTH Input event is triggered at both edges.
3:0	CCACT	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C0CC.*].		RW	0x0
		0x0	DIS Disable channel.
		0x1	SET_ON_CAPT_DIS Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C0CC.VAL]. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while [CTL.MODE] is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit.
		0x2	CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are set when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x3	SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are cleared when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x4	CLR_ON_CMP_DIS Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x5	SET_ON_CMP_DIS Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x6	TGL_ON_CMP_DIS Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x7	PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when [C0CC.VAL] = [CNTR.VAL]. - Disable channel. The output is high for two timer clock periods.
		0x8	PER_PULSE_WIDTH_MEAS Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and [RIS.C0CC] when [C0CC.VAL] contains signal period and [PC0CC.VAL] contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when [C0CC.VAL] contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
		0x9	SET_ON_CAPT Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C0CC.VAL].
		0xA	CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When [C0CC.VAL] <= [TGT.VAL]: Duty cycle = 1 - ( [C0CC.VAL] / [TGT.VAL] ). When [C0CC.VAL] > [TGT.VAL]: Duty cycle = 0. Enabled outputs are set when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xB	SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When [C0CC.VAL] <= [TGT.VAL]: Duty cycle = [C0CC.VAL] / ( [TGT.VAL] + 1 ). When [C0CC.VAL] > [TGT.VAL]: Duty cycle = 1. Enabled outputs are cleared when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xC	CLR_ON_CMP Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when [C0CC.VAL] = [CNTR.VAL].
		0xD	SET_ON_CMP Set on compare repeatedly. Channel function sequence: - Set enabled outputs when [C0CC.VAL] = [CNTR.VAL].
		0xE	TGL_ON_CMP Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
		0xF	PULSE_ON_CMP Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when [C0CC.VAL] = [CNTR.VAL]. The output is high for two timer clock periods.

:GPTIMER:C1CFG

Address offset	0x0000 00C4
Description	Channel 1 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS. - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	OUT3	Output 3 enable. When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 1 does not control output 3.
		1	EN Channel 1 controls output 3.
10	OUT2	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 1 does not control output 2.
		1	EN Channel 1 controls output 2.
9	OUT1	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 1 does not control output 1.
		1	EN Channel 1 controls output 1.
8	OUT0	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 1 does not control output 0.
		1	EN Channel 1 controls output 0.
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	INPUT	Select channel input.		RW	0
		0	EV Event fabric
		1	IO IO controller
5:4	EDGE	Determines the edge that triggers the channel input event. This happens post filter.		RW	0x0
		0x0	NONE Input is turned off.
		0x1	RISE Input event is triggered at rising edge.
		0x2	FALL Input event is triggered at falling edge.
		0x3	BOTH Input event is triggered at both edges.
3:0	CCACT	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C1CC.*].		RW	0x0
		0x0	DIS Disable channel.
		0x1	SET_ON_CAPT_DIS Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C1CC.VAL]. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while [CTL.MODE] is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit.
		0x2	CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are set when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x3	SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are cleared when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x4	CLR_ON_CMP_DIS Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x5	SET_ON_CMP_DIS Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x6	TGL_ON_CMP_DIS Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x7	PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when [C1CC.VAL] = [CNTR.VAL]. - Disable channel. The output is high for two timer clock periods.
		0x8	PER_PULSE_WIDTH_MEAS Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and [RIS.C1CC] when [C1CC.VAL] contains signal period and [PC1CC.VAL] contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when [C1CC.VAL] contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
		0x9	SET_ON_CAPT Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C1CC.VAL].
		0xA	CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When [C1CC.VAL] <= [TGT.VAL]: Duty cycle = 1 - ( [C1CC.VAL] / [TGT.VAL] ). When [C1CC.VAL] > [TGT.VAL]: Duty cycle = 0. Enabled outputs are set when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xB	SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When [C1CC.VAL] <= [TGT.VAL]: Duty cycle = [C1CC.VAL] / ( [TGT.VAL] + 1 ). When [C1CC.VAL] > [TGT.VAL]: Duty cycle = 1. Enabled outputs are cleared when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xC	CLR_ON_CMP Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when [C1CC.VAL] = [CNTR.VAL].
		0xD	SET_ON_CMP Set on compare repeatedly. Channel function sequence: - Set enabled outputs when [C1CC.VAL] = [CNTR.VAL].
		0xE	TGL_ON_CMP Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
		0xF	PULSE_ON_CMP Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when [C1CC.VAL] = [CNTR.VAL]. The output is high for two timer clock periods.

:GPTIMER:C2CFG

Address offset	0x0000 00C8
Description	Channel 2 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS. - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	OUT3	Output 3 enable. When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 2 does not control output 3.
		1	EN Channel 2 controls output 3.
10	OUT2	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 2 does not control output 2.
		1	EN Channel 2 controls output 2.
9	OUT1	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 2 does not control output 1.
		1	EN Channel 2 controls output 1.
8	OUT0	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 2 does not control output 0.
		1	EN Channel 2 controls output 0.
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	INPUT	Select channel input.		RW	0
		0	EV Event fabric
		1	IO IO controller
5:4	EDGE	Determines the edge that triggers the channel input event. This happens post filter.		RW	0x0
		0x0	NONE Input is turned off.
		0x1	RISE Input event is triggered at rising edge.
		0x2	FALL Input event is triggered at falling edge.
		0x3	BOTH Input event is triggered at both edges.
3:0	CCACT	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C2CC.*].		RW	0x0
		0x0	DIS Disable channel.
		0x1	SET_ON_CAPT_DIS Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C2CC.VAL]. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while [CTL.MODE] is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit.
		0x2	CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are set when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x3	SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are cleared when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x4	CLR_ON_CMP_DIS Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x5	SET_ON_CMP_DIS Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x6	TGL_ON_CMP_DIS Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x7	PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when [C2CC.VAL] = [CNTR.VAL]. - Disable channel. The output is high for two timer clock periods.
		0x8	PER_PULSE_WIDTH_MEAS Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and [RIS.C2CC] when [C2CC.VAL] contains signal period and [PC2CC.VAL] contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when [C2CC.VAL] contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
		0x9	SET_ON_CAPT Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C2CC.VAL].
		0xA	CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When [C2CC.VAL] <= [TGT.VAL]: Duty cycle = 1 - ( [C2CC.VAL] / [TGT.VAL] ). When [C2CC.VAL] > [TGT.VAL]: Duty cycle = 0. Enabled outputs are set when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xB	SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When [C2CC.VAL] <= [TGT.VAL]: Duty cycle = [C2CC.VAL] / ( [TGT.VAL] + 1 ). When [C2CC.VAL] > [TGT.VAL]: Duty cycle = 1. Enabled outputs are cleared when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xC	CLR_ON_CMP Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when [C2CC.VAL] = [CNTR.VAL].
		0xD	SET_ON_CMP Set on compare repeatedly. Channel function sequence: - Set enabled outputs when [C2CC.VAL] = [CNTR.VAL].
		0xE	TGL_ON_CMP Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
		0xF	PULSE_ON_CMP Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when [C2CC.VAL] = [CNTR.VAL]. The output is high for two timer clock periods.

:GPTIMER:C3CFG

Address offset	0x0000 00CC
Description	Channel 3 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS. - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type	RW

Bits	Field Name	Description		Type	Reset
31:12	RESERVED_2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0x0 0000
11	OUT3	Output 3 enable. When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 3 does not control output 3.
		1	EN Channel 3 controls output 3.
10	OUT2	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 3 does not control output 2.
		1	EN Channel 3 controls output 2.
9	OUT1	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 3 does not control output 1.
		1	EN Channel 3 controls output 1.
8	OUT0	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.		RW	0
		0	DIS Channel 3 does not control output 0.
		1	EN Channel 3 controls output 0.
7	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.		RO	0
6	INPUT	Select channel input.		RW	0
		0	EV Event fabric
		1	IO IO controller
5:4	EDGE	Determines the edge that triggers the channel input event. This happens post filter.		RW	0x0
		0x0	NONE Input is turned off.
		0x1	RISE Input event is triggered at rising edge.
		0x2	FALL Input event is triggered at falling edge.
		0x3	BOTH Input event is triggered at both edges.
3:0	CCACT	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C3CC.*].		RW	0x0
		0x0	DIS Disable channel.
		0x1	SET_ON_CAPT_DIS Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C3CC.VAL]. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while [CTL.MODE] is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit.
		0x2	CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are set when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x3	SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel. Enabled outputs are cleared when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
		0x4	CLR_ON_CMP_DIS Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x5	SET_ON_CMP_DIS Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x6	TGL_ON_CMP_DIS Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel.
		0x7	PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when [C3CC.VAL] = [CNTR.VAL]. - Disable channel. The output is high for two timer clock periods.
		0x8	PER_PULSE_WIDTH_MEAS Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and [RIS.C3CC] when [C3CC.VAL] contains signal period and [PC3CC.VAL] contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when [C3CC.VAL] contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + [PRECFG.TICKDIV] ) * timer clock period. - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
		0x9	SET_ON_CAPT Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy [CNTR.VAL] to [C3CC.VAL].
		0xA	CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When [C3CC.VAL] <= [TGT.VAL]: Duty cycle = 1 - ( [C3CC.VAL] / [TGT.VAL] ). When [C3CC.VAL] > [TGT.VAL]: Duty cycle = 0. Enabled outputs are set when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xB	SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when [CNTR.VAL] = 0. - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL]. Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When [C3CC.VAL] <= [TGT.VAL]: Duty cycle = [C3CC.VAL] / ( [TGT.VAL] + 1 ). When [C3CC.VAL] > [TGT.VAL]: Duty cycle = 1. Enabled outputs are cleared when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
		0xC	CLR_ON_CMP Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when [C3CC.VAL] = [CNTR.VAL].
		0xD	SET_ON_CMP Set on compare repeatedly. Channel function sequence: - Set enabled outputs when [C3CC.VAL] = [CNTR.VAL].
		0xE	TGL_ON_CMP Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
		0xF	PULSE_ON_CMP Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when [C3CC.VAL] = [CNTR.VAL]. The output is high for two timer clock periods.

:GPTIMER:PTGT

Address offset	0x0000 00FC
Description	Pipeline Target A read or write to this register will clear the [RIS.ZERO] and [RIS.TGT] interrupt. If [CTL.MODE] != QDEC. Target value for next counter period. The timer will copy [PTGT.VAL] to [TGT.VAL] on the upcoming [CNTR.] zero crossing only if [PTGT.VAL] has been written. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If [CTL.MODE] = QDEC The [CNTR.] value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, [CNTR.*] is loaded with zero on IDX. In this mode the VALUE is not loaded into [TGT] on zero crossing.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	The pipleline target value.			RW	0x0000 0000

:GPTIMER:PC0CC

Address offset	0x0000 0100
Description	Pipeline Channel 0 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C0CC] interrupt. Compare mode: An update of VAL will be transferred to [C0CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C0CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C0CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC1CC

Address offset	0x0000 0104
Description	Pipeline Channel 1 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C1CC] interrupt. Compare mode: An update of VAL will be transferred to [C1CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C1CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C1CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC2CC

Address offset	0x0000 0108
Description	Pipeline Channel 2 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C2CC] interrupt. Compare mode: An update of VAL will be transferred to [C2CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C2CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C2CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC3CC

Address offset	0x0000 010C
Description	Pipeline Channel 3 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C3CC] interrupt. Compare mode: An update of VAL will be transferred to [C3CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C3CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C3CFG.EDGE].			RW	0x0000 0000

:GPTIMER:TGT

Address offset	0x0000 013C
Description	Target User defined counter target. A read or write to this register will clear the [RIS.ZERO] and [RIS.TGT] interrupt.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	User defined counter target value.			RW	0xFFFF FFFF

:GPTIMER:C0CC

Address offset	0x0000 0140
Description	Channel 0 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C0CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C0CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C0CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C1CC

Address offset	0x0000 0144
Description	Channel 1 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C1CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C1CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C1CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C2CC

Address offset	0x0000 0148
Description	Channel 2 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C2CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C2CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C2CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C3CC

Address offset	0x0000 014C
Description	Channel 3 Capture Compare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the [RIS.C3CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C3CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C3CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:PTGTNC

Address offset	0x0000 017C
Description	Pipeline Target No Clear Use this register to read or write to [PTGT.*] without clearing the [RIS.ZERO] and [RIS.TGT] interrupt.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	A read or write to this register will not clear the [RIS.TGT] interrupt. If [CTL.MODE] != QDEC. Target value for next counter period. The timer copies VAL to [TGT.VAL] when [CNTR.VAL] becomes 0. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If [CTL.MODE] = QDEC. The [CNTR.VAL] is updated with VAL on IDX. VAL is not loaded into [TGT.VAL] when [CNTR.VAL] becomes 0.			RW	0x0000 0000

:GPTIMER:PC0CCNC

Address offset	0x0000 0180
Description	Pipeline Channel 0 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C0CC] interrupt. Compare mode: An update of VAL will be transferred to [C0CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C0CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C0CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC1CCNC

Address offset	0x0000 0184
Description	Pipeline Channel 1 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C1CC] interrupt. Compare mode: An update of VAL will be transferred to [C1CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C1CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C1CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC2CCNC

Address offset	0x0000 0188
Description	Pipeline Channel 2 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C2CC] interrupt. Compare mode: An update of VAL will be transferred to [C2CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C2CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C2CFG.EDGE].			RW	0x0000 0000

:GPTIMER:PC3CCNC

Address offset	0x0000 018C
Description	Pipeline Channel 3 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C3CC] interrupt. Compare mode: An update of VAL will be transferred to [C3CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When [C3CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C3CFG.EDGE].			RW	0x0000 0000

:GPTIMER:TGTNC

Address offset	0x0000 01BC
Description	Target No Clear Use this register to read or write to [TGT.*] without clearing the [RIS.ZERO] and [RIS.TGT] interrupt.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	User defined counter target value.			RW	0xFFFF FFFF

:GPTIMER:C0CCNC

Address offset	0x0000 01C0
Description	Channel 0 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C0CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C0CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C0CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C1CCNC

Address offset	0x0000 01C4
Description	Channel 1 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C1CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C1CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C1CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C2CCNC

Address offset	0x0000 01C8
Description	Channel 2 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C2CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C2CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C2CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:C3CCNC

Address offset	0x0000 01CC
Description	Channel 3 Capture Compare No Clear
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the [RIS.C3CC] interrupt. Compare mode: VAL is compared against [CNTR.VAL] and an event is generated as specified by [C3CFG.CCACT] when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. [C3CFG.CCACT] determines if VAL is a signal period or a regular capture value.			RW	0x0000 0000

:GPTIMER:CLKCFG

Address offset	0x0000 1000
Description	Clock Enable Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000 0000
0	ENABLE	GPTimer main clock Enable	RW	0